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Searched refs:regCP_ME1_PIPE3_INT_CNTL (Results 1 – 4 of 4) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h485 #define regCP_ME1_PIPE3_INT_CNTL … macro
Dgc_11_0_3_offset.h4450 #define regCP_ME1_PIPE3_INT_CNTL … macro
Dgc_11_0_0_offset.h4238 #define regCP_ME1_PIPE3_INT_CNTL … macro
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c5763 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL); in gfx_v11_0_set_compute_eop_interrupt_state()