| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | mca_v3_0.c | 60 .ras_block = {
86 .ras_block = {
112 .ras_block = {
132 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block); in mca_v3_0_init()
133 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block); in mca_v3_0_init()
134 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block); in mca_v3_0_init()
135 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm; in mca_v3_0_init()
136 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm; in mca_v3_0_init()
137 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm; in mca_v3_0_init()
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| D | amdgpu_umc.c | 38 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
39 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_do_page_retirement()
40 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
42 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
43 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_do_page_retirement()
59 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
144 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_umc_ras_late_init() argument
148 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_umc_ras_late_init()
152 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_umc_ras_late_init()
166 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_umc_ras_late_init()
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| D | amdgpu_nbio.c | 25 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_nbio_ras_late_init() argument
28 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_nbio_ras_late_init()
32 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_nbio_ras_late_init()
43 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_nbio_ras_late_init()
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| D | amdgpu_ras.c | 89 const char *get_ras_block_str(struct ras_common_if *ras_block) in get_ras_block_str() argument
91 if (!ras_block) in get_ras_block_str()
94 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) in get_ras_block_str()
97 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) in get_ras_block_str()
98 return ras_mca_block_string[ras_block->sub_block_index]; in get_ras_block_str()
100 return ras_block_string[ras_block->block]; in get_ras_block_str()
946 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
947 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_ras_get_ecc_info()
948 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()
953 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
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| D | gmc_v9_0.c | 1239 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v9_0_set_umc_funcs()
1241 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v9_0_set_umc_funcs()
1242 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v9_0_set_umc_funcs()
1243 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v9_0_set_umc_funcs()
1244 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v9_0_set_umc_funcs()
1247 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v9_0_set_umc_funcs()
1248 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v9_0_set_umc_funcs()
1251 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v9_0_set_umc_funcs()
1252 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v9_0_set_umc_funcs()
1289 amdgpu_ras_register_ras_block(adev, &adev->mmhub.ras->ras_block); in gmc_v9_0_set_mmhub_ras_funcs()
[all …]
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| D | amdgpu_hdp.h | 28 struct amdgpu_ras_block_object ras_block; member
46 int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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| D | jpeg_v2_5.c | 795 .ras_block = {
811 amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block); in jpeg_v2_5_set_ras_funcs()
813 strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg"); in jpeg_v2_5_set_ras_funcs()
814 adev->jpeg.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in jpeg_v2_5_set_ras_funcs()
815 adev->jpeg.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in jpeg_v2_5_set_ras_funcs()
816 adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm; in jpeg_v2_5_set_ras_funcs()
819 if (!adev->jpeg.ras->ras_block.ras_late_init) in jpeg_v2_5_set_ras_funcs()
820 adev->jpeg.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; in jpeg_v2_5_set_ras_funcs()
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| D | gmc_v11_0.c | 564 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v11_0_set_umc_funcs()
566 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v11_0_set_umc_funcs()
567 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v11_0_set_umc_funcs()
568 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v11_0_set_umc_funcs()
569 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v11_0_set_umc_funcs()
572 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v11_0_set_umc_funcs()
573 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v11_0_set_umc_funcs()
576 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v11_0_set_umc_funcs()
577 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v11_0_set_umc_funcs()
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| D | amdgpu_sdma.c | 99 struct ras_common_if *ras_block) in amdgpu_sdma_ras_late_init() argument
103 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_sdma_ras_late_init()
107 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_sdma_ras_late_init()
119 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_sdma_ras_late_init()
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| D | amdgpu_ras.h | 504 int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
505 void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
616 struct ras_common_if *ras_block);
619 struct ras_common_if *ras_block);
678 const char *get_ras_block_str(struct ras_common_if *ras_block);
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| D | amdgpu_umc.h | 51 struct amdgpu_ras_block_object ras_block; member
88 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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| D | amdgpu_sdma.h | 55 struct amdgpu_ras_block_object ras_block; member
120 struct ras_common_if *ras_block);
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| D | amdgpu_nbio.h | 51 struct amdgpu_ras_block_object ras_block; member
109 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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| D | gmc_v10_0.c | 687 amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block); in gmc_v10_0_set_umc_funcs()
689 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in gmc_v10_0_set_umc_funcs()
690 adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in gmc_v10_0_set_umc_funcs()
691 adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in gmc_v10_0_set_umc_funcs()
692 adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm; in gmc_v10_0_set_umc_funcs()
695 if (!adev->umc.ras->ras_block.ras_late_init) in gmc_v10_0_set_umc_funcs()
696 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init; in gmc_v10_0_set_umc_funcs()
699 if (!adev->umc.ras->ras_block.ras_cb) in gmc_v10_0_set_umc_funcs()
700 adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb; in gmc_v10_0_set_umc_funcs()
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| D | amdgpu_gfx.c | 667 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_gfx_ras_late_init() argument
671 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_gfx_ras_late_init()
675 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_gfx_ras_late_init()
683 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); in amdgpu_gfx_ras_late_init()
688 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_late_init()
704 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && in amdgpu_gfx_process_ras_data_cb()
705 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_gfx_process_ras_data_cb()
706 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_gfx_process_ras_data_cb()
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| D | amdgpu_mca.h | 25 struct amdgpu_ras_block_object ras_block; member
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| D | amdgpu_mmhub.h | 25 struct amdgpu_ras_block_object ras_block; member
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| D | amdgpu_jpeg.h | 45 struct amdgpu_ras_block_object ras_block; member
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| D | amdgpu_xgmi.c | 760 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_xgmi_ras_late_init() argument
766 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_ras_late_init()
768 return amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_xgmi_ras_late_init()
920 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_query_ras_error_count()
960 .ras_block = {
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| D | sdma_v4_0.c | 1799 if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops && in sdma_v4_0_late_init()
1800 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_0_late_init()
1801 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_0_late_init()
2714 .ras_block = {
2735 amdgpu_ras_register_ras_block(adev, &adev->sdma.ras->ras_block); in sdma_v4_0_set_ras_funcs()
2737 strcpy(adev->sdma.ras->ras_block.ras_comm.name, "sdma"); in sdma_v4_0_set_ras_funcs()
2738 adev->sdma.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in sdma_v4_0_set_ras_funcs()
2739 adev->sdma.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in sdma_v4_0_set_ras_funcs()
2740 adev->sdma.ras_if = &adev->sdma.ras->ras_block.ras_comm; in sdma_v4_0_set_ras_funcs()
2743 if (!adev->sdma.ras->ras_block.ras_late_init) in sdma_v4_0_set_ras_funcs()
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| D | amdgpu_gfx.h | 209 struct amdgpu_ras_block_object ras_block; member
415 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
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| D | hdp_v4_0.c | 162 .ras_block = {
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| D | vcn_v2_5.c | 1990 .ras_block = {
2006 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block); in vcn_v2_5_set_ras_funcs()
2008 strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn"); in vcn_v2_5_set_ras_funcs()
2009 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in vcn_v2_5_set_ras_funcs()
2010 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in vcn_v2_5_set_ras_funcs()
2011 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm; in vcn_v2_5_set_ras_funcs()
2014 if (!adev->vcn.ras->ras_block.ras_late_init) in vcn_v2_5_set_ras_funcs()
2015 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init; in vcn_v2_5_set_ras_funcs()
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| D | sdma_v4_4.c | 267 .ras_block = {
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| D | amdgpu_gmc.c | 446 amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block); in amdgpu_gmc_ras_early_init()
447 adev->gmc.xgmi.ras_if = &adev->gmc.xgmi.ras->ras_block.ras_comm; in amdgpu_gmc_ras_early_init()
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