Searched refs:pll_value (Results 1 – 7 of 7) sorted by relevance
42 struct pll_value { struct97 unsigned int sm750_calc_pll_value(unsigned int request, struct pll_value *pll);98 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL);
58 struct pll_value pll; in set_chip_clock()313 struct pll_value *pll) in sm750_calc_pll_value()385 unsigned int sm750_format_pll_reg(struct pll_value *p_PLL) in sm750_format_pll_reg()
79 struct pll_value *pll) in programModeRegisters()212 struct pll_value pll; in ddk750_setModeTiming()
256 pll->pll_value = tmp & Q40_RTC_PLL_MASK; in q40_get_rtc_pll()258 pll->pll_value = -pll->pll_value; in q40_get_rtc_pll()273 int tmp = (pll->pll_value & 31) | (pll->pll_value<0 ? 32 : 0) | in q40_set_rtc_pll()
25 u32 pll_value; member76 value = cs5530_pll_table[0].pll_value; in cs5530_set_dclk_frequency()84 value = cs5530_pll_table[i].pll_value; in cs5530_set_dclk_frequency()
191 u32 pll_value; in gli_set_9750() local201 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()223 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; in gli_set_9750()224 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; in gli_set_9750()225 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()227 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()251 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); in gli_set_9750()
62 int pll_value; /* get/set correction value */ member
