Searched refs:pll_cntl (Results 1 – 6 of 6) sorted by relevance
974 union pll_cntl_u pll_cntl; member1079 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */ in w100_pll_adjust()1080 w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */ in w100_pll_adjust()1081 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */ in w100_pll_adjust()1082 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */ in w100_pll_adjust()1083 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */ in w100_pll_adjust()1084 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */ in w100_pll_adjust()1085 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0; in w100_pll_adjust()1093 w100_pwr_state.pll_cntl.f.pll_dactal = 0xd; in w100_pll_adjust()1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); in w100_pll_adjust()[all …]
64 u8 pll_cntl; member631 par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */ in i740fb_decode_var()828 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl); in i740fb_set_par()
67 pll_cntl: syscon@fffe0008 { label
68 pll_cntl: syscon@100000008 { label
78 pll_cntl: syscon@10000008 { label
