Home
last modified time | relevance | path

Searched refs:pipe_mask (Results 1 – 25 of 25) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/i915/
Di915_pci.c44 #define NO_DISPLAY .__runtime.pipe_mask = 0
176 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
198 .__runtime.pipe_mask = BIT(PIPE_A), \
241 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
332 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
386 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
417 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
469 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
533 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
628 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dintel_device_info.c378 runtime->pipe_mask = 0; in intel_device_info_runtime_init()
383 runtime->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
390 runtime->pipe_mask &= ~BIT(PIPE_A); in intel_device_info_runtime_init()
395 runtime->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
399 runtime->pipe_mask &= ~BIT(PIPE_C); in intel_device_info_runtime_init()
405 runtime->pipe_mask &= ~BIT(PIPE_D); in intel_device_info_runtime_init()
Di915_irq.h71 u8 pipe_mask);
73 u8 pipe_mask);
Dintel_device_info.h243 u8 pipe_mask; member
Di915_drv.h953 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
955 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
Di915_irq.c3204 u8 pipe_mask) in gen8_irq_power_well_post_enable() argument
3219 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
3228 u8 pipe_mask) in gen8_irq_power_well_pre_disable() argument
3240 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c243 unsigned int pipe_mask = BIT(crtc->pipe); in intel_enable_shared_dpll() local
252 if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) || in intel_enable_shared_dpll()
253 drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask)) in intel_enable_shared_dpll()
256 pll->active_mask |= pipe_mask; in intel_enable_shared_dpll()
289 unsigned int pipe_mask = BIT(crtc->pipe); in intel_disable_shared_dpll() local
299 if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask), in intel_disable_shared_dpll()
312 pll->active_mask &= ~pipe_mask; in intel_disable_shared_dpll()
343 if (shared_dpll[i].pipe_mask == 0) { in intel_find_shared_dpll()
356 shared_dpll[i].pipe_mask, in intel_find_shared_dpll()
385 if (shared_dpll[id].pipe_mask == 0) in intel_reference_shared_dpll()
[all …]
Dintel_ddi.c716 u8 *pipe_mask, bool *is_dp_mst) in intel_ddi_get_encoder_pipes() argument
726 *pipe_mask = 0; in intel_ddi_get_encoder_pipes()
748 *pipe_mask = BIT(PIPE_A); in intel_ddi_get_encoder_pipes()
751 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
754 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
793 *pipe_mask |= BIT(p); in intel_ddi_get_encoder_pipes()
796 if (!*pipe_mask) in intel_ddi_get_encoder_pipes()
801 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { in intel_ddi_get_encoder_pipes()
805 *pipe_mask); in intel_ddi_get_encoder_pipes()
806 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
[all …]
Dg4x_hdmi.c582 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
584 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
586 intel_encoder->pipe_mask = ~0; in g4x_hdmi_init()
Dintel_dp.c4033 u8 *pipe_mask) in intel_dp_prep_link_retrain() argument
4040 *pipe_mask = 0; in intel_dp_prep_link_retrain()
4074 *pipe_mask |= BIT(crtc->pipe); in intel_dp_prep_link_retrain()
4079 *pipe_mask = 0; in intel_dp_prep_link_retrain()
4098 u8 pipe_mask; in intel_dp_retrain_link() local
4109 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &pipe_mask); in intel_dp_retrain_link()
4113 if (pipe_mask == 0) in intel_dp_retrain_link()
4119 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4130 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
4147 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { in intel_dp_retrain_link()
[all …]
Dintel_display.h378 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
434 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \ argument
438 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
Dintel_dpll_mgr.h248 u8 pipe_mask; member
Dintel_lvds.c917 intel_encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
919 intel_encoder->pipe_mask = ~0; in intel_lvds_init()
Dg4x_dp.c1364 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
1366 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
1368 intel_encoder->pipe_mask = ~0; in g4x_dp_init()
Dintel_crt.c1049 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1051 crt->base.pipe_mask = ~0; in intel_crt_init()
Dintel_dvo.c491 intel_encoder->pipe_mask = ~0; in intel_dvo_init()
Dvlv_dsi.c1920 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1922 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1924 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
Dintel_dp_mst.c910 intel_encoder->pipe_mask = ~0; in intel_dp_create_fake_mst_encoder()
Dintel_display_types.h159 u8 pipe_mask; member
Dintel_tv.c1973 intel_encoder->pipe_mask = ~0; in intel_tv_init()
Dicl_dsi.c2038 encoder->pipe_mask = ~0; in icl_dsi_init()
Dintel_display_debugfs.c948 pll->state.pipe_mask, pll->active_mask, in i915_shared_dplls_info()
Dintel_sdvo.c2997 intel_sdvo->base.pipe_mask = ~0; in intel_sdvo_output_setup()
Dintel_display.c3735 return pipes & RUNTIME_INFO(i915)->pipe_mask; in bigjoiner_pipes()
7854 for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask) in intel_encoder_possible_crtcs()
/Linux-v6.1/drivers/usb/renesas_usbhs/
Dcommon.c276 u16 pipe_mask = (u16)GENMASK(usbhs_get_dparam(priv, pipe_size), 0); in usbhs_xxxsts_clear() local
278 usbhs_write(priv, sts_reg, ~(1 << bit) & pipe_mask); in usbhs_xxxsts_clear()