| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource_helpers.c | 71 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_calculate_num_ways_for_subvp()
84 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_helper_calculate_num_ways_for_subvp()
154 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
199 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
216 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
241 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
307 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
318 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
327 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
337 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
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| D | dcn32_hwseq.c | 227 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
277 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_calculate_cab_allocation()
448 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
479 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
499 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
683 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_update_force_pstate()
698 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_update_force_pstate()
724 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_mall_sel()
784 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_program_mall_pipe_config()
948 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_init_hw()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1126 for (i = 0; i < pool->base.pipe_count; i++) { in dcn20_resource_destruct()
1382 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_add_dsc_to_stream_resource()
1613 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_set_mcif_arb_params()
1658 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_dsc()
1728 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1751 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { in dcn20_find_secondary_pipe()
1773 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1802 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_merge_pipes_for_validate()
1845 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_validate_apply_pipe_split_flags()
1865 if (plane_count > dc->res_pool->pipe_count / 2) in dcn20_validate_apply_pipe_split_flags()
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| D | dcn20_hwseq.c | 1516 int opp_count = dc->res_pool->pipe_count; in dcn20_update_dchubp_dpp()
1718 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1727 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1740 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1745 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1754 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_program_front_end_for_ctx()
1776 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_program_front_end_for_ctx()
1829 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn20_post_unlock_program_front_end()
1839 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
1853 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_post_unlock_program_front_end()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 133 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_hubp_states()
203 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_rq_states()
248 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_dlg_states()
302 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_ttu_states()
341 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_cm_states()
394 for (i = 0; i < pool->pipe_count; i++) { in dcn10_get_mpcc_states()
509 for (i = 0; i < pool->pipe_count; i++) { in dcn10_clear_hubp_underflow()
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| D | dcn10_hw_sequencer.c | 103 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
175 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
207 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
232 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
264 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hubp_states()
297 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
339 for (i = 0; i < pool->pipe_count; i++) { in dcn10_log_hw_state()
783 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
827 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_bios_golden_init()
854 for (i = 0; i < dc->res_pool->pipe_count; i++) { in false_optc_underflow_wa()
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| D | dcn10_resource.c | 934 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_destruct()
1386 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1389 pool->base.pipe_count = 3; in dcn10_resource_construct()
1603 for (i = 0; i < pool->base.pipe_count; i++) { in dcn10_resource_construct()
1672 pool->base.pipe_count = j; in dcn10_resource_construct()
1678 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1679 dc->dcn_ip->max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
1701 dc->caps.max_planes = pool->base.pipe_count; in dcn10_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 801 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_resource_destruct()
874 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_validate_bandwidth()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
1035 for (i = 0; i < pool->base.pipe_count; i++) { in dce60_construct()
1097 dc->caps.max_planes = pool->base.pipe_count; in dce60_construct()
1154 pool->base.pipe_count = res_cap_61.num_timing_generator; in dce61_construct()
1232 for (i = 0; i < pool->base.pipe_count; i++) { in dce61_construct()
1294 dc->caps.max_planes = pool->base.pipe_count; in dce61_construct()
1351 pool->base.pipe_count = res_cap_64.num_timing_generator; in dce64_construct()
1425 for (i = 0; i < pool->base.pipe_count; i++) { in dce64_construct()
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| D | dce60_hw_sequencer.c | 70 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_should_enable_fbc()
86 if (i == dc->res_pool->pipe_count) in dce60_should_enable_fbc()
395 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce60_apply_ctx_for_surface()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 804 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_resource_destruct()
877 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce80_validate_bandwidth()
963 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
1044 for (i = 0; i < pool->base.pipe_count; i++) { in dce80_construct()
1106 dc->caps.max_planes = pool->base.pipe_count; in dce80_construct()
1163 pool->base.pipe_count = res_cap_81.num_timing_generator; in dce81_construct()
1243 for (i = 0; i < pool->base.pipe_count; i++) { in dce81_construct()
1305 dc->caps.max_planes = pool->base.pipe_count; in dce81_construct()
1362 pool->base.pipe_count = res_cap_83.num_timing_generator; in dce83_construct()
1438 for (i = 0; i < pool->base.pipe_count; i++) { in dce83_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 1054 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_ctx_interdependent_lock()
1079 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_dangling_plane()
1145 for (i = 0; i < dc->res_pool->pipe_count; i++) { in disable_vbios_mode_if_required()
1241 full_pipe_count = dc->res_pool->pipe_count; in dc_create()
1338 int pipe_count = dc->res_pool->pipe_count; in enable_timing_multisync() local
1341 for (i = 0; i < pipe_count; i++) { in enable_timing_multisync()
1364 int pipe_count = dc->res_pool->pipe_count; in program_timing_sync() local
1367 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1376 for (i = 0; i < pipe_count; i++) { in program_timing_sync()
1390 for (j = i + 1; j < pipe_count; j++) { in program_timing_sync()
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| D | dc_surface.c | 150 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
162 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1112 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1193 for (i = 0; i < pool->base.pipe_count; i++) { in dcn30_resource_destruct()
1230 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() local
1232 for (i = 0; i < pipe_count; i++) { in dcn30_dwbc_create()
1255 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() local
1257 for (i = 0; i < pipe_count; i++) { in dcn30_mmhubbub_create()
1342 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_populate_dml_pipes_from_context()
1397 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_set_mcif_arb_params()
1524 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1610 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn30_find_split_pipe()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_resource.c | 716 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() local
718 for (i = 0; i < pipe_count; i++) { in dcn302_dwbc_create()
751 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() local
753 for (i = 0; i < pipe_count; i++) { in dcn302_mmhubbub_create()
978 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
979 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
1034 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1109 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_destruct()
1215 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
1367 for (i = 0; i < pool->pipe_count; i++) { in dcn302_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_resource.c | 660 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() local
662 for (i = 0; i < pipe_count; i++) { in dcn303_dwbc_create()
695 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() local
697 for (i = 0; i < pipe_count; i++) { in dcn303_mmhubbub_create()
906 loaded_ip->max_num_otg = pool->pipe_count; in init_soc_bounding_box()
907 loaded_ip->max_num_dpp = pool->pipe_count; in init_soc_bounding_box()
961 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1036 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_destruct()
1144 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
1286 for (i = 0; i < pool->pipe_count; i++) { in dcn303_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 815 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_destruct()
978 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
1266 pool->opps[pool->pipe_count] = &dce110_oppv->base; in underlay_create()
1267 pool->timing_generators[pool->pipe_count] = &dce110_tgv->base; in underlay_create()
1268 pool->mis[pool->pipe_count] = &dce110_miv->base; in underlay_create()
1269 pool->transforms[pool->pipe_count] = &dce110_xfmv->base; in underlay_create()
1270 pool->pipe_count++; in underlay_create()
1364 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1365 pool->base.underlay_pipe_index = pool->base.pipe_count; in dce110_resource_construct()
1439 for (i = 0; i < pool->base.pipe_count; i++) { in dce110_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 311 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
541 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
605 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
616 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
651 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
726 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
729 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
750 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
779 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
858 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn301/ |
| D | dcn301_resource.c | 1090 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_destruct()
1200 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() local
1202 for (i = 0; i < pipe_count; i++) { in dcn301_dwbc_create()
1225 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() local
1227 for (i = 0; i < pipe_count; i++) { in dcn301_mmhubbub_create()
1324 loaded_ip->max_num_dpp = pool->base.pipe_count; in init_soc_bounding_box()
1443 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn301_resource_construct()
1599 for (i = 0; i < pool->base.pipe_count; i++) { in dcn301_resource_construct()
1642 pool->base.pipe_count = j; in dcn301_resource_construct()
1717 dc->caps.max_planes = pool->base.pipe_count; in dcn301_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 195 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
296 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
369 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 718 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_destruct()
862 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
886 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
1452 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1510 pool->base.pipe_count = 4; in dcn21_resource_construct()
1621 for (i = 0; i < pool->base.pipe_count; i++) { in dcn21_resource_construct()
1689 pool->base.pipe_count = j; in dcn21_resource_construct()
1733 dc->caps.max_planes = pool->base.pipe_count; in dcn21_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 756 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_destruct()
843 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dce100_validate_bandwidth()
1064 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1075 for (i = 0; i < pool->base.pipe_count; i++) { in dce100_resource_construct()
1138 dc->caps.max_planes = pool->base.pipe_count; in dce100_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn316/ |
| D | dcn316_resource.c | 1422 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_destruct()
1537 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1539 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1562 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1564 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1652 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn316_populate_dml_pipes_from_context()
1771 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn316_resource_construct()
1916 for (i = 0; i < pool->base.pipe_count; i++) { in dcn316_resource_construct()
2034 dc->caps.max_planes = pool->base.pipe_count; in dcn316_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 1421 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_destruct()
1536 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1538 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1561 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1563 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1649 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn315_populate_dml_pipes_from_context()
1769 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn315_resource_construct()
1914 for (i = 0; i < pool->base.pipe_count; i++) { in dcn315_resource_construct()
2032 dc->caps.max_planes = pool->base.pipe_count; in dcn315_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_resource.c | 1423 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_destruct()
1538 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() local
1540 for (i = 0; i < pipe_count; i++) { in dcn31_dwbc_create()
1563 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() local
1565 for (i = 0; i < pipe_count; i++) { in dcn31_mmhubbub_create()
1651 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_populate_dml_pipes_from_context()
1767 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn31_validate_bandwidth()
1887 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn31_resource_construct()
2050 for (i = 0; i < pool->base.pipe_count; i++) { in dcn31_resource_construct()
2178 dc->caps.max_planes = pool->base.pipe_count; in dcn31_resource_construct()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 887 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_writeback_from_context()
938 for (i = 0; i < dc->res_pool->pipe_count; i++) { in is_dtbclk_required()
955 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
976 for (i = 0; i < dc->res_pool->pipe_count; i++) { in decide_zstate_support()
1039 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1070 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1171 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1195 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_populate_dml_pipes_from_context()
1583 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_wm()
1867 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dcn20_validate_bandwidth_internal()
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