Searched refs:op_own (Results 1 – 11 of 11) sorted by relevance
773 __be32 op_own, bool bf_ok, in mlx4_en_tx_write_desc() argument779 op_own |= htonl((bf_index & 0xffff) << 8); in mlx4_en_tx_write_desc()784 tx_desc->ctrl.owner_opcode = op_own; in mlx4_en_tx_write_desc()799 tx_desc->ctrl.owner_opcode = op_own; in mlx4_en_tx_write_desc()887 __be32 op_own; in mlx4_en_xmit() local1019 op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | in mlx4_en_xmit()1055 op_own = cpu_to_be32(MLX4_OPCODE_SEND) | in mlx4_en_xmit()1079 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); in mlx4_en_xmit()1081 op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); in mlx4_en_xmit()1113 op_own, bf_ok, send_doorbell); in mlx4_en_xmit()[all …]
87 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) { in get_sw_cqe()872 cqe64->op_own = MLX5_CQE_INVALID << 4; in init_cq_frag_buf()1102 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK; in __mlx5_ib_cq_clean()1104 dest64->op_own = owner_bit | in __mlx5_ib_cq_clean()1105 (dest64->op_own & ~MLX5_CQE_OWNER_MASK); in __mlx5_ib_cq_clean()1239 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own; in copy_resize_cqes()
786 u8 op_own; member837 u8 op_own; member877 return (cqe->op_own >> 2) & 0x3; in mlx5_get_cqe_format()882 return cqe->op_own >> 4; in get_cqe_opcode()1019 u8 op_own; member
116 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1; in mlx5e_cqes_update_owner() local124 cqe->op_own = op_own; in mlx5e_cqes_update_owner()128 op_own = !op_own; in mlx5e_cqes_update_owner()132 cqe->op_own = op_own; in mlx5e_cqes_update_owner()147 title->op_own &= 0xf0; in mlx5e_decompress_cqe()148 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz); in mlx5e_decompress_cqe()
234 u8 cqe_ownership_bit = cqe->op_own & MLX5_CQE_OWNER_MASK; in mlx5_cqwq_get_cqe()
1898 cqe->op_own = 0xf1; in mlx5e_alloc_cq_common()
67 cqe->op_own = 0xf1; in mlx5_aso_alloc_cq()
622 cqe64->op_own = MLX5_CQE_INVALID << 4; in init_cq_frag_buf()1270 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ncqe)))) { in get_sw_cqe()
789 cqe->op_own = MLX5_CQE_INVALID << 4 | MLX5_CQE_OWNER_MASK; in dr_create_cq()
437 cqe->op_own = MLX5_CQE_INVALID << 4 | MLX5_CQE_OWNER_MASK; in mlx5_fpga_conn_create_cq()
375 cqe64->op_own = MLX5_CQE_INVALID << 4; in cq_frag_buf_init()384 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & cq->cqe))) in get_sw_cqe()
