Searched refs:odiv (Results 1 – 7 of 7) sorted by relevance
| /Linux-v6.1/drivers/clk/imx/ |
| D | clk-fracn-gppll.c | 52 .odiv = (_odiv), \
122 u32 mfi, mfn, mfd, rdiv, odiv; in clk_fracn_gppll_recalc_rate() local
137 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
148 rate_table[i].odiv == odiv) in clk_fracn_gppll_recalc_rate()
158 switch (odiv) { in clk_fracn_gppll_recalc_rate()
160 odiv = 2; in clk_fracn_gppll_recalc_rate()
163 odiv = 3; in clk_fracn_gppll_recalc_rate()
171 do_div(fvco, mfd * rdiv * odiv); in clk_fracn_gppll_recalc_rate()
207 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | in clk_fracn_gppll_set_rate()
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| D | clk.h | 83 unsigned int odiv; member
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| /Linux-v6.1/drivers/media/dvb-frontends/ |
| D | stb6100.c | 302 int psd2, odiv; in stb6100_get_frequency() local
310 odiv = (regs[STB6100_VCO] & STB6100_VCO_ODIV) >> STB6100_VCO_ODIV_SHIFT; in stb6100_get_frequency()
315 *frequency = state->frequency = fvco >> (odiv + 1); in stb6100_get_frequency()
319 state->frequency, odiv, psd2, state->reference, fvco, nint, nfrac); in stb6100_get_frequency()
333 u8 g, psd2, odiv; in stb6100_set_frequency() local
358 odiv = 1; in stb6100_set_frequency()
360 odiv = 0; in stb6100_set_frequency()
363 regs[STB6100_VCO] = 0xe0 | (odiv << STB6100_VCO_ODIV_SHIFT); in stb6100_set_frequency()
384 fvco = frequency << (1 + odiv); in stb6100_set_frequency()
435 frequency, srate, (unsigned int)g, (unsigned int)odiv, in stb6100_set_frequency()
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| /Linux-v6.1/drivers/clk/axs10x/ |
| D | pll_clock.c | 71 u32 odiv; member
140 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
145 odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV)); in axs10x_pll_recalc_rate()
148 do_div(rate, idiv * odiv); in axs10x_pll_recalc_rate()
188 axs10x_encode_div(pll_cfg[i].odiv, 1)); in axs10x_pll_set_rate()
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| D | i2s_pll_clock.c | 102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
106 odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
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| /Linux-v6.1/drivers/clk/ |
| D | clk-hsdk-pll.c | 51 u32 odiv; member
144 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; in hsdk_pll_set_cfg()
173 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
193 odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT); in hsdk_pll_recalc_rate()
196 do_div(rate, idiv * odiv); in hsdk_pll_recalc_rate()
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| /Linux-v6.1/drivers/clk/microchip/ |
| D | clk-core.c | 591 static inline u32 spll_odiv_to_divider(u32 odiv) in spll_odiv_to_divider() argument
593 odiv = clamp_val(odiv, PLL_ODIV_MIN, PLL_ODIV_MAX); in spll_odiv_to_divider()
595 return 1 << odiv; in spll_odiv_to_divider()
649 u32 mult, odiv, div, v; in spll_clk_recalc_rate() local
653 odiv = ((v >> PLL_ODIV_SHIFT) & PLL_ODIV_MASK); in spll_clk_recalc_rate()
655 div = spll_odiv_to_divider(odiv); in spll_clk_recalc_rate()
681 u32 mult, odiv, v; in spll_clk_set_rate() local
684 ret = spll_calc_mult_div(pll, rate, parent_rate, &mult, &odiv); in spll_clk_set_rate()
705 v |= (mult << PLL_MULT_SHIFT) | (odiv << PLL_ODIV_SHIFT); in spll_clk_set_rate()
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