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Searched refs:mmSDMA0_GFX_RB_WPTR_HI (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
Dsdma0_4_0_offset.h220 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
Dsdma0_4_2_2_offset.h220 #define mmSDMA0_GFX_RB_WPTR_HI … macro
Dsdma0_4_2_offset.h216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Dsdma_v5_2.c209 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
254 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_2_ring_set_wptr()
569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume()
603 … WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume()
Dsdma_v5_0.c344 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
421 ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_ring_set_wptr()
741 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume()
778 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_gfx_resume()
Dsdma_v4_0.c675 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr()
722 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, in sdma_v4_0_ring_set_wptr()
1102 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); in sdma_v4_0_gfx_resume()
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h214 #define mmSDMA0_GFX_RB_WPTR_HI … macro
Dgc_10_3_0_offset.h200 #define mmSDMA0_GFX_RB_WPTR_HI … macro