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Searched refs:mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX (Results 1 – 7 of 7) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h3684 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_3_0_1_offset.h10351 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_1_0_offset.h5468 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_2_1_0_offset.h5711 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_3_0_2_offset.h12575 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_2_0_0_offset.h6649 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro
Ddcn_3_0_0_offset.h13859 #define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX … macro