1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v13_0.h"
29 #include "smu13_driver_if_v13_0_5.h"
30 #include "smu_v13_0_5_ppt.h"
31 #include "smu_v13_0_5_ppsmc.h"
32 #include "smu_v13_0_5_pmfw.h"
33 #include "smu_cmn.h"
34
35 /*
36 * DO NOT use these for err/warn/info/debug messages.
37 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
38 * They are more MGPU friendly.
39 */
40 #undef pr_err
41 #undef pr_warn
42 #undef pr_info
43 #undef pr_debug
44
45 #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
46 #define mmMP1_C2PMSG_2_BASE_IDX 0
47
48 #define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
49 #define mmMP1_C2PMSG_34_BASE_IDX 0
50
51 #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
52 #define mmMP1_C2PMSG_33_BASE_IDX 0
53
54 #define FEATURE_MASK(feature) (1ULL << feature)
55 #define SMC_DPM_FEATURE ( \
56 FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
57 FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
58 FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
59 FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \
60 FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
61 FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
62 FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \
63 FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \
64 FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT))
65
66 static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = {
67 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
68 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
69 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
70 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
71 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
72 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1),
73 MSG_MAP(Spare0, PPSMC_MSG_Spare0, 1),
74 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu , 1),
79 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
80 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
81 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
82 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
83 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
84 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
85 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
86 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
87 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
88 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
89 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
90 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
91 };
92
93 static struct cmn2asic_mapping smu_v13_0_5_feature_mask_map[SMU_FEATURE_COUNT] = {
94 FEA_MAP(DATA_CALCULATION),
95 FEA_MAP(PPT),
96 FEA_MAP(TDC),
97 FEA_MAP(THERMAL),
98 FEA_MAP(PROCHOT),
99 FEA_MAP(CCLK_DPM),
100 FEA_MAP_REVERSE(FCLK),
101 FEA_MAP(LCLK_DPM),
102 FEA_MAP(DF_CSTATES),
103 FEA_MAP(FAN_CONTROLLER),
104 FEA_MAP(CPPC),
105 FEA_MAP_HALF_REVERSE(GFX),
106 FEA_MAP(DS_GFXCLK),
107 FEA_MAP(S0I3),
108 FEA_MAP(VCN_DPM),
109 FEA_MAP(DS_VCN),
110 FEA_MAP(DCFCLK_DPM),
111 FEA_MAP(ATHUB_PG),
112 FEA_MAP_REVERSE(SOCCLK),
113 FEA_MAP(SHUBCLK_DPM),
114 FEA_MAP(GFXOFF),
115 };
116
117 static struct cmn2asic_mapping smu_v13_0_5_table_map[SMU_TABLE_COUNT] = {
118 TAB_MAP_VALID(WATERMARKS),
119 TAB_MAP_VALID(SMU_METRICS),
120 TAB_MAP_VALID(CUSTOM_DPM),
121 TAB_MAP_VALID(DPMCLOCKS),
122 };
123
smu_v13_0_5_init_smc_tables(struct smu_context * smu)124 static int smu_v13_0_5_init_smc_tables(struct smu_context *smu)
125 {
126 struct smu_table_context *smu_table = &smu->smu_table;
127 struct smu_table *tables = smu_table->tables;
128
129 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
130 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
131 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
132 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
133 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
134 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
135
136 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
137 if (!smu_table->clocks_table)
138 goto err0_out;
139
140 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
141 if (!smu_table->metrics_table)
142 goto err1_out;
143 smu_table->metrics_time = 0;
144
145 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
146 if (!smu_table->watermarks_table)
147 goto err2_out;
148
149 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
150 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
151 if (!smu_table->gpu_metrics_table)
152 goto err3_out;
153
154 return 0;
155
156 err3_out:
157 kfree(smu_table->watermarks_table);
158 err2_out:
159 kfree(smu_table->metrics_table);
160 err1_out:
161 kfree(smu_table->clocks_table);
162 err0_out:
163 return -ENOMEM;
164 }
165
smu_v13_0_5_fini_smc_tables(struct smu_context * smu)166 static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu)
167 {
168 struct smu_table_context *smu_table = &smu->smu_table;
169
170 kfree(smu_table->clocks_table);
171 smu_table->clocks_table = NULL;
172
173 kfree(smu_table->metrics_table);
174 smu_table->metrics_table = NULL;
175
176 kfree(smu_table->watermarks_table);
177 smu_table->watermarks_table = NULL;
178
179 kfree(smu_table->gpu_metrics_table);
180 smu_table->gpu_metrics_table = NULL;
181
182 return 0;
183 }
184
smu_v13_0_5_system_features_control(struct smu_context * smu,bool en)185 static int smu_v13_0_5_system_features_control(struct smu_context *smu, bool en)
186 {
187 struct amdgpu_device *adev = smu->adev;
188 int ret = 0;
189
190 if (!en && !adev->in_s0ix)
191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
192
193 return ret;
194 }
195
smu_v13_0_5_dpm_set_vcn_enable(struct smu_context * smu,bool enable)196 static int smu_v13_0_5_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
197 {
198 int ret = 0;
199
200 /* vcn dpm on is a prerequisite for vcn power gate messages */
201 if (enable)
202 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
203 0, NULL);
204 else
205 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
206 0, NULL);
207
208 return ret;
209 }
210
smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)211 static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
212 {
213 int ret = 0;
214
215 if (enable)
216 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
217 0, NULL);
218 else
219 ret = smu_cmn_send_smc_msg_with_param(smu,
220 SMU_MSG_PowerDownJpeg, 0,
221 NULL);
222
223 return ret;
224 }
225
226
smu_v13_0_5_is_dpm_running(struct smu_context * smu)227 static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu)
228 {
229 int ret = 0;
230 uint64_t feature_enabled;
231
232 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
233
234 if (ret)
235 return false;
236
237 return !!(feature_enabled & SMC_DPM_FEATURE);
238 }
239
smu_v13_0_5_mode_reset(struct smu_context * smu,int type)240 static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type)
241 {
242 int ret = 0;
243
244 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, type, NULL);
245 if (ret)
246 dev_err(smu->adev->dev, "Failed to mode reset!\n");
247
248 return ret;
249 }
250
smu_v13_0_5_mode2_reset(struct smu_context * smu)251 static int smu_v13_0_5_mode2_reset(struct smu_context *smu)
252 {
253 return smu_v13_0_5_mode_reset(smu, SMU_RESET_MODE_2);
254 }
255
smu_v13_0_5_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)256 static int smu_v13_0_5_get_smu_metrics_data(struct smu_context *smu,
257 MetricsMember_t member,
258 uint32_t *value)
259 {
260 struct smu_table_context *smu_table = &smu->smu_table;
261
262 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
263 int ret = 0;
264
265 ret = smu_cmn_get_metrics_table(smu, NULL, false);
266 if (ret)
267 return ret;
268
269 switch (member) {
270 case METRICS_AVERAGE_GFXCLK:
271 *value = metrics->GfxclkFrequency;
272 break;
273 case METRICS_AVERAGE_SOCCLK:
274 *value = metrics->SocclkFrequency;
275 break;
276 case METRICS_AVERAGE_VCLK:
277 *value = metrics->VclkFrequency;
278 break;
279 case METRICS_AVERAGE_DCLK:
280 *value = metrics->DclkFrequency;
281 break;
282 case METRICS_AVERAGE_UCLK:
283 *value = metrics->MemclkFrequency;
284 break;
285 case METRICS_AVERAGE_GFXACTIVITY:
286 *value = metrics->GfxActivity / 100;
287 break;
288 case METRICS_AVERAGE_VCNACTIVITY:
289 *value = metrics->UvdActivity;
290 break;
291 case METRICS_AVERAGE_SOCKETPOWER:
292 *value = (metrics->CurrentSocketPower << 8) / 1000;
293 break;
294 case METRICS_TEMPERATURE_EDGE:
295 *value = metrics->GfxTemperature / 100 *
296 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
297 break;
298 case METRICS_TEMPERATURE_HOTSPOT:
299 *value = metrics->SocTemperature / 100 *
300 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
301 break;
302 case METRICS_THROTTLER_STATUS:
303 *value = metrics->ThrottlerStatus;
304 break;
305 case METRICS_VOLTAGE_VDDGFX:
306 *value = metrics->Voltage[0];
307 break;
308 case METRICS_VOLTAGE_VDDSOC:
309 *value = metrics->Voltage[1];
310 break;
311 default:
312 *value = UINT_MAX;
313 break;
314 }
315
316 return ret;
317 }
318
smu_v13_0_5_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)319 static int smu_v13_0_5_read_sensor(struct smu_context *smu,
320 enum amd_pp_sensors sensor,
321 void *data, uint32_t *size)
322 {
323 int ret = 0;
324
325 if (!data || !size)
326 return -EINVAL;
327
328 switch (sensor) {
329 case AMDGPU_PP_SENSOR_GPU_LOAD:
330 ret = smu_v13_0_5_get_smu_metrics_data(smu,
331 METRICS_AVERAGE_GFXACTIVITY,
332 (uint32_t *)data);
333 *size = 4;
334 break;
335 case AMDGPU_PP_SENSOR_GPU_POWER:
336 ret = smu_v13_0_5_get_smu_metrics_data(smu,
337 METRICS_AVERAGE_SOCKETPOWER,
338 (uint32_t *)data);
339 *size = 4;
340 break;
341 case AMDGPU_PP_SENSOR_EDGE_TEMP:
342 ret = smu_v13_0_5_get_smu_metrics_data(smu,
343 METRICS_TEMPERATURE_EDGE,
344 (uint32_t *)data);
345 *size = 4;
346 break;
347 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
348 ret = smu_v13_0_5_get_smu_metrics_data(smu,
349 METRICS_TEMPERATURE_HOTSPOT,
350 (uint32_t *)data);
351 *size = 4;
352 break;
353 case AMDGPU_PP_SENSOR_GFX_MCLK:
354 ret = smu_v13_0_5_get_smu_metrics_data(smu,
355 METRICS_AVERAGE_UCLK,
356 (uint32_t *)data);
357 *(uint32_t *)data *= 100;
358 *size = 4;
359 break;
360 case AMDGPU_PP_SENSOR_GFX_SCLK:
361 ret = smu_v13_0_5_get_smu_metrics_data(smu,
362 METRICS_AVERAGE_GFXCLK,
363 (uint32_t *)data);
364 *(uint32_t *)data *= 100;
365 *size = 4;
366 break;
367 case AMDGPU_PP_SENSOR_VDDGFX:
368 ret = smu_v13_0_5_get_smu_metrics_data(smu,
369 METRICS_VOLTAGE_VDDGFX,
370 (uint32_t *)data);
371 *size = 4;
372 break;
373 case AMDGPU_PP_SENSOR_VDDNB:
374 ret = smu_v13_0_5_get_smu_metrics_data(smu,
375 METRICS_VOLTAGE_VDDSOC,
376 (uint32_t *)data);
377 *size = 4;
378 break;
379 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
380 ret = smu_v13_0_5_get_smu_metrics_data(smu,
381 METRICS_SS_APU_SHARE,
382 (uint32_t *)data);
383 *size = 4;
384 break;
385 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
386 ret = smu_v13_0_5_get_smu_metrics_data(smu,
387 METRICS_SS_DGPU_SHARE,
388 (uint32_t *)data);
389 *size = 4;
390 break;
391 default:
392 ret = -EOPNOTSUPP;
393 break;
394 }
395
396 return ret;
397 }
398
smu_v13_0_5_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)399 static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu,
400 struct pp_smu_wm_range_sets *clock_ranges)
401 {
402 int i;
403 int ret = 0;
404 Watermarks_t *table = smu->smu_table.watermarks_table;
405
406 if (!table || !clock_ranges)
407 return -EINVAL;
408
409 if (clock_ranges) {
410 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
411 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
412 return -EINVAL;
413
414 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
415 table->WatermarkRow[WM_DCFCLK][i].MinClock =
416 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
417 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
418 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
419 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
420 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
421 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
422 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
423
424 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
425 clock_ranges->reader_wm_sets[i].wm_inst;
426 }
427
428 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
429 table->WatermarkRow[WM_SOCCLK][i].MinClock =
430 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
431 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
432 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
433 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
434 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
435 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
436 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
437
438 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
439 clock_ranges->writer_wm_sets[i].wm_inst;
440 }
441
442 smu->watermarks_bitmap |= WATERMARKS_EXIST;
443 }
444
445 /* pass data to smu controller */
446 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
447 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
448 ret = smu_cmn_write_watermarks_table(smu);
449 if (ret) {
450 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
451 return ret;
452 }
453 smu->watermarks_bitmap |= WATERMARKS_LOADED;
454 }
455
456 return 0;
457 }
458
smu_v13_0_5_get_gpu_metrics(struct smu_context * smu,void ** table)459 static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu,
460 void **table)
461 {
462 struct smu_table_context *smu_table = &smu->smu_table;
463 struct gpu_metrics_v2_1 *gpu_metrics =
464 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
465 SmuMetrics_t metrics;
466 int ret = 0;
467
468 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
469 if (ret)
470 return ret;
471
472 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
473
474 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
475 gpu_metrics->temperature_soc = metrics.SocTemperature;
476
477 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
478 gpu_metrics->average_mm_activity = metrics.UvdActivity;
479
480 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
481 gpu_metrics->average_gfx_power = metrics.Power[0];
482 gpu_metrics->average_soc_power = metrics.Power[1];
483 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
484 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
485 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
486 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
487 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
488 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
489 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
490 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
491
492 *table = (void *)gpu_metrics;
493
494 return sizeof(struct gpu_metrics_v2_1);
495 }
496
smu_v13_0_5_set_default_dpm_tables(struct smu_context * smu)497 static int smu_v13_0_5_set_default_dpm_tables(struct smu_context *smu)
498 {
499 struct smu_table_context *smu_table = &smu->smu_table;
500
501 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
502 }
503
smu_v13_0_5_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)504 static int smu_v13_0_5_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
505 long input[], uint32_t size)
506 {
507 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
508 int ret = 0;
509
510 /* Only allowed in manual mode */
511 if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
512 return -EINVAL;
513
514 switch (type) {
515 case PP_OD_EDIT_SCLK_VDDC_TABLE:
516 if (size != 2) {
517 dev_err(smu->adev->dev, "Input parameter number not correct\n");
518 return -EINVAL;
519 }
520
521 if (input[0] == 0) {
522 if (input[1] < smu->gfx_default_hard_min_freq) {
523 dev_warn(smu->adev->dev,
524 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
525 input[1], smu->gfx_default_hard_min_freq);
526 return -EINVAL;
527 }
528 smu->gfx_actual_hard_min_freq = input[1];
529 } else if (input[0] == 1) {
530 if (input[1] > smu->gfx_default_soft_max_freq) {
531 dev_warn(smu->adev->dev,
532 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
533 input[1], smu->gfx_default_soft_max_freq);
534 return -EINVAL;
535 }
536 smu->gfx_actual_soft_max_freq = input[1];
537 } else {
538 return -EINVAL;
539 }
540 break;
541 case PP_OD_RESTORE_DEFAULT_TABLE:
542 if (size != 0) {
543 dev_err(smu->adev->dev, "Input parameter number not correct\n");
544 return -EINVAL;
545 } else {
546 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
547 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
548 }
549 break;
550 case PP_OD_COMMIT_DPM_TABLE:
551 if (size != 0) {
552 dev_err(smu->adev->dev, "Input parameter number not correct\n");
553 return -EINVAL;
554 } else {
555 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
556 dev_err(smu->adev->dev,
557 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
558 smu->gfx_actual_hard_min_freq,
559 smu->gfx_actual_soft_max_freq);
560 return -EINVAL;
561 }
562
563 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
564 smu->gfx_actual_hard_min_freq, NULL);
565 if (ret) {
566 dev_err(smu->adev->dev, "Set hard min sclk failed!");
567 return ret;
568 }
569
570 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
571 smu->gfx_actual_soft_max_freq, NULL);
572 if (ret) {
573 dev_err(smu->adev->dev, "Set soft max sclk failed!");
574 return ret;
575 }
576 }
577 break;
578 default:
579 return -ENOSYS;
580 }
581
582 return ret;
583 }
584
smu_v13_0_5_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)585 static int smu_v13_0_5_get_current_clk_freq(struct smu_context *smu,
586 enum smu_clk_type clk_type,
587 uint32_t *value)
588 {
589 MetricsMember_t member_type;
590
591 switch (clk_type) {
592 case SMU_SOCCLK:
593 member_type = METRICS_AVERAGE_SOCCLK;
594 break;
595 case SMU_VCLK:
596 member_type = METRICS_AVERAGE_VCLK;
597 break;
598 case SMU_DCLK:
599 member_type = METRICS_AVERAGE_DCLK;
600 break;
601 case SMU_MCLK:
602 member_type = METRICS_AVERAGE_UCLK;
603 break;
604 case SMU_GFXCLK:
605 case SMU_SCLK:
606 return smu_cmn_send_smc_msg_with_param(smu,
607 SMU_MSG_GetGfxclkFrequency, 0, value);
608 break;
609 default:
610 return -EINVAL;
611 }
612
613 return smu_v13_0_5_get_smu_metrics_data(smu, member_type, value);
614 }
615
smu_v13_0_5_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)616 static int smu_v13_0_5_get_dpm_level_count(struct smu_context *smu,
617 enum smu_clk_type clk_type,
618 uint32_t *count)
619 {
620 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
621
622 switch (clk_type) {
623 case SMU_SOCCLK:
624 *count = clk_table->NumSocClkLevelsEnabled;
625 break;
626 case SMU_VCLK:
627 *count = clk_table->VcnClkLevelsEnabled;
628 break;
629 case SMU_DCLK:
630 *count = clk_table->VcnClkLevelsEnabled;
631 break;
632 case SMU_MCLK:
633 *count = clk_table->NumDfPstatesEnabled;
634 break;
635 case SMU_FCLK:
636 *count = clk_table->NumDfPstatesEnabled;
637 break;
638 default:
639 break;
640 }
641
642 return 0;
643 }
644
smu_v13_0_5_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)645 static int smu_v13_0_5_get_dpm_freq_by_index(struct smu_context *smu,
646 enum smu_clk_type clk_type,
647 uint32_t dpm_level,
648 uint32_t *freq)
649 {
650 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
651
652 if (!clk_table || clk_type >= SMU_CLK_COUNT)
653 return -EINVAL;
654
655 switch (clk_type) {
656 case SMU_SOCCLK:
657 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
658 return -EINVAL;
659 *freq = clk_table->SocClocks[dpm_level];
660 break;
661 case SMU_VCLK:
662 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
663 return -EINVAL;
664 *freq = clk_table->VClocks[dpm_level];
665 break;
666 case SMU_DCLK:
667 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
668 return -EINVAL;
669 *freq = clk_table->DClocks[dpm_level];
670 break;
671 case SMU_UCLK:
672 case SMU_MCLK:
673 if (dpm_level >= clk_table->NumDfPstatesEnabled)
674 return -EINVAL;
675 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
676 break;
677 case SMU_FCLK:
678 if (dpm_level >= clk_table->NumDfPstatesEnabled)
679 return -EINVAL;
680 *freq = clk_table->DfPstateTable[dpm_level].FClk;
681 break;
682 default:
683 return -EINVAL;
684 }
685
686 return 0;
687 }
688
smu_v13_0_5_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)689 static bool smu_v13_0_5_clk_dpm_is_enabled(struct smu_context *smu,
690 enum smu_clk_type clk_type)
691 {
692 enum smu_feature_mask feature_id = 0;
693
694 switch (clk_type) {
695 case SMU_MCLK:
696 case SMU_UCLK:
697 case SMU_FCLK:
698 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
699 break;
700 case SMU_GFXCLK:
701 case SMU_SCLK:
702 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
703 break;
704 case SMU_SOCCLK:
705 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
706 break;
707 case SMU_VCLK:
708 case SMU_DCLK:
709 feature_id = SMU_FEATURE_VCN_DPM_BIT;
710 break;
711 default:
712 return true;
713 }
714
715 return smu_cmn_feature_is_enabled(smu, feature_id);
716 }
717
smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)718 static int smu_v13_0_5_get_dpm_ultimate_freq(struct smu_context *smu,
719 enum smu_clk_type clk_type,
720 uint32_t *min,
721 uint32_t *max)
722 {
723 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
724 uint32_t clock_limit;
725 uint32_t max_dpm_level, min_dpm_level;
726 int ret = 0;
727
728 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type)) {
729 switch (clk_type) {
730 case SMU_MCLK:
731 case SMU_UCLK:
732 clock_limit = smu->smu_table.boot_values.uclk;
733 break;
734 case SMU_FCLK:
735 clock_limit = smu->smu_table.boot_values.fclk;
736 break;
737 case SMU_GFXCLK:
738 case SMU_SCLK:
739 clock_limit = smu->smu_table.boot_values.gfxclk;
740 break;
741 case SMU_SOCCLK:
742 clock_limit = smu->smu_table.boot_values.socclk;
743 break;
744 case SMU_VCLK:
745 clock_limit = smu->smu_table.boot_values.vclk;
746 break;
747 case SMU_DCLK:
748 clock_limit = smu->smu_table.boot_values.dclk;
749 break;
750 default:
751 clock_limit = 0;
752 break;
753 }
754
755 /* clock in Mhz unit */
756 if (min)
757 *min = clock_limit / 100;
758 if (max)
759 *max = clock_limit / 100;
760
761 return 0;
762 }
763
764 if (max) {
765 switch (clk_type) {
766 case SMU_GFXCLK:
767 case SMU_SCLK:
768 *max = clk_table->MaxGfxClk;
769 break;
770 case SMU_MCLK:
771 case SMU_UCLK:
772 case SMU_FCLK:
773 max_dpm_level = 0;
774 break;
775 case SMU_SOCCLK:
776 max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
777 break;
778 case SMU_VCLK:
779 case SMU_DCLK:
780 max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
781 break;
782 default:
783 ret = -EINVAL;
784 goto failed;
785 }
786
787 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
788 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
789 if (ret)
790 goto failed;
791 }
792 }
793
794 if (min) {
795 switch (clk_type) {
796 case SMU_GFXCLK:
797 case SMU_SCLK:
798 *min = clk_table->MinGfxClk;
799 break;
800 case SMU_MCLK:
801 case SMU_UCLK:
802 case SMU_FCLK:
803 min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
804 break;
805 case SMU_SOCCLK:
806 min_dpm_level = 0;
807 break;
808 case SMU_VCLK:
809 case SMU_DCLK:
810 min_dpm_level = 0;
811 break;
812 default:
813 ret = -EINVAL;
814 goto failed;
815 }
816
817 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
818 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
819 if (ret)
820 goto failed;
821 }
822 }
823
824 failed:
825 return ret;
826 }
827
smu_v13_0_5_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)828 static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu,
829 enum smu_clk_type clk_type,
830 uint32_t min,
831 uint32_t max)
832 {
833 enum smu_message_type msg_set_min, msg_set_max;
834 int ret = 0;
835
836 if (!smu_v13_0_5_clk_dpm_is_enabled(smu, clk_type))
837 return -EINVAL;
838
839 switch (clk_type) {
840 case SMU_GFXCLK:
841 case SMU_SCLK:
842 msg_set_min = SMU_MSG_SetHardMinGfxClk;
843 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
844 break;
845 case SMU_VCLK:
846 case SMU_DCLK:
847 msg_set_min = SMU_MSG_SetHardMinVcn;
848 msg_set_max = SMU_MSG_SetSoftMaxVcn;
849 break;
850 default:
851 return -EINVAL;
852 }
853
854 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
855 if (ret)
856 goto out;
857
858 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
859 if (ret)
860 goto out;
861
862 out:
863 return ret;
864 }
865
smu_v13_0_5_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)866 static int smu_v13_0_5_print_clk_levels(struct smu_context *smu,
867 enum smu_clk_type clk_type, char *buf)
868 {
869 int i, size = 0, ret = 0;
870 uint32_t cur_value = 0, value = 0, count = 0;
871 uint32_t min = 0, max = 0;
872
873 smu_cmn_get_sysfs_buf(&buf, &size);
874
875 switch (clk_type) {
876 case SMU_OD_SCLK:
877 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
878 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
879 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
880 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
881 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
882 break;
883 case SMU_OD_RANGE:
884 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
885 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
886 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
887 break;
888 case SMU_SOCCLK:
889 case SMU_VCLK:
890 case SMU_DCLK:
891 case SMU_MCLK:
892 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
893 if (ret)
894 goto print_clk_out;
895
896 ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count);
897 if (ret)
898 goto print_clk_out;
899
900 for (i = 0; i < count; i++) {
901 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, i, &value);
902 if (ret)
903 goto print_clk_out;
904
905 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
906 cur_value == value ? "*" : "");
907 }
908 break;
909 case SMU_GFXCLK:
910 case SMU_SCLK:
911 ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value);
912 if (ret)
913 goto print_clk_out;
914 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
915 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
916 if (cur_value == max)
917 i = 2;
918 else if (cur_value == min)
919 i = 0;
920 else
921 i = 1;
922 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
923 i == 0 ? "*" : "");
924 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
925 i == 1 ? cur_value : SMU_13_0_5_UMD_PSTATE_GFXCLK,
926 i == 1 ? "*" : "");
927 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
928 i == 2 ? "*" : "");
929 break;
930 default:
931 break;
932 }
933
934 print_clk_out:
935 return size;
936 }
937
938
smu_v13_0_5_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)939 static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,
940 enum smu_clk_type clk_type, uint32_t mask)
941 {
942 uint32_t soft_min_level = 0, soft_max_level = 0;
943 uint32_t min_freq = 0, max_freq = 0;
944 int ret = 0;
945
946 soft_min_level = mask ? (ffs(mask) - 1) : 0;
947 soft_max_level = mask ? (fls(mask) - 1) : 0;
948
949 switch (clk_type) {
950 case SMU_VCLK:
951 case SMU_DCLK:
952 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
953 if (ret)
954 goto force_level_out;
955
956 ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
957 if (ret)
958 goto force_level_out;
959
960 ret = smu_v13_0_5_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
961 if (ret)
962 goto force_level_out;
963 break;
964 default:
965 ret = -EINVAL;
966 break;
967 }
968
969 force_level_out:
970 return ret;
971 }
972
smu_v13_0_5_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)973 static int smu_v13_0_5_set_performance_level(struct smu_context *smu,
974 enum amd_dpm_forced_level level)
975 {
976 struct amdgpu_device *adev = smu->adev;
977 uint32_t sclk_min = 0, sclk_max = 0;
978 int ret = 0;
979
980 switch (level) {
981 case AMD_DPM_FORCED_LEVEL_HIGH:
982 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
983 sclk_min = sclk_max;
984 break;
985 case AMD_DPM_FORCED_LEVEL_LOW:
986 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
987 sclk_max = sclk_min;
988 break;
989 case AMD_DPM_FORCED_LEVEL_AUTO:
990 smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
991 break;
992 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
993 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
994 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
995 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
996 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
997 break;
998 case AMD_DPM_FORCED_LEVEL_MANUAL:
999 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1000 return 0;
1001 default:
1002 dev_err(adev->dev, "Invalid performance level %d\n", level);
1003 return -EINVAL;
1004 }
1005
1006 if (sclk_min && sclk_max && smu_v13_0_5_clk_dpm_is_enabled(smu, SMU_SCLK)) {
1007 ret = smu_v13_0_5_set_soft_freq_limited_range(smu,
1008 SMU_SCLK,
1009 sclk_min,
1010 sclk_max);
1011 if (ret)
1012 return ret;
1013
1014 smu->gfx_actual_hard_min_freq = sclk_min;
1015 smu->gfx_actual_soft_max_freq = sclk_max;
1016 }
1017
1018 return ret;
1019 }
1020
smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)1021 static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1022 {
1023 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1024
1025 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1026 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1027 smu->gfx_actual_hard_min_freq = 0;
1028 smu->gfx_actual_soft_max_freq = 0;
1029
1030 return 0;
1031 }
1032
1033 static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
1034 .check_fw_status = smu_v13_0_check_fw_status,
1035 .check_fw_version = smu_v13_0_check_fw_version,
1036 .init_smc_tables = smu_v13_0_5_init_smc_tables,
1037 .fini_smc_tables = smu_v13_0_5_fini_smc_tables,
1038 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1039 .system_features_control = smu_v13_0_5_system_features_control,
1040 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1041 .send_smc_msg = smu_cmn_send_smc_msg,
1042 .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable,
1043 .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable,
1044 .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables,
1045 .read_sensor = smu_v13_0_5_read_sensor,
1046 .is_dpm_running = smu_v13_0_5_is_dpm_running,
1047 .set_watermarks_table = smu_v13_0_5_set_watermarks_table,
1048 .get_gpu_metrics = smu_v13_0_5_get_gpu_metrics,
1049 .get_enabled_mask = smu_cmn_get_enabled_mask,
1050 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1051 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1052 .gfx_off_control = smu_v13_0_gfx_off_control,
1053 .mode2_reset = smu_v13_0_5_mode2_reset,
1054 .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq,
1055 .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table,
1056 .print_clk_levels = smu_v13_0_5_print_clk_levels,
1057 .force_clk_levels = smu_v13_0_5_force_clk_levels,
1058 .set_performance_level = smu_v13_0_5_set_performance_level,
1059 .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters,
1060 };
1061
smu_v13_0_5_set_ppt_funcs(struct smu_context * smu)1062 void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
1063 {
1064 struct amdgpu_device *adev = smu->adev;
1065
1066 smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
1067 smu->message_map = smu_v13_0_5_message_map;
1068 smu->feature_map = smu_v13_0_5_feature_mask_map;
1069 smu->table_map = smu_v13_0_5_table_map;
1070 smu->is_apu = true;
1071 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
1072 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
1073 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
1074 }
1075
