Searched refs:mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR (Results 1 – 5 of 5) sorted by relevance
120 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
294 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
1095 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1097 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()1138 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1140 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1364 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_init_cpu_queues()1836 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1838 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1885 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1887 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1943 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_tpc_qman()[all …]
164 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x4800040 macro
2661 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_pci_dma_qman()2716 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_dma_core()2832 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_hbm_dma_qman()2965 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_mme_qman()3101 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_tpc_qman()3258 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_nic_qman()3923 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_init_cpu_queues()4114 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_hw_fini()4584 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_ring_doorbell()8852 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR : in gaudi_enable_events_from_fw()
