1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
69 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
70 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
71 	MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION       = 0x25,
72 };
73 
74 enum {
75 	MLX5_SHARED_RESOURCE_UID = 0xffff,
76 };
77 
78 enum {
79 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
80 };
81 
82 enum {
83 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
84 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
85 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
86 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
87 };
88 
89 enum {
90 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
91 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
92 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
93 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
94 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
95 	MLX5_OBJ_TYPE_MKEY = 0xff01,
96 	MLX5_OBJ_TYPE_QP = 0xff02,
97 	MLX5_OBJ_TYPE_PSV = 0xff03,
98 	MLX5_OBJ_TYPE_RMP = 0xff04,
99 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
100 	MLX5_OBJ_TYPE_RQ = 0xff06,
101 	MLX5_OBJ_TYPE_SQ = 0xff07,
102 	MLX5_OBJ_TYPE_TIR = 0xff08,
103 	MLX5_OBJ_TYPE_TIS = 0xff09,
104 	MLX5_OBJ_TYPE_DCT = 0xff0a,
105 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
106 	MLX5_OBJ_TYPE_RQT = 0xff0e,
107 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
108 	MLX5_OBJ_TYPE_CQ = 0xff10,
109 };
110 
111 enum {
112 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
113 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
114 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
115 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
116 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
117 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
118 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
119 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
120 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
121 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
122 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
123 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
124 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
125 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
126 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
127 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
128 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
129 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
130 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
131 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
132 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
133 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
134 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
135 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
136 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
137 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
138 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
139 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
140 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
141 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
142 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
143 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
144 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
145 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
146 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
147 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
148 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
149 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
150 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
151 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
152 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
153 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
154 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
155 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
156 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
157 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
158 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
159 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
160 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
161 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
162 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
163 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
164 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
165 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
166 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
167 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
168 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
169 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
170 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
171 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
172 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
173 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
174 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
175 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
176 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
177 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
178 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
179 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
180 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
181 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
182 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
183 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
184 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
185 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
186 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
187 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
188 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
189 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
190 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
191 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
192 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
193 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
194 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
195 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
196 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
197 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
198 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
199 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
200 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
201 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
202 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
203 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
204 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
205 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
206 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
207 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
208 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
209 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
210 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
211 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
212 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
213 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
214 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
215 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
216 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
217 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
218 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
219 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
220 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
221 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
222 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
223 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
224 	MLX5_CMD_OP_NOP                           = 0x80d,
225 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
226 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
227 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
228 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
229 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
230 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
231 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
232 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
233 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
234 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
235 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
236 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
237 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
238 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
239 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
240 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
241 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
242 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
243 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
244 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
245 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
246 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
247 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
248 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
249 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
250 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
251 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
252 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
253 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
254 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
255 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
256 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
257 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
258 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
259 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
260 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
261 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
262 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
263 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
264 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
265 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
266 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
267 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
268 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
269 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
270 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
271 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
272 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
273 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
274 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
275 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
276 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
277 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
278 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
279 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
280 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
281 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
282 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
283 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
284 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
285 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
286 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
287 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
288 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
289 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
290 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
291 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
292 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
293 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
294 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
295 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
296 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
297 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
298 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
299 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
300 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
301 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
302 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
303 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
304 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
305 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
306 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
307 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
308 	MLX5_CMD_OP_MAX
309 };
310 
311 /* Valid range for general commands that don't work over an object */
312 enum {
313 	MLX5_CMD_OP_GENERAL_START = 0xb00,
314 	MLX5_CMD_OP_GENERAL_END = 0xd00,
315 };
316 
317 struct mlx5_ifc_flow_table_fields_supported_bits {
318 	u8         outer_dmac[0x1];
319 	u8         outer_smac[0x1];
320 	u8         outer_ether_type[0x1];
321 	u8         outer_ip_version[0x1];
322 	u8         outer_first_prio[0x1];
323 	u8         outer_first_cfi[0x1];
324 	u8         outer_first_vid[0x1];
325 	u8         outer_ipv4_ttl[0x1];
326 	u8         outer_second_prio[0x1];
327 	u8         outer_second_cfi[0x1];
328 	u8         outer_second_vid[0x1];
329 	u8         reserved_at_b[0x1];
330 	u8         outer_sip[0x1];
331 	u8         outer_dip[0x1];
332 	u8         outer_frag[0x1];
333 	u8         outer_ip_protocol[0x1];
334 	u8         outer_ip_ecn[0x1];
335 	u8         outer_ip_dscp[0x1];
336 	u8         outer_udp_sport[0x1];
337 	u8         outer_udp_dport[0x1];
338 	u8         outer_tcp_sport[0x1];
339 	u8         outer_tcp_dport[0x1];
340 	u8         outer_tcp_flags[0x1];
341 	u8         outer_gre_protocol[0x1];
342 	u8         outer_gre_key[0x1];
343 	u8         outer_vxlan_vni[0x1];
344 	u8         outer_geneve_vni[0x1];
345 	u8         outer_geneve_oam[0x1];
346 	u8         outer_geneve_protocol_type[0x1];
347 	u8         outer_geneve_opt_len[0x1];
348 	u8         source_vhca_port[0x1];
349 	u8         source_eswitch_port[0x1];
350 
351 	u8         inner_dmac[0x1];
352 	u8         inner_smac[0x1];
353 	u8         inner_ether_type[0x1];
354 	u8         inner_ip_version[0x1];
355 	u8         inner_first_prio[0x1];
356 	u8         inner_first_cfi[0x1];
357 	u8         inner_first_vid[0x1];
358 	u8         reserved_at_27[0x1];
359 	u8         inner_second_prio[0x1];
360 	u8         inner_second_cfi[0x1];
361 	u8         inner_second_vid[0x1];
362 	u8         reserved_at_2b[0x1];
363 	u8         inner_sip[0x1];
364 	u8         inner_dip[0x1];
365 	u8         inner_frag[0x1];
366 	u8         inner_ip_protocol[0x1];
367 	u8         inner_ip_ecn[0x1];
368 	u8         inner_ip_dscp[0x1];
369 	u8         inner_udp_sport[0x1];
370 	u8         inner_udp_dport[0x1];
371 	u8         inner_tcp_sport[0x1];
372 	u8         inner_tcp_dport[0x1];
373 	u8         inner_tcp_flags[0x1];
374 	u8         reserved_at_37[0x9];
375 
376 	u8         geneve_tlv_option_0_data[0x1];
377 	u8         geneve_tlv_option_0_exist[0x1];
378 	u8         reserved_at_42[0x3];
379 	u8         outer_first_mpls_over_udp[0x4];
380 	u8         outer_first_mpls_over_gre[0x4];
381 	u8         inner_first_mpls[0x4];
382 	u8         outer_first_mpls[0x4];
383 	u8         reserved_at_55[0x2];
384 	u8	   outer_esp_spi[0x1];
385 	u8         reserved_at_58[0x2];
386 	u8         bth_dst_qp[0x1];
387 	u8         reserved_at_5b[0x5];
388 
389 	u8         reserved_at_60[0x18];
390 	u8         metadata_reg_c_7[0x1];
391 	u8         metadata_reg_c_6[0x1];
392 	u8         metadata_reg_c_5[0x1];
393 	u8         metadata_reg_c_4[0x1];
394 	u8         metadata_reg_c_3[0x1];
395 	u8         metadata_reg_c_2[0x1];
396 	u8         metadata_reg_c_1[0x1];
397 	u8         metadata_reg_c_0[0x1];
398 };
399 
400 struct mlx5_ifc_flow_table_fields_supported_2_bits {
401 	u8         reserved_at_0[0xe];
402 	u8         bth_opcode[0x1];
403 	u8         reserved_at_f[0x11];
404 
405 	u8         reserved_at_20[0x60];
406 };
407 
408 struct mlx5_ifc_flow_table_prop_layout_bits {
409 	u8         ft_support[0x1];
410 	u8         reserved_at_1[0x1];
411 	u8         flow_counter[0x1];
412 	u8	   flow_modify_en[0x1];
413 	u8         modify_root[0x1];
414 	u8         identified_miss_table_mode[0x1];
415 	u8         flow_table_modify[0x1];
416 	u8         reformat[0x1];
417 	u8         decap[0x1];
418 	u8         reserved_at_9[0x1];
419 	u8         pop_vlan[0x1];
420 	u8         push_vlan[0x1];
421 	u8         reserved_at_c[0x1];
422 	u8         pop_vlan_2[0x1];
423 	u8         push_vlan_2[0x1];
424 	u8	   reformat_and_vlan_action[0x1];
425 	u8	   reserved_at_10[0x1];
426 	u8         sw_owner[0x1];
427 	u8	   reformat_l3_tunnel_to_l2[0x1];
428 	u8	   reformat_l2_to_l3_tunnel[0x1];
429 	u8	   reformat_and_modify_action[0x1];
430 	u8	   ignore_flow_level[0x1];
431 	u8         reserved_at_16[0x1];
432 	u8	   table_miss_action_domain[0x1];
433 	u8         termination_table[0x1];
434 	u8         reformat_and_fwd_to_table[0x1];
435 	u8         reserved_at_1a[0x2];
436 	u8         ipsec_encrypt[0x1];
437 	u8         ipsec_decrypt[0x1];
438 	u8         sw_owner_v2[0x1];
439 	u8         reserved_at_1f[0x1];
440 
441 	u8         termination_table_raw_traffic[0x1];
442 	u8         reserved_at_21[0x1];
443 	u8         log_max_ft_size[0x6];
444 	u8         log_max_modify_header_context[0x8];
445 	u8         max_modify_header_actions[0x8];
446 	u8         max_ft_level[0x8];
447 
448 	u8         reserved_at_40[0x6];
449 	u8         execute_aso[0x1];
450 	u8         reserved_at_47[0x19];
451 
452 	u8         reserved_at_60[0x2];
453 	u8         reformat_insert[0x1];
454 	u8         reformat_remove[0x1];
455 	u8         macsec_encrypt[0x1];
456 	u8         macsec_decrypt[0x1];
457 	u8         reserved_at_66[0x2];
458 	u8         reformat_add_macsec[0x1];
459 	u8         reformat_remove_macsec[0x1];
460 	u8         reserved_at_6a[0xe];
461 	u8         log_max_ft_num[0x8];
462 
463 	u8         reserved_at_80[0x10];
464 	u8         log_max_flow_counter[0x8];
465 	u8         log_max_destination[0x8];
466 
467 	u8         reserved_at_a0[0x18];
468 	u8         log_max_flow[0x8];
469 
470 	u8         reserved_at_c0[0x40];
471 
472 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
473 
474 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
475 };
476 
477 struct mlx5_ifc_odp_per_transport_service_cap_bits {
478 	u8         send[0x1];
479 	u8         receive[0x1];
480 	u8         write[0x1];
481 	u8         read[0x1];
482 	u8         atomic[0x1];
483 	u8         srq_receive[0x1];
484 	u8         reserved_at_6[0x1a];
485 };
486 
487 struct mlx5_ifc_ipv4_layout_bits {
488 	u8         reserved_at_0[0x60];
489 
490 	u8         ipv4[0x20];
491 };
492 
493 struct mlx5_ifc_ipv6_layout_bits {
494 	u8         ipv6[16][0x8];
495 };
496 
497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
498 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
499 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
500 	u8         reserved_at_0[0x80];
501 };
502 
503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
504 	u8         smac_47_16[0x20];
505 
506 	u8         smac_15_0[0x10];
507 	u8         ethertype[0x10];
508 
509 	u8         dmac_47_16[0x20];
510 
511 	u8         dmac_15_0[0x10];
512 	u8         first_prio[0x3];
513 	u8         first_cfi[0x1];
514 	u8         first_vid[0xc];
515 
516 	u8         ip_protocol[0x8];
517 	u8         ip_dscp[0x6];
518 	u8         ip_ecn[0x2];
519 	u8         cvlan_tag[0x1];
520 	u8         svlan_tag[0x1];
521 	u8         frag[0x1];
522 	u8         ip_version[0x4];
523 	u8         tcp_flags[0x9];
524 
525 	u8         tcp_sport[0x10];
526 	u8         tcp_dport[0x10];
527 
528 	u8         reserved_at_c0[0x10];
529 	u8         ipv4_ihl[0x4];
530 	u8         reserved_at_c4[0x4];
531 
532 	u8         ttl_hoplimit[0x8];
533 
534 	u8         udp_sport[0x10];
535 	u8         udp_dport[0x10];
536 
537 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
538 
539 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
540 };
541 
542 struct mlx5_ifc_nvgre_key_bits {
543 	u8 hi[0x18];
544 	u8 lo[0x8];
545 };
546 
547 union mlx5_ifc_gre_key_bits {
548 	struct mlx5_ifc_nvgre_key_bits nvgre;
549 	u8 key[0x20];
550 };
551 
552 struct mlx5_ifc_fte_match_set_misc_bits {
553 	u8         gre_c_present[0x1];
554 	u8         reserved_at_1[0x1];
555 	u8         gre_k_present[0x1];
556 	u8         gre_s_present[0x1];
557 	u8         source_vhca_port[0x4];
558 	u8         source_sqn[0x18];
559 
560 	u8         source_eswitch_owner_vhca_id[0x10];
561 	u8         source_port[0x10];
562 
563 	u8         outer_second_prio[0x3];
564 	u8         outer_second_cfi[0x1];
565 	u8         outer_second_vid[0xc];
566 	u8         inner_second_prio[0x3];
567 	u8         inner_second_cfi[0x1];
568 	u8         inner_second_vid[0xc];
569 
570 	u8         outer_second_cvlan_tag[0x1];
571 	u8         inner_second_cvlan_tag[0x1];
572 	u8         outer_second_svlan_tag[0x1];
573 	u8         inner_second_svlan_tag[0x1];
574 	u8         reserved_at_64[0xc];
575 	u8         gre_protocol[0x10];
576 
577 	union mlx5_ifc_gre_key_bits gre_key;
578 
579 	u8         vxlan_vni[0x18];
580 	u8         bth_opcode[0x8];
581 
582 	u8         geneve_vni[0x18];
583 	u8         reserved_at_d8[0x6];
584 	u8         geneve_tlv_option_0_exist[0x1];
585 	u8         geneve_oam[0x1];
586 
587 	u8         reserved_at_e0[0xc];
588 	u8         outer_ipv6_flow_label[0x14];
589 
590 	u8         reserved_at_100[0xc];
591 	u8         inner_ipv6_flow_label[0x14];
592 
593 	u8         reserved_at_120[0xa];
594 	u8         geneve_opt_len[0x6];
595 	u8         geneve_protocol_type[0x10];
596 
597 	u8         reserved_at_140[0x8];
598 	u8         bth_dst_qp[0x18];
599 	u8	   reserved_at_160[0x20];
600 	u8	   outer_esp_spi[0x20];
601 	u8         reserved_at_1a0[0x60];
602 };
603 
604 struct mlx5_ifc_fte_match_mpls_bits {
605 	u8         mpls_label[0x14];
606 	u8         mpls_exp[0x3];
607 	u8         mpls_s_bos[0x1];
608 	u8         mpls_ttl[0x8];
609 };
610 
611 struct mlx5_ifc_fte_match_set_misc2_bits {
612 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
613 
614 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
615 
616 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
617 
618 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
619 
620 	u8         metadata_reg_c_7[0x20];
621 
622 	u8         metadata_reg_c_6[0x20];
623 
624 	u8         metadata_reg_c_5[0x20];
625 
626 	u8         metadata_reg_c_4[0x20];
627 
628 	u8         metadata_reg_c_3[0x20];
629 
630 	u8         metadata_reg_c_2[0x20];
631 
632 	u8         metadata_reg_c_1[0x20];
633 
634 	u8         metadata_reg_c_0[0x20];
635 
636 	u8         metadata_reg_a[0x20];
637 
638 	u8         reserved_at_1a0[0x8];
639 
640 	u8         macsec_syndrome[0x8];
641 
642 	u8         reserved_at_1b0[0x50];
643 };
644 
645 struct mlx5_ifc_fte_match_set_misc3_bits {
646 	u8         inner_tcp_seq_num[0x20];
647 
648 	u8         outer_tcp_seq_num[0x20];
649 
650 	u8         inner_tcp_ack_num[0x20];
651 
652 	u8         outer_tcp_ack_num[0x20];
653 
654 	u8	   reserved_at_80[0x8];
655 	u8         outer_vxlan_gpe_vni[0x18];
656 
657 	u8         outer_vxlan_gpe_next_protocol[0x8];
658 	u8         outer_vxlan_gpe_flags[0x8];
659 	u8	   reserved_at_b0[0x10];
660 
661 	u8	   icmp_header_data[0x20];
662 
663 	u8	   icmpv6_header_data[0x20];
664 
665 	u8	   icmp_type[0x8];
666 	u8	   icmp_code[0x8];
667 	u8	   icmpv6_type[0x8];
668 	u8	   icmpv6_code[0x8];
669 
670 	u8         geneve_tlv_option_0_data[0x20];
671 
672 	u8	   gtpu_teid[0x20];
673 
674 	u8	   gtpu_msg_type[0x8];
675 	u8	   gtpu_msg_flags[0x8];
676 	u8	   reserved_at_170[0x10];
677 
678 	u8	   gtpu_dw_2[0x20];
679 
680 	u8	   gtpu_first_ext_dw_0[0x20];
681 
682 	u8	   gtpu_dw_0[0x20];
683 
684 	u8	   reserved_at_1e0[0x20];
685 };
686 
687 struct mlx5_ifc_fte_match_set_misc4_bits {
688 	u8         prog_sample_field_value_0[0x20];
689 
690 	u8         prog_sample_field_id_0[0x20];
691 
692 	u8         prog_sample_field_value_1[0x20];
693 
694 	u8         prog_sample_field_id_1[0x20];
695 
696 	u8         prog_sample_field_value_2[0x20];
697 
698 	u8         prog_sample_field_id_2[0x20];
699 
700 	u8         prog_sample_field_value_3[0x20];
701 
702 	u8         prog_sample_field_id_3[0x20];
703 
704 	u8         reserved_at_100[0x100];
705 };
706 
707 struct mlx5_ifc_fte_match_set_misc5_bits {
708 	u8         macsec_tag_0[0x20];
709 
710 	u8         macsec_tag_1[0x20];
711 
712 	u8         macsec_tag_2[0x20];
713 
714 	u8         macsec_tag_3[0x20];
715 
716 	u8         tunnel_header_0[0x20];
717 
718 	u8         tunnel_header_1[0x20];
719 
720 	u8         tunnel_header_2[0x20];
721 
722 	u8         tunnel_header_3[0x20];
723 
724 	u8         reserved_at_100[0x100];
725 };
726 
727 struct mlx5_ifc_cmd_pas_bits {
728 	u8         pa_h[0x20];
729 
730 	u8         pa_l[0x14];
731 	u8         reserved_at_34[0xc];
732 };
733 
734 struct mlx5_ifc_uint64_bits {
735 	u8         hi[0x20];
736 
737 	u8         lo[0x20];
738 };
739 
740 enum {
741 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
742 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
743 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
744 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
745 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
746 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
747 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
748 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
749 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
750 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
751 };
752 
753 struct mlx5_ifc_ads_bits {
754 	u8         fl[0x1];
755 	u8         free_ar[0x1];
756 	u8         reserved_at_2[0xe];
757 	u8         pkey_index[0x10];
758 
759 	u8         reserved_at_20[0x8];
760 	u8         grh[0x1];
761 	u8         mlid[0x7];
762 	u8         rlid[0x10];
763 
764 	u8         ack_timeout[0x5];
765 	u8         reserved_at_45[0x3];
766 	u8         src_addr_index[0x8];
767 	u8         reserved_at_50[0x4];
768 	u8         stat_rate[0x4];
769 	u8         hop_limit[0x8];
770 
771 	u8         reserved_at_60[0x4];
772 	u8         tclass[0x8];
773 	u8         flow_label[0x14];
774 
775 	u8         rgid_rip[16][0x8];
776 
777 	u8         reserved_at_100[0x4];
778 	u8         f_dscp[0x1];
779 	u8         f_ecn[0x1];
780 	u8         reserved_at_106[0x1];
781 	u8         f_eth_prio[0x1];
782 	u8         ecn[0x2];
783 	u8         dscp[0x6];
784 	u8         udp_sport[0x10];
785 
786 	u8         dei_cfi[0x1];
787 	u8         eth_prio[0x3];
788 	u8         sl[0x4];
789 	u8         vhca_port_num[0x8];
790 	u8         rmac_47_32[0x10];
791 
792 	u8         rmac_31_0[0x20];
793 };
794 
795 struct mlx5_ifc_flow_table_nic_cap_bits {
796 	u8         nic_rx_multi_path_tirs[0x1];
797 	u8         nic_rx_multi_path_tirs_fts[0x1];
798 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
799 	u8	   reserved_at_3[0x4];
800 	u8	   sw_owner_reformat_supported[0x1];
801 	u8	   reserved_at_8[0x18];
802 
803 	u8	   encap_general_header[0x1];
804 	u8	   reserved_at_21[0xa];
805 	u8	   log_max_packet_reformat_context[0x5];
806 	u8	   reserved_at_30[0x6];
807 	u8	   max_encap_header_size[0xa];
808 	u8	   reserved_at_40[0x1c0];
809 
810 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
811 
812 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
813 
814 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
815 
816 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
817 
818 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
819 
820 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
821 
822 	u8         reserved_at_e00[0x700];
823 
824 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
825 
826 	u8         reserved_at_1580[0x280];
827 
828 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
829 
830 	u8         reserved_at_1880[0x780];
831 
832 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
833 
834 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
835 
836 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
837 
838 	u8         reserved_at_20c0[0x5f40];
839 };
840 
841 struct mlx5_ifc_port_selection_cap_bits {
842 	u8         reserved_at_0[0x10];
843 	u8         port_select_flow_table[0x1];
844 	u8         reserved_at_11[0x1];
845 	u8         port_select_flow_table_bypass[0x1];
846 	u8         reserved_at_13[0xd];
847 
848 	u8         reserved_at_20[0x1e0];
849 
850 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
851 
852 	u8         reserved_at_400[0x7c00];
853 };
854 
855 enum {
856 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
857 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
858 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
859 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
860 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
861 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
862 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
863 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
864 };
865 
866 struct mlx5_ifc_flow_table_eswitch_cap_bits {
867 	u8      fdb_to_vport_reg_c_id[0x8];
868 	u8      reserved_at_8[0xd];
869 	u8      fdb_modify_header_fwd_to_table[0x1];
870 	u8      fdb_ipv4_ttl_modify[0x1];
871 	u8      flow_source[0x1];
872 	u8      reserved_at_18[0x2];
873 	u8      multi_fdb_encap[0x1];
874 	u8      egress_acl_forward_to_vport[0x1];
875 	u8      fdb_multi_path_to_table[0x1];
876 	u8      reserved_at_1d[0x3];
877 
878 	u8      reserved_at_20[0x1e0];
879 
880 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
881 
882 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
883 
884 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
885 
886 	u8      reserved_at_800[0x1000];
887 
888 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
889 
890 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
891 
892 	u8      sw_steering_uplink_icm_address_rx[0x40];
893 
894 	u8      sw_steering_uplink_icm_address_tx[0x40];
895 
896 	u8      reserved_at_1900[0x6700];
897 };
898 
899 enum {
900 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
901 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
902 };
903 
904 struct mlx5_ifc_e_switch_cap_bits {
905 	u8         vport_svlan_strip[0x1];
906 	u8         vport_cvlan_strip[0x1];
907 	u8         vport_svlan_insert[0x1];
908 	u8         vport_cvlan_insert_if_not_exist[0x1];
909 	u8         vport_cvlan_insert_overwrite[0x1];
910 	u8         reserved_at_5[0x2];
911 	u8         esw_shared_ingress_acl[0x1];
912 	u8         esw_uplink_ingress_acl[0x1];
913 	u8         root_ft_on_other_esw[0x1];
914 	u8         reserved_at_a[0xf];
915 	u8         esw_functions_changed[0x1];
916 	u8         reserved_at_1a[0x1];
917 	u8         ecpf_vport_exists[0x1];
918 	u8         counter_eswitch_affinity[0x1];
919 	u8         merged_eswitch[0x1];
920 	u8         nic_vport_node_guid_modify[0x1];
921 	u8         nic_vport_port_guid_modify[0x1];
922 
923 	u8         vxlan_encap_decap[0x1];
924 	u8         nvgre_encap_decap[0x1];
925 	u8         reserved_at_22[0x1];
926 	u8         log_max_fdb_encap_uplink[0x5];
927 	u8         reserved_at_21[0x3];
928 	u8         log_max_packet_reformat_context[0x5];
929 	u8         reserved_2b[0x6];
930 	u8         max_encap_header_size[0xa];
931 
932 	u8         reserved_at_40[0xb];
933 	u8         log_max_esw_sf[0x5];
934 	u8         esw_sf_base_id[0x10];
935 
936 	u8         reserved_at_60[0x7a0];
937 
938 };
939 
940 struct mlx5_ifc_qos_cap_bits {
941 	u8         packet_pacing[0x1];
942 	u8         esw_scheduling[0x1];
943 	u8         esw_bw_share[0x1];
944 	u8         esw_rate_limit[0x1];
945 	u8         reserved_at_4[0x1];
946 	u8         packet_pacing_burst_bound[0x1];
947 	u8         packet_pacing_typical_size[0x1];
948 	u8         reserved_at_7[0x1];
949 	u8         nic_sq_scheduling[0x1];
950 	u8         nic_bw_share[0x1];
951 	u8         nic_rate_limit[0x1];
952 	u8         packet_pacing_uid[0x1];
953 	u8         log_esw_max_sched_depth[0x4];
954 	u8         reserved_at_10[0x10];
955 
956 	u8         reserved_at_20[0xb];
957 	u8         log_max_qos_nic_queue_group[0x5];
958 	u8         reserved_at_30[0x10];
959 
960 	u8         packet_pacing_max_rate[0x20];
961 
962 	u8         packet_pacing_min_rate[0x20];
963 
964 	u8         reserved_at_80[0x10];
965 	u8         packet_pacing_rate_table_size[0x10];
966 
967 	u8         esw_element_type[0x10];
968 	u8         esw_tsar_type[0x10];
969 
970 	u8         reserved_at_c0[0x10];
971 	u8         max_qos_para_vport[0x10];
972 
973 	u8         max_tsar_bw_share[0x20];
974 
975 	u8         reserved_at_100[0x20];
976 
977 	u8         reserved_at_120[0x3];
978 	u8         log_meter_aso_granularity[0x5];
979 	u8         reserved_at_128[0x3];
980 	u8         log_meter_aso_max_alloc[0x5];
981 	u8         reserved_at_130[0x3];
982 	u8         log_max_num_meter_aso[0x5];
983 	u8         reserved_at_138[0x8];
984 
985 	u8         reserved_at_140[0x6c0];
986 };
987 
988 struct mlx5_ifc_debug_cap_bits {
989 	u8         core_dump_general[0x1];
990 	u8         core_dump_qp[0x1];
991 	u8         reserved_at_2[0x7];
992 	u8         resource_dump[0x1];
993 	u8         reserved_at_a[0x16];
994 
995 	u8         reserved_at_20[0x2];
996 	u8         stall_detect[0x1];
997 	u8         reserved_at_23[0x1d];
998 
999 	u8         reserved_at_40[0x7c0];
1000 };
1001 
1002 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1003 	u8         csum_cap[0x1];
1004 	u8         vlan_cap[0x1];
1005 	u8         lro_cap[0x1];
1006 	u8         lro_psh_flag[0x1];
1007 	u8         lro_time_stamp[0x1];
1008 	u8         reserved_at_5[0x2];
1009 	u8         wqe_vlan_insert[0x1];
1010 	u8         self_lb_en_modifiable[0x1];
1011 	u8         reserved_at_9[0x2];
1012 	u8         max_lso_cap[0x5];
1013 	u8         multi_pkt_send_wqe[0x2];
1014 	u8	   wqe_inline_mode[0x2];
1015 	u8         rss_ind_tbl_cap[0x4];
1016 	u8         reg_umr_sq[0x1];
1017 	u8         scatter_fcs[0x1];
1018 	u8         enhanced_multi_pkt_send_wqe[0x1];
1019 	u8         tunnel_lso_const_out_ip_id[0x1];
1020 	u8         tunnel_lro_gre[0x1];
1021 	u8         tunnel_lro_vxlan[0x1];
1022 	u8         tunnel_stateless_gre[0x1];
1023 	u8         tunnel_stateless_vxlan[0x1];
1024 
1025 	u8         swp[0x1];
1026 	u8         swp_csum[0x1];
1027 	u8         swp_lso[0x1];
1028 	u8         cqe_checksum_full[0x1];
1029 	u8         tunnel_stateless_geneve_tx[0x1];
1030 	u8         tunnel_stateless_mpls_over_udp[0x1];
1031 	u8         tunnel_stateless_mpls_over_gre[0x1];
1032 	u8         tunnel_stateless_vxlan_gpe[0x1];
1033 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1034 	u8         tunnel_stateless_ip_over_ip[0x1];
1035 	u8         insert_trailer[0x1];
1036 	u8         reserved_at_2b[0x1];
1037 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1038 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1039 	u8         reserved_at_2e[0x2];
1040 	u8         max_vxlan_udp_ports[0x8];
1041 	u8         reserved_at_38[0x6];
1042 	u8         max_geneve_opt_len[0x1];
1043 	u8         tunnel_stateless_geneve_rx[0x1];
1044 
1045 	u8         reserved_at_40[0x10];
1046 	u8         lro_min_mss_size[0x10];
1047 
1048 	u8         reserved_at_60[0x120];
1049 
1050 	u8         lro_timer_supported_periods[4][0x20];
1051 
1052 	u8         reserved_at_200[0x600];
1053 };
1054 
1055 enum {
1056 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1057 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1058 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1059 };
1060 
1061 struct mlx5_ifc_roce_cap_bits {
1062 	u8         roce_apm[0x1];
1063 	u8         reserved_at_1[0x3];
1064 	u8         sw_r_roce_src_udp_port[0x1];
1065 	u8         fl_rc_qp_when_roce_disabled[0x1];
1066 	u8         fl_rc_qp_when_roce_enabled[0x1];
1067 	u8         reserved_at_7[0x17];
1068 	u8	   qp_ts_format[0x2];
1069 
1070 	u8         reserved_at_20[0x60];
1071 
1072 	u8         reserved_at_80[0xc];
1073 	u8         l3_type[0x4];
1074 	u8         reserved_at_90[0x8];
1075 	u8         roce_version[0x8];
1076 
1077 	u8         reserved_at_a0[0x10];
1078 	u8         r_roce_dest_udp_port[0x10];
1079 
1080 	u8         r_roce_max_src_udp_port[0x10];
1081 	u8         r_roce_min_src_udp_port[0x10];
1082 
1083 	u8         reserved_at_e0[0x10];
1084 	u8         roce_address_table_size[0x10];
1085 
1086 	u8         reserved_at_100[0x700];
1087 };
1088 
1089 struct mlx5_ifc_sync_steering_in_bits {
1090 	u8         opcode[0x10];
1091 	u8         uid[0x10];
1092 
1093 	u8         reserved_at_20[0x10];
1094 	u8         op_mod[0x10];
1095 
1096 	u8         reserved_at_40[0xc0];
1097 };
1098 
1099 struct mlx5_ifc_sync_steering_out_bits {
1100 	u8         status[0x8];
1101 	u8         reserved_at_8[0x18];
1102 
1103 	u8         syndrome[0x20];
1104 
1105 	u8         reserved_at_40[0x40];
1106 };
1107 
1108 struct mlx5_ifc_device_mem_cap_bits {
1109 	u8         memic[0x1];
1110 	u8         reserved_at_1[0x1f];
1111 
1112 	u8         reserved_at_20[0xb];
1113 	u8         log_min_memic_alloc_size[0x5];
1114 	u8         reserved_at_30[0x8];
1115 	u8	   log_max_memic_addr_alignment[0x8];
1116 
1117 	u8         memic_bar_start_addr[0x40];
1118 
1119 	u8         memic_bar_size[0x20];
1120 
1121 	u8         max_memic_size[0x20];
1122 
1123 	u8         steering_sw_icm_start_address[0x40];
1124 
1125 	u8         reserved_at_100[0x8];
1126 	u8         log_header_modify_sw_icm_size[0x8];
1127 	u8         reserved_at_110[0x2];
1128 	u8         log_sw_icm_alloc_granularity[0x6];
1129 	u8         log_steering_sw_icm_size[0x8];
1130 
1131 	u8         reserved_at_120[0x18];
1132 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1133 
1134 	u8         header_modify_sw_icm_start_address[0x40];
1135 
1136 	u8         reserved_at_180[0x40];
1137 
1138 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1139 
1140 	u8         memic_operations[0x20];
1141 
1142 	u8         reserved_at_220[0x5e0];
1143 };
1144 
1145 struct mlx5_ifc_device_event_cap_bits {
1146 	u8         user_affiliated_events[4][0x40];
1147 
1148 	u8         user_unaffiliated_events[4][0x40];
1149 };
1150 
1151 struct mlx5_ifc_virtio_emulation_cap_bits {
1152 	u8         desc_tunnel_offload_type[0x1];
1153 	u8         eth_frame_offload_type[0x1];
1154 	u8         virtio_version_1_0[0x1];
1155 	u8         device_features_bits_mask[0xd];
1156 	u8         event_mode[0x8];
1157 	u8         virtio_queue_type[0x8];
1158 
1159 	u8         max_tunnel_desc[0x10];
1160 	u8         reserved_at_30[0x3];
1161 	u8         log_doorbell_stride[0x5];
1162 	u8         reserved_at_38[0x3];
1163 	u8         log_doorbell_bar_size[0x5];
1164 
1165 	u8         doorbell_bar_offset[0x40];
1166 
1167 	u8         max_emulated_devices[0x8];
1168 	u8         max_num_virtio_queues[0x18];
1169 
1170 	u8         reserved_at_a0[0x60];
1171 
1172 	u8         umem_1_buffer_param_a[0x20];
1173 
1174 	u8         umem_1_buffer_param_b[0x20];
1175 
1176 	u8         umem_2_buffer_param_a[0x20];
1177 
1178 	u8         umem_2_buffer_param_b[0x20];
1179 
1180 	u8         umem_3_buffer_param_a[0x20];
1181 
1182 	u8         umem_3_buffer_param_b[0x20];
1183 
1184 	u8         reserved_at_1c0[0x640];
1185 };
1186 
1187 enum {
1188 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1189 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1190 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1191 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1192 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1193 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1194 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1195 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1196 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1197 };
1198 
1199 enum {
1200 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1201 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1202 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1203 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1204 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1205 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1206 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1207 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1208 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1209 };
1210 
1211 struct mlx5_ifc_atomic_caps_bits {
1212 	u8         reserved_at_0[0x40];
1213 
1214 	u8         atomic_req_8B_endianness_mode[0x2];
1215 	u8         reserved_at_42[0x4];
1216 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1217 
1218 	u8         reserved_at_47[0x19];
1219 
1220 	u8         reserved_at_60[0x20];
1221 
1222 	u8         reserved_at_80[0x10];
1223 	u8         atomic_operations[0x10];
1224 
1225 	u8         reserved_at_a0[0x10];
1226 	u8         atomic_size_qp[0x10];
1227 
1228 	u8         reserved_at_c0[0x10];
1229 	u8         atomic_size_dc[0x10];
1230 
1231 	u8         reserved_at_e0[0x720];
1232 };
1233 
1234 struct mlx5_ifc_odp_cap_bits {
1235 	u8         reserved_at_0[0x40];
1236 
1237 	u8         sig[0x1];
1238 	u8         reserved_at_41[0x1f];
1239 
1240 	u8         reserved_at_60[0x20];
1241 
1242 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1243 
1244 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1245 
1246 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1247 
1248 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1249 
1250 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1251 
1252 	u8         reserved_at_120[0x6E0];
1253 };
1254 
1255 struct mlx5_ifc_calc_op {
1256 	u8        reserved_at_0[0x10];
1257 	u8        reserved_at_10[0x9];
1258 	u8        op_swap_endianness[0x1];
1259 	u8        op_min[0x1];
1260 	u8        op_xor[0x1];
1261 	u8        op_or[0x1];
1262 	u8        op_and[0x1];
1263 	u8        op_max[0x1];
1264 	u8        op_add[0x1];
1265 };
1266 
1267 struct mlx5_ifc_vector_calc_cap_bits {
1268 	u8         calc_matrix[0x1];
1269 	u8         reserved_at_1[0x1f];
1270 	u8         reserved_at_20[0x8];
1271 	u8         max_vec_count[0x8];
1272 	u8         reserved_at_30[0xd];
1273 	u8         max_chunk_size[0x3];
1274 	struct mlx5_ifc_calc_op calc0;
1275 	struct mlx5_ifc_calc_op calc1;
1276 	struct mlx5_ifc_calc_op calc2;
1277 	struct mlx5_ifc_calc_op calc3;
1278 
1279 	u8         reserved_at_c0[0x720];
1280 };
1281 
1282 struct mlx5_ifc_tls_cap_bits {
1283 	u8         tls_1_2_aes_gcm_128[0x1];
1284 	u8         tls_1_3_aes_gcm_128[0x1];
1285 	u8         tls_1_2_aes_gcm_256[0x1];
1286 	u8         tls_1_3_aes_gcm_256[0x1];
1287 	u8         reserved_at_4[0x1c];
1288 
1289 	u8         reserved_at_20[0x7e0];
1290 };
1291 
1292 struct mlx5_ifc_ipsec_cap_bits {
1293 	u8         ipsec_full_offload[0x1];
1294 	u8         ipsec_crypto_offload[0x1];
1295 	u8         ipsec_esn[0x1];
1296 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1297 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1298 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1299 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1300 	u8         reserved_at_7[0x4];
1301 	u8         log_max_ipsec_offload[0x5];
1302 	u8         reserved_at_10[0x10];
1303 
1304 	u8         min_log_ipsec_full_replay_window[0x8];
1305 	u8         max_log_ipsec_full_replay_window[0x8];
1306 	u8         reserved_at_30[0x7d0];
1307 };
1308 
1309 struct mlx5_ifc_macsec_cap_bits {
1310 	u8    macsec_epn[0x1];
1311 	u8    reserved_at_1[0x2];
1312 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1313 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1314 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1315 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1316 	u8    reserved_at_7[0x4];
1317 	u8    log_max_macsec_offload[0x5];
1318 	u8    reserved_at_10[0x10];
1319 
1320 	u8    min_log_macsec_full_replay_window[0x8];
1321 	u8    max_log_macsec_full_replay_window[0x8];
1322 	u8    reserved_at_30[0x10];
1323 
1324 	u8    reserved_at_40[0x7c0];
1325 };
1326 
1327 enum {
1328 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1329 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1330 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1331 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1332 };
1333 
1334 enum {
1335 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1336 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1337 };
1338 
1339 enum {
1340 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1341 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1342 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1343 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1344 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1345 };
1346 
1347 enum {
1348 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1349 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1350 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1351 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1352 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1353 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1354 };
1355 
1356 enum {
1357 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1358 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1359 };
1360 
1361 enum {
1362 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1363 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1364 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1365 };
1366 
1367 enum {
1368 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1369 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1370 };
1371 
1372 enum {
1373 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1374 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1375 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1376 };
1377 
1378 enum {
1379 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1380 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1381 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1382 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1383 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1384 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1385 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1386 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1387 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1388 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1389 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1390 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1391 };
1392 
1393 enum {
1394 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1395 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1396 };
1397 
1398 #define MLX5_FC_BULK_SIZE_FACTOR 128
1399 
1400 enum mlx5_fc_bulk_alloc_bitmask {
1401 	MLX5_FC_BULK_128   = (1 << 0),
1402 	MLX5_FC_BULK_256   = (1 << 1),
1403 	MLX5_FC_BULK_512   = (1 << 2),
1404 	MLX5_FC_BULK_1024  = (1 << 3),
1405 	MLX5_FC_BULK_2048  = (1 << 4),
1406 	MLX5_FC_BULK_4096  = (1 << 5),
1407 	MLX5_FC_BULK_8192  = (1 << 6),
1408 	MLX5_FC_BULK_16384 = (1 << 7),
1409 };
1410 
1411 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1412 
1413 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1414 
1415 enum {
1416 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1417 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1418 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1419 };
1420 
1421 struct mlx5_ifc_cmd_hca_cap_bits {
1422 	u8         reserved_at_0[0x10];
1423 	u8         shared_object_to_user_object_allowed[0x1];
1424 	u8         reserved_at_13[0xe];
1425 	u8         vhca_resource_manager[0x1];
1426 
1427 	u8         hca_cap_2[0x1];
1428 	u8         create_lag_when_not_master_up[0x1];
1429 	u8         dtor[0x1];
1430 	u8         event_on_vhca_state_teardown_request[0x1];
1431 	u8         event_on_vhca_state_in_use[0x1];
1432 	u8         event_on_vhca_state_active[0x1];
1433 	u8         event_on_vhca_state_allocated[0x1];
1434 	u8         event_on_vhca_state_invalid[0x1];
1435 	u8         reserved_at_28[0x8];
1436 	u8         vhca_id[0x10];
1437 
1438 	u8         reserved_at_40[0x40];
1439 
1440 	u8         log_max_srq_sz[0x8];
1441 	u8         log_max_qp_sz[0x8];
1442 	u8         event_cap[0x1];
1443 	u8         reserved_at_91[0x2];
1444 	u8         isolate_vl_tc_new[0x1];
1445 	u8         reserved_at_94[0x4];
1446 	u8         prio_tag_required[0x1];
1447 	u8         reserved_at_99[0x2];
1448 	u8         log_max_qp[0x5];
1449 
1450 	u8         reserved_at_a0[0x3];
1451 	u8	   ece_support[0x1];
1452 	u8	   reserved_at_a4[0x5];
1453 	u8         reg_c_preserve[0x1];
1454 	u8         reserved_at_aa[0x1];
1455 	u8         log_max_srq[0x5];
1456 	u8         reserved_at_b0[0x1];
1457 	u8         uplink_follow[0x1];
1458 	u8         ts_cqe_to_dest_cqn[0x1];
1459 	u8         reserved_at_b3[0x7];
1460 	u8         shampo[0x1];
1461 	u8         reserved_at_bb[0x5];
1462 
1463 	u8         max_sgl_for_optimized_performance[0x8];
1464 	u8         log_max_cq_sz[0x8];
1465 	u8         relaxed_ordering_write_umr[0x1];
1466 	u8         relaxed_ordering_read_umr[0x1];
1467 	u8         reserved_at_d2[0x7];
1468 	u8         virtio_net_device_emualtion_manager[0x1];
1469 	u8         virtio_blk_device_emualtion_manager[0x1];
1470 	u8         log_max_cq[0x5];
1471 
1472 	u8         log_max_eq_sz[0x8];
1473 	u8         relaxed_ordering_write[0x1];
1474 	u8         relaxed_ordering_read[0x1];
1475 	u8         log_max_mkey[0x6];
1476 	u8         reserved_at_f0[0x8];
1477 	u8         dump_fill_mkey[0x1];
1478 	u8         reserved_at_f9[0x2];
1479 	u8         fast_teardown[0x1];
1480 	u8         log_max_eq[0x4];
1481 
1482 	u8         max_indirection[0x8];
1483 	u8         fixed_buffer_size[0x1];
1484 	u8         log_max_mrw_sz[0x7];
1485 	u8         force_teardown[0x1];
1486 	u8         reserved_at_111[0x1];
1487 	u8         log_max_bsf_list_size[0x6];
1488 	u8         umr_extended_translation_offset[0x1];
1489 	u8         null_mkey[0x1];
1490 	u8         log_max_klm_list_size[0x6];
1491 
1492 	u8         reserved_at_120[0xa];
1493 	u8         log_max_ra_req_dc[0x6];
1494 	u8         reserved_at_130[0x2];
1495 	u8         eth_wqe_too_small[0x1];
1496 	u8         reserved_at_133[0x6];
1497 	u8         vnic_env_cq_overrun[0x1];
1498 	u8         log_max_ra_res_dc[0x6];
1499 
1500 	u8         reserved_at_140[0x5];
1501 	u8         release_all_pages[0x1];
1502 	u8         must_not_use[0x1];
1503 	u8         reserved_at_147[0x2];
1504 	u8         roce_accl[0x1];
1505 	u8         log_max_ra_req_qp[0x6];
1506 	u8         reserved_at_150[0xa];
1507 	u8         log_max_ra_res_qp[0x6];
1508 
1509 	u8         end_pad[0x1];
1510 	u8         cc_query_allowed[0x1];
1511 	u8         cc_modify_allowed[0x1];
1512 	u8         start_pad[0x1];
1513 	u8         cache_line_128byte[0x1];
1514 	u8         reserved_at_165[0x4];
1515 	u8         rts2rts_qp_counters_set_id[0x1];
1516 	u8         reserved_at_16a[0x2];
1517 	u8         vnic_env_int_rq_oob[0x1];
1518 	u8         sbcam_reg[0x1];
1519 	u8         reserved_at_16e[0x1];
1520 	u8         qcam_reg[0x1];
1521 	u8         gid_table_size[0x10];
1522 
1523 	u8         out_of_seq_cnt[0x1];
1524 	u8         vport_counters[0x1];
1525 	u8         retransmission_q_counters[0x1];
1526 	u8         debug[0x1];
1527 	u8         modify_rq_counter_set_id[0x1];
1528 	u8         rq_delay_drop[0x1];
1529 	u8         max_qp_cnt[0xa];
1530 	u8         pkey_table_size[0x10];
1531 
1532 	u8         vport_group_manager[0x1];
1533 	u8         vhca_group_manager[0x1];
1534 	u8         ib_virt[0x1];
1535 	u8         eth_virt[0x1];
1536 	u8         vnic_env_queue_counters[0x1];
1537 	u8         ets[0x1];
1538 	u8         nic_flow_table[0x1];
1539 	u8         eswitch_manager[0x1];
1540 	u8         device_memory[0x1];
1541 	u8         mcam_reg[0x1];
1542 	u8         pcam_reg[0x1];
1543 	u8         local_ca_ack_delay[0x5];
1544 	u8         port_module_event[0x1];
1545 	u8         enhanced_error_q_counters[0x1];
1546 	u8         ports_check[0x1];
1547 	u8         reserved_at_1b3[0x1];
1548 	u8         disable_link_up[0x1];
1549 	u8         beacon_led[0x1];
1550 	u8         port_type[0x2];
1551 	u8         num_ports[0x8];
1552 
1553 	u8         reserved_at_1c0[0x1];
1554 	u8         pps[0x1];
1555 	u8         pps_modify[0x1];
1556 	u8         log_max_msg[0x5];
1557 	u8         reserved_at_1c8[0x4];
1558 	u8         max_tc[0x4];
1559 	u8         temp_warn_event[0x1];
1560 	u8         dcbx[0x1];
1561 	u8         general_notification_event[0x1];
1562 	u8         reserved_at_1d3[0x2];
1563 	u8         fpga[0x1];
1564 	u8         rol_s[0x1];
1565 	u8         rol_g[0x1];
1566 	u8         reserved_at_1d8[0x1];
1567 	u8         wol_s[0x1];
1568 	u8         wol_g[0x1];
1569 	u8         wol_a[0x1];
1570 	u8         wol_b[0x1];
1571 	u8         wol_m[0x1];
1572 	u8         wol_u[0x1];
1573 	u8         wol_p[0x1];
1574 
1575 	u8         stat_rate_support[0x10];
1576 	u8         reserved_at_1f0[0x1];
1577 	u8         pci_sync_for_fw_update_event[0x1];
1578 	u8         reserved_at_1f2[0x6];
1579 	u8         init2_lag_tx_port_affinity[0x1];
1580 	u8         reserved_at_1fa[0x3];
1581 	u8         cqe_version[0x4];
1582 
1583 	u8         compact_address_vector[0x1];
1584 	u8         striding_rq[0x1];
1585 	u8         reserved_at_202[0x1];
1586 	u8         ipoib_enhanced_offloads[0x1];
1587 	u8         ipoib_basic_offloads[0x1];
1588 	u8         reserved_at_205[0x1];
1589 	u8         repeated_block_disabled[0x1];
1590 	u8         umr_modify_entity_size_disabled[0x1];
1591 	u8         umr_modify_atomic_disabled[0x1];
1592 	u8         umr_indirect_mkey_disabled[0x1];
1593 	u8         umr_fence[0x2];
1594 	u8         dc_req_scat_data_cqe[0x1];
1595 	u8         reserved_at_20d[0x2];
1596 	u8         drain_sigerr[0x1];
1597 	u8         cmdif_checksum[0x2];
1598 	u8         sigerr_cqe[0x1];
1599 	u8         reserved_at_213[0x1];
1600 	u8         wq_signature[0x1];
1601 	u8         sctr_data_cqe[0x1];
1602 	u8         reserved_at_216[0x1];
1603 	u8         sho[0x1];
1604 	u8         tph[0x1];
1605 	u8         rf[0x1];
1606 	u8         dct[0x1];
1607 	u8         qos[0x1];
1608 	u8         eth_net_offloads[0x1];
1609 	u8         roce[0x1];
1610 	u8         atomic[0x1];
1611 	u8         reserved_at_21f[0x1];
1612 
1613 	u8         cq_oi[0x1];
1614 	u8         cq_resize[0x1];
1615 	u8         cq_moderation[0x1];
1616 	u8         reserved_at_223[0x3];
1617 	u8         cq_eq_remap[0x1];
1618 	u8         pg[0x1];
1619 	u8         block_lb_mc[0x1];
1620 	u8         reserved_at_229[0x1];
1621 	u8         scqe_break_moderation[0x1];
1622 	u8         cq_period_start_from_cqe[0x1];
1623 	u8         cd[0x1];
1624 	u8         reserved_at_22d[0x1];
1625 	u8         apm[0x1];
1626 	u8         vector_calc[0x1];
1627 	u8         umr_ptr_rlky[0x1];
1628 	u8	   imaicl[0x1];
1629 	u8	   qp_packet_based[0x1];
1630 	u8         reserved_at_233[0x3];
1631 	u8         qkv[0x1];
1632 	u8         pkv[0x1];
1633 	u8         set_deth_sqpn[0x1];
1634 	u8         reserved_at_239[0x3];
1635 	u8         xrc[0x1];
1636 	u8         ud[0x1];
1637 	u8         uc[0x1];
1638 	u8         rc[0x1];
1639 
1640 	u8         uar_4k[0x1];
1641 	u8         reserved_at_241[0x9];
1642 	u8         uar_sz[0x6];
1643 	u8         port_selection_cap[0x1];
1644 	u8         reserved_at_248[0x1];
1645 	u8         umem_uid_0[0x1];
1646 	u8         reserved_at_250[0x5];
1647 	u8         log_pg_sz[0x8];
1648 
1649 	u8         bf[0x1];
1650 	u8         driver_version[0x1];
1651 	u8         pad_tx_eth_packet[0x1];
1652 	u8         reserved_at_263[0x3];
1653 	u8         mkey_by_name[0x1];
1654 	u8         reserved_at_267[0x4];
1655 
1656 	u8         log_bf_reg_size[0x5];
1657 
1658 	u8         reserved_at_270[0x6];
1659 	u8         lag_dct[0x2];
1660 	u8         lag_tx_port_affinity[0x1];
1661 	u8         lag_native_fdb_selection[0x1];
1662 	u8         reserved_at_27a[0x1];
1663 	u8         lag_master[0x1];
1664 	u8         num_lag_ports[0x4];
1665 
1666 	u8         reserved_at_280[0x10];
1667 	u8         max_wqe_sz_sq[0x10];
1668 
1669 	u8         reserved_at_2a0[0x10];
1670 	u8         max_wqe_sz_rq[0x10];
1671 
1672 	u8         max_flow_counter_31_16[0x10];
1673 	u8         max_wqe_sz_sq_dc[0x10];
1674 
1675 	u8         reserved_at_2e0[0x7];
1676 	u8         max_qp_mcg[0x19];
1677 
1678 	u8         reserved_at_300[0x10];
1679 	u8         flow_counter_bulk_alloc[0x8];
1680 	u8         log_max_mcg[0x8];
1681 
1682 	u8         reserved_at_320[0x3];
1683 	u8         log_max_transport_domain[0x5];
1684 	u8         reserved_at_328[0x3];
1685 	u8         log_max_pd[0x5];
1686 	u8         reserved_at_330[0xb];
1687 	u8         log_max_xrcd[0x5];
1688 
1689 	u8         nic_receive_steering_discard[0x1];
1690 	u8         receive_discard_vport_down[0x1];
1691 	u8         transmit_discard_vport_down[0x1];
1692 	u8         eq_overrun_count[0x1];
1693 	u8         reserved_at_344[0x1];
1694 	u8         invalid_command_count[0x1];
1695 	u8         quota_exceeded_count[0x1];
1696 	u8         reserved_at_347[0x1];
1697 	u8         log_max_flow_counter_bulk[0x8];
1698 	u8         max_flow_counter_15_0[0x10];
1699 
1700 
1701 	u8         reserved_at_360[0x3];
1702 	u8         log_max_rq[0x5];
1703 	u8         reserved_at_368[0x3];
1704 	u8         log_max_sq[0x5];
1705 	u8         reserved_at_370[0x3];
1706 	u8         log_max_tir[0x5];
1707 	u8         reserved_at_378[0x3];
1708 	u8         log_max_tis[0x5];
1709 
1710 	u8         basic_cyclic_rcv_wqe[0x1];
1711 	u8         reserved_at_381[0x2];
1712 	u8         log_max_rmp[0x5];
1713 	u8         reserved_at_388[0x3];
1714 	u8         log_max_rqt[0x5];
1715 	u8         reserved_at_390[0x3];
1716 	u8         log_max_rqt_size[0x5];
1717 	u8         reserved_at_398[0x3];
1718 	u8         log_max_tis_per_sq[0x5];
1719 
1720 	u8         ext_stride_num_range[0x1];
1721 	u8         roce_rw_supported[0x1];
1722 	u8         log_max_current_uc_list_wr_supported[0x1];
1723 	u8         log_max_stride_sz_rq[0x5];
1724 	u8         reserved_at_3a8[0x3];
1725 	u8         log_min_stride_sz_rq[0x5];
1726 	u8         reserved_at_3b0[0x3];
1727 	u8         log_max_stride_sz_sq[0x5];
1728 	u8         reserved_at_3b8[0x3];
1729 	u8         log_min_stride_sz_sq[0x5];
1730 
1731 	u8         hairpin[0x1];
1732 	u8         reserved_at_3c1[0x2];
1733 	u8         log_max_hairpin_queues[0x5];
1734 	u8         reserved_at_3c8[0x3];
1735 	u8         log_max_hairpin_wq_data_sz[0x5];
1736 	u8         reserved_at_3d0[0x3];
1737 	u8         log_max_hairpin_num_packets[0x5];
1738 	u8         reserved_at_3d8[0x3];
1739 	u8         log_max_wq_sz[0x5];
1740 
1741 	u8         nic_vport_change_event[0x1];
1742 	u8         disable_local_lb_uc[0x1];
1743 	u8         disable_local_lb_mc[0x1];
1744 	u8         log_min_hairpin_wq_data_sz[0x5];
1745 	u8         reserved_at_3e8[0x2];
1746 	u8         vhca_state[0x1];
1747 	u8         log_max_vlan_list[0x5];
1748 	u8         reserved_at_3f0[0x3];
1749 	u8         log_max_current_mc_list[0x5];
1750 	u8         reserved_at_3f8[0x3];
1751 	u8         log_max_current_uc_list[0x5];
1752 
1753 	u8         general_obj_types[0x40];
1754 
1755 	u8         sq_ts_format[0x2];
1756 	u8         rq_ts_format[0x2];
1757 	u8         steering_format_version[0x4];
1758 	u8         create_qp_start_hint[0x18];
1759 
1760 	u8         reserved_at_460[0x1];
1761 	u8         ats[0x1];
1762 	u8         reserved_at_462[0x1];
1763 	u8         log_max_uctx[0x5];
1764 	u8         reserved_at_468[0x2];
1765 	u8         ipsec_offload[0x1];
1766 	u8         log_max_umem[0x5];
1767 	u8         max_num_eqs[0x10];
1768 
1769 	u8         reserved_at_480[0x1];
1770 	u8         tls_tx[0x1];
1771 	u8         tls_rx[0x1];
1772 	u8         log_max_l2_table[0x5];
1773 	u8         reserved_at_488[0x8];
1774 	u8         log_uar_page_sz[0x10];
1775 
1776 	u8         reserved_at_4a0[0x20];
1777 	u8         device_frequency_mhz[0x20];
1778 	u8         device_frequency_khz[0x20];
1779 
1780 	u8         reserved_at_500[0x20];
1781 	u8	   num_of_uars_per_page[0x20];
1782 
1783 	u8         flex_parser_protocols[0x20];
1784 
1785 	u8         max_geneve_tlv_options[0x8];
1786 	u8         reserved_at_568[0x3];
1787 	u8         max_geneve_tlv_option_data_len[0x5];
1788 	u8         reserved_at_570[0x9];
1789 	u8         adv_virtualization[0x1];
1790 	u8         reserved_at_57a[0x6];
1791 
1792 	u8	   reserved_at_580[0xb];
1793 	u8	   log_max_dci_stream_channels[0x5];
1794 	u8	   reserved_at_590[0x3];
1795 	u8	   log_max_dci_errored_streams[0x5];
1796 	u8	   reserved_at_598[0x8];
1797 
1798 	u8         reserved_at_5a0[0x10];
1799 	u8         enhanced_cqe_compression[0x1];
1800 	u8         reserved_at_5b1[0x2];
1801 	u8         log_max_dek[0x5];
1802 	u8         reserved_at_5b8[0x4];
1803 	u8         mini_cqe_resp_stride_index[0x1];
1804 	u8         cqe_128_always[0x1];
1805 	u8         cqe_compression_128[0x1];
1806 	u8         cqe_compression[0x1];
1807 
1808 	u8         cqe_compression_timeout[0x10];
1809 	u8         cqe_compression_max_num[0x10];
1810 
1811 	u8         reserved_at_5e0[0x8];
1812 	u8         flex_parser_id_gtpu_dw_0[0x4];
1813 	u8         reserved_at_5ec[0x4];
1814 	u8         tag_matching[0x1];
1815 	u8         rndv_offload_rc[0x1];
1816 	u8         rndv_offload_dc[0x1];
1817 	u8         log_tag_matching_list_sz[0x5];
1818 	u8         reserved_at_5f8[0x3];
1819 	u8         log_max_xrq[0x5];
1820 
1821 	u8	   affiliate_nic_vport_criteria[0x8];
1822 	u8	   native_port_num[0x8];
1823 	u8	   num_vhca_ports[0x8];
1824 	u8         flex_parser_id_gtpu_teid[0x4];
1825 	u8         reserved_at_61c[0x2];
1826 	u8	   sw_owner_id[0x1];
1827 	u8         reserved_at_61f[0x1];
1828 
1829 	u8         max_num_of_monitor_counters[0x10];
1830 	u8         num_ppcnt_monitor_counters[0x10];
1831 
1832 	u8         max_num_sf[0x10];
1833 	u8         num_q_monitor_counters[0x10];
1834 
1835 	u8         reserved_at_660[0x20];
1836 
1837 	u8         sf[0x1];
1838 	u8         sf_set_partition[0x1];
1839 	u8         reserved_at_682[0x1];
1840 	u8         log_max_sf[0x5];
1841 	u8         apu[0x1];
1842 	u8         reserved_at_689[0x4];
1843 	u8         migration[0x1];
1844 	u8         reserved_at_68e[0x2];
1845 	u8         log_min_sf_size[0x8];
1846 	u8         max_num_sf_partitions[0x8];
1847 
1848 	u8         uctx_cap[0x20];
1849 
1850 	u8         reserved_at_6c0[0x4];
1851 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1852 	u8         flex_parser_id_icmp_dw1[0x4];
1853 	u8         flex_parser_id_icmp_dw0[0x4];
1854 	u8         flex_parser_id_icmpv6_dw1[0x4];
1855 	u8         flex_parser_id_icmpv6_dw0[0x4];
1856 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1857 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1858 
1859 	u8         max_num_match_definer[0x10];
1860 	u8	   sf_base_id[0x10];
1861 
1862 	u8         flex_parser_id_gtpu_dw_2[0x4];
1863 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1864 	u8	   num_total_dynamic_vf_msix[0x18];
1865 	u8	   reserved_at_720[0x14];
1866 	u8	   dynamic_msix_table_size[0xc];
1867 	u8	   reserved_at_740[0xc];
1868 	u8	   min_dynamic_vf_msix_table_size[0x4];
1869 	u8	   reserved_at_750[0x4];
1870 	u8	   max_dynamic_vf_msix_table_size[0xc];
1871 
1872 	u8	   reserved_at_760[0x20];
1873 	u8	   vhca_tunnel_commands[0x40];
1874 	u8         match_definer_format_supported[0x40];
1875 };
1876 
1877 struct mlx5_ifc_cmd_hca_cap_2_bits {
1878 	u8	   reserved_at_0[0xa0];
1879 
1880 	u8	   max_reformat_insert_size[0x8];
1881 	u8	   max_reformat_insert_offset[0x8];
1882 	u8	   max_reformat_remove_size[0x8];
1883 	u8	   max_reformat_remove_offset[0x8];
1884 
1885 	u8	   reserved_at_c0[0xe0];
1886 
1887 	u8	   reserved_at_1a0[0xb];
1888 	u8	   log_min_mkey_entity_size[0x5];
1889 	u8	   reserved_at_1b0[0x10];
1890 
1891 	u8	   reserved_at_1c0[0x60];
1892 
1893 	u8	   reserved_at_220[0x1];
1894 	u8	   sw_vhca_id_valid[0x1];
1895 	u8	   sw_vhca_id[0xe];
1896 	u8	   reserved_at_230[0x10];
1897 
1898 	u8	   reserved_at_240[0xb];
1899 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
1900 	u8	   reserved_at_250[0x10];
1901 
1902 	u8	   reserved_at_260[0x5a0];
1903 };
1904 
1905 enum mlx5_ifc_flow_destination_type {
1906 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1907 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1908 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1909 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1910 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1911 };
1912 
1913 enum mlx5_flow_table_miss_action {
1914 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1915 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1916 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1917 };
1918 
1919 struct mlx5_ifc_dest_format_struct_bits {
1920 	u8         destination_type[0x8];
1921 	u8         destination_id[0x18];
1922 
1923 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1924 	u8         packet_reformat[0x1];
1925 	u8         reserved_at_22[0xe];
1926 	u8         destination_eswitch_owner_vhca_id[0x10];
1927 };
1928 
1929 struct mlx5_ifc_flow_counter_list_bits {
1930 	u8         flow_counter_id[0x20];
1931 
1932 	u8         reserved_at_20[0x20];
1933 };
1934 
1935 struct mlx5_ifc_extended_dest_format_bits {
1936 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
1937 
1938 	u8         packet_reformat_id[0x20];
1939 
1940 	u8         reserved_at_60[0x20];
1941 };
1942 
1943 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1944 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1945 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1946 };
1947 
1948 struct mlx5_ifc_fte_match_param_bits {
1949 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1950 
1951 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1952 
1953 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1954 
1955 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1956 
1957 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1958 
1959 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1960 
1961 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1962 
1963 	u8         reserved_at_e00[0x200];
1964 };
1965 
1966 enum {
1967 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1968 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1969 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1970 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1971 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1972 };
1973 
1974 struct mlx5_ifc_rx_hash_field_select_bits {
1975 	u8         l3_prot_type[0x1];
1976 	u8         l4_prot_type[0x1];
1977 	u8         selected_fields[0x1e];
1978 };
1979 
1980 enum {
1981 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1982 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1983 };
1984 
1985 enum {
1986 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1987 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1988 };
1989 
1990 struct mlx5_ifc_wq_bits {
1991 	u8         wq_type[0x4];
1992 	u8         wq_signature[0x1];
1993 	u8         end_padding_mode[0x2];
1994 	u8         cd_slave[0x1];
1995 	u8         reserved_at_8[0x18];
1996 
1997 	u8         hds_skip_first_sge[0x1];
1998 	u8         log2_hds_buf_size[0x3];
1999 	u8         reserved_at_24[0x7];
2000 	u8         page_offset[0x5];
2001 	u8         lwm[0x10];
2002 
2003 	u8         reserved_at_40[0x8];
2004 	u8         pd[0x18];
2005 
2006 	u8         reserved_at_60[0x8];
2007 	u8         uar_page[0x18];
2008 
2009 	u8         dbr_addr[0x40];
2010 
2011 	u8         hw_counter[0x20];
2012 
2013 	u8         sw_counter[0x20];
2014 
2015 	u8         reserved_at_100[0xc];
2016 	u8         log_wq_stride[0x4];
2017 	u8         reserved_at_110[0x3];
2018 	u8         log_wq_pg_sz[0x5];
2019 	u8         reserved_at_118[0x3];
2020 	u8         log_wq_sz[0x5];
2021 
2022 	u8         dbr_umem_valid[0x1];
2023 	u8         wq_umem_valid[0x1];
2024 	u8         reserved_at_122[0x1];
2025 	u8         log_hairpin_num_packets[0x5];
2026 	u8         reserved_at_128[0x3];
2027 	u8         log_hairpin_data_sz[0x5];
2028 
2029 	u8         reserved_at_130[0x4];
2030 	u8         log_wqe_num_of_strides[0x4];
2031 	u8         two_byte_shift_en[0x1];
2032 	u8         reserved_at_139[0x4];
2033 	u8         log_wqe_stride_size[0x3];
2034 
2035 	u8         reserved_at_140[0x80];
2036 
2037 	u8         headers_mkey[0x20];
2038 
2039 	u8         shampo_enable[0x1];
2040 	u8         reserved_at_1e1[0x4];
2041 	u8         log_reservation_size[0x3];
2042 	u8         reserved_at_1e8[0x5];
2043 	u8         log_max_num_of_packets_per_reservation[0x3];
2044 	u8         reserved_at_1f0[0x6];
2045 	u8         log_headers_entry_size[0x2];
2046 	u8         reserved_at_1f8[0x4];
2047 	u8         log_headers_buffer_entry_num[0x4];
2048 
2049 	u8         reserved_at_200[0x400];
2050 
2051 	struct mlx5_ifc_cmd_pas_bits pas[];
2052 };
2053 
2054 struct mlx5_ifc_rq_num_bits {
2055 	u8         reserved_at_0[0x8];
2056 	u8         rq_num[0x18];
2057 };
2058 
2059 struct mlx5_ifc_mac_address_layout_bits {
2060 	u8         reserved_at_0[0x10];
2061 	u8         mac_addr_47_32[0x10];
2062 
2063 	u8         mac_addr_31_0[0x20];
2064 };
2065 
2066 struct mlx5_ifc_vlan_layout_bits {
2067 	u8         reserved_at_0[0x14];
2068 	u8         vlan[0x0c];
2069 
2070 	u8         reserved_at_20[0x20];
2071 };
2072 
2073 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2074 	u8         reserved_at_0[0xa0];
2075 
2076 	u8         min_time_between_cnps[0x20];
2077 
2078 	u8         reserved_at_c0[0x12];
2079 	u8         cnp_dscp[0x6];
2080 	u8         reserved_at_d8[0x4];
2081 	u8         cnp_prio_mode[0x1];
2082 	u8         cnp_802p_prio[0x3];
2083 
2084 	u8         reserved_at_e0[0x720];
2085 };
2086 
2087 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2088 	u8         reserved_at_0[0x60];
2089 
2090 	u8         reserved_at_60[0x4];
2091 	u8         clamp_tgt_rate[0x1];
2092 	u8         reserved_at_65[0x3];
2093 	u8         clamp_tgt_rate_after_time_inc[0x1];
2094 	u8         reserved_at_69[0x17];
2095 
2096 	u8         reserved_at_80[0x20];
2097 
2098 	u8         rpg_time_reset[0x20];
2099 
2100 	u8         rpg_byte_reset[0x20];
2101 
2102 	u8         rpg_threshold[0x20];
2103 
2104 	u8         rpg_max_rate[0x20];
2105 
2106 	u8         rpg_ai_rate[0x20];
2107 
2108 	u8         rpg_hai_rate[0x20];
2109 
2110 	u8         rpg_gd[0x20];
2111 
2112 	u8         rpg_min_dec_fac[0x20];
2113 
2114 	u8         rpg_min_rate[0x20];
2115 
2116 	u8         reserved_at_1c0[0xe0];
2117 
2118 	u8         rate_to_set_on_first_cnp[0x20];
2119 
2120 	u8         dce_tcp_g[0x20];
2121 
2122 	u8         dce_tcp_rtt[0x20];
2123 
2124 	u8         rate_reduce_monitor_period[0x20];
2125 
2126 	u8         reserved_at_320[0x20];
2127 
2128 	u8         initial_alpha_value[0x20];
2129 
2130 	u8         reserved_at_360[0x4a0];
2131 };
2132 
2133 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2134 	u8         reserved_at_0[0x80];
2135 
2136 	u8         rppp_max_rps[0x20];
2137 
2138 	u8         rpg_time_reset[0x20];
2139 
2140 	u8         rpg_byte_reset[0x20];
2141 
2142 	u8         rpg_threshold[0x20];
2143 
2144 	u8         rpg_max_rate[0x20];
2145 
2146 	u8         rpg_ai_rate[0x20];
2147 
2148 	u8         rpg_hai_rate[0x20];
2149 
2150 	u8         rpg_gd[0x20];
2151 
2152 	u8         rpg_min_dec_fac[0x20];
2153 
2154 	u8         rpg_min_rate[0x20];
2155 
2156 	u8         reserved_at_1c0[0x640];
2157 };
2158 
2159 enum {
2160 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2161 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2162 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2163 };
2164 
2165 struct mlx5_ifc_resize_field_select_bits {
2166 	u8         resize_field_select[0x20];
2167 };
2168 
2169 struct mlx5_ifc_resource_dump_bits {
2170 	u8         more_dump[0x1];
2171 	u8         inline_dump[0x1];
2172 	u8         reserved_at_2[0xa];
2173 	u8         seq_num[0x4];
2174 	u8         segment_type[0x10];
2175 
2176 	u8         reserved_at_20[0x10];
2177 	u8         vhca_id[0x10];
2178 
2179 	u8         index1[0x20];
2180 
2181 	u8         index2[0x20];
2182 
2183 	u8         num_of_obj1[0x10];
2184 	u8         num_of_obj2[0x10];
2185 
2186 	u8         reserved_at_a0[0x20];
2187 
2188 	u8         device_opaque[0x40];
2189 
2190 	u8         mkey[0x20];
2191 
2192 	u8         size[0x20];
2193 
2194 	u8         address[0x40];
2195 
2196 	u8         inline_data[52][0x20];
2197 };
2198 
2199 struct mlx5_ifc_resource_dump_menu_record_bits {
2200 	u8         reserved_at_0[0x4];
2201 	u8         num_of_obj2_supports_active[0x1];
2202 	u8         num_of_obj2_supports_all[0x1];
2203 	u8         must_have_num_of_obj2[0x1];
2204 	u8         support_num_of_obj2[0x1];
2205 	u8         num_of_obj1_supports_active[0x1];
2206 	u8         num_of_obj1_supports_all[0x1];
2207 	u8         must_have_num_of_obj1[0x1];
2208 	u8         support_num_of_obj1[0x1];
2209 	u8         must_have_index2[0x1];
2210 	u8         support_index2[0x1];
2211 	u8         must_have_index1[0x1];
2212 	u8         support_index1[0x1];
2213 	u8         segment_type[0x10];
2214 
2215 	u8         segment_name[4][0x20];
2216 
2217 	u8         index1_name[4][0x20];
2218 
2219 	u8         index2_name[4][0x20];
2220 };
2221 
2222 struct mlx5_ifc_resource_dump_segment_header_bits {
2223 	u8         length_dw[0x10];
2224 	u8         segment_type[0x10];
2225 };
2226 
2227 struct mlx5_ifc_resource_dump_command_segment_bits {
2228 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2229 
2230 	u8         segment_called[0x10];
2231 	u8         vhca_id[0x10];
2232 
2233 	u8         index1[0x20];
2234 
2235 	u8         index2[0x20];
2236 
2237 	u8         num_of_obj1[0x10];
2238 	u8         num_of_obj2[0x10];
2239 };
2240 
2241 struct mlx5_ifc_resource_dump_error_segment_bits {
2242 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2243 
2244 	u8         reserved_at_20[0x10];
2245 	u8         syndrome_id[0x10];
2246 
2247 	u8         reserved_at_40[0x40];
2248 
2249 	u8         error[8][0x20];
2250 };
2251 
2252 struct mlx5_ifc_resource_dump_info_segment_bits {
2253 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2254 
2255 	u8         reserved_at_20[0x18];
2256 	u8         dump_version[0x8];
2257 
2258 	u8         hw_version[0x20];
2259 
2260 	u8         fw_version[0x20];
2261 };
2262 
2263 struct mlx5_ifc_resource_dump_menu_segment_bits {
2264 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2265 
2266 	u8         reserved_at_20[0x10];
2267 	u8         num_of_records[0x10];
2268 
2269 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2270 };
2271 
2272 struct mlx5_ifc_resource_dump_resource_segment_bits {
2273 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2274 
2275 	u8         reserved_at_20[0x20];
2276 
2277 	u8         index1[0x20];
2278 
2279 	u8         index2[0x20];
2280 
2281 	u8         payload[][0x20];
2282 };
2283 
2284 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2285 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2286 };
2287 
2288 struct mlx5_ifc_menu_resource_dump_response_bits {
2289 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2290 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2291 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2292 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2293 };
2294 
2295 enum {
2296 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2297 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2298 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2299 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2300 };
2301 
2302 struct mlx5_ifc_modify_field_select_bits {
2303 	u8         modify_field_select[0x20];
2304 };
2305 
2306 struct mlx5_ifc_field_select_r_roce_np_bits {
2307 	u8         field_select_r_roce_np[0x20];
2308 };
2309 
2310 struct mlx5_ifc_field_select_r_roce_rp_bits {
2311 	u8         field_select_r_roce_rp[0x20];
2312 };
2313 
2314 enum {
2315 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2316 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2317 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2318 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2319 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2320 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2321 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2322 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2323 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2324 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2325 };
2326 
2327 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2328 	u8         field_select_8021qaurp[0x20];
2329 };
2330 
2331 struct mlx5_ifc_phys_layer_cntrs_bits {
2332 	u8         time_since_last_clear_high[0x20];
2333 
2334 	u8         time_since_last_clear_low[0x20];
2335 
2336 	u8         symbol_errors_high[0x20];
2337 
2338 	u8         symbol_errors_low[0x20];
2339 
2340 	u8         sync_headers_errors_high[0x20];
2341 
2342 	u8         sync_headers_errors_low[0x20];
2343 
2344 	u8         edpl_bip_errors_lane0_high[0x20];
2345 
2346 	u8         edpl_bip_errors_lane0_low[0x20];
2347 
2348 	u8         edpl_bip_errors_lane1_high[0x20];
2349 
2350 	u8         edpl_bip_errors_lane1_low[0x20];
2351 
2352 	u8         edpl_bip_errors_lane2_high[0x20];
2353 
2354 	u8         edpl_bip_errors_lane2_low[0x20];
2355 
2356 	u8         edpl_bip_errors_lane3_high[0x20];
2357 
2358 	u8         edpl_bip_errors_lane3_low[0x20];
2359 
2360 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2361 
2362 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2363 
2364 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2365 
2366 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2367 
2368 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2369 
2370 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2371 
2372 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2373 
2374 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2375 
2376 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2377 
2378 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2379 
2380 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2381 
2382 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2383 
2384 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2385 
2386 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2387 
2388 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2389 
2390 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2391 
2392 	u8         rs_fec_corrected_blocks_high[0x20];
2393 
2394 	u8         rs_fec_corrected_blocks_low[0x20];
2395 
2396 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2397 
2398 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2399 
2400 	u8         rs_fec_no_errors_blocks_high[0x20];
2401 
2402 	u8         rs_fec_no_errors_blocks_low[0x20];
2403 
2404 	u8         rs_fec_single_error_blocks_high[0x20];
2405 
2406 	u8         rs_fec_single_error_blocks_low[0x20];
2407 
2408 	u8         rs_fec_corrected_symbols_total_high[0x20];
2409 
2410 	u8         rs_fec_corrected_symbols_total_low[0x20];
2411 
2412 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2413 
2414 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2415 
2416 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2417 
2418 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2419 
2420 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2421 
2422 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2423 
2424 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2425 
2426 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2427 
2428 	u8         link_down_events[0x20];
2429 
2430 	u8         successful_recovery_events[0x20];
2431 
2432 	u8         reserved_at_640[0x180];
2433 };
2434 
2435 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2436 	u8         time_since_last_clear_high[0x20];
2437 
2438 	u8         time_since_last_clear_low[0x20];
2439 
2440 	u8         phy_received_bits_high[0x20];
2441 
2442 	u8         phy_received_bits_low[0x20];
2443 
2444 	u8         phy_symbol_errors_high[0x20];
2445 
2446 	u8         phy_symbol_errors_low[0x20];
2447 
2448 	u8         phy_corrected_bits_high[0x20];
2449 
2450 	u8         phy_corrected_bits_low[0x20];
2451 
2452 	u8         phy_corrected_bits_lane0_high[0x20];
2453 
2454 	u8         phy_corrected_bits_lane0_low[0x20];
2455 
2456 	u8         phy_corrected_bits_lane1_high[0x20];
2457 
2458 	u8         phy_corrected_bits_lane1_low[0x20];
2459 
2460 	u8         phy_corrected_bits_lane2_high[0x20];
2461 
2462 	u8         phy_corrected_bits_lane2_low[0x20];
2463 
2464 	u8         phy_corrected_bits_lane3_high[0x20];
2465 
2466 	u8         phy_corrected_bits_lane3_low[0x20];
2467 
2468 	u8         reserved_at_200[0x5c0];
2469 };
2470 
2471 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2472 	u8	   symbol_error_counter[0x10];
2473 
2474 	u8         link_error_recovery_counter[0x8];
2475 
2476 	u8         link_downed_counter[0x8];
2477 
2478 	u8         port_rcv_errors[0x10];
2479 
2480 	u8         port_rcv_remote_physical_errors[0x10];
2481 
2482 	u8         port_rcv_switch_relay_errors[0x10];
2483 
2484 	u8         port_xmit_discards[0x10];
2485 
2486 	u8         port_xmit_constraint_errors[0x8];
2487 
2488 	u8         port_rcv_constraint_errors[0x8];
2489 
2490 	u8         reserved_at_70[0x8];
2491 
2492 	u8         link_overrun_errors[0x8];
2493 
2494 	u8	   reserved_at_80[0x10];
2495 
2496 	u8         vl_15_dropped[0x10];
2497 
2498 	u8	   reserved_at_a0[0x80];
2499 
2500 	u8         port_xmit_wait[0x20];
2501 };
2502 
2503 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2504 	u8         transmit_queue_high[0x20];
2505 
2506 	u8         transmit_queue_low[0x20];
2507 
2508 	u8         no_buffer_discard_uc_high[0x20];
2509 
2510 	u8         no_buffer_discard_uc_low[0x20];
2511 
2512 	u8         reserved_at_80[0x740];
2513 };
2514 
2515 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2516 	u8         wred_discard_high[0x20];
2517 
2518 	u8         wred_discard_low[0x20];
2519 
2520 	u8         ecn_marked_tc_high[0x20];
2521 
2522 	u8         ecn_marked_tc_low[0x20];
2523 
2524 	u8         reserved_at_80[0x740];
2525 };
2526 
2527 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2528 	u8         rx_octets_high[0x20];
2529 
2530 	u8         rx_octets_low[0x20];
2531 
2532 	u8         reserved_at_40[0xc0];
2533 
2534 	u8         rx_frames_high[0x20];
2535 
2536 	u8         rx_frames_low[0x20];
2537 
2538 	u8         tx_octets_high[0x20];
2539 
2540 	u8         tx_octets_low[0x20];
2541 
2542 	u8         reserved_at_180[0xc0];
2543 
2544 	u8         tx_frames_high[0x20];
2545 
2546 	u8         tx_frames_low[0x20];
2547 
2548 	u8         rx_pause_high[0x20];
2549 
2550 	u8         rx_pause_low[0x20];
2551 
2552 	u8         rx_pause_duration_high[0x20];
2553 
2554 	u8         rx_pause_duration_low[0x20];
2555 
2556 	u8         tx_pause_high[0x20];
2557 
2558 	u8         tx_pause_low[0x20];
2559 
2560 	u8         tx_pause_duration_high[0x20];
2561 
2562 	u8         tx_pause_duration_low[0x20];
2563 
2564 	u8         rx_pause_transition_high[0x20];
2565 
2566 	u8         rx_pause_transition_low[0x20];
2567 
2568 	u8         rx_discards_high[0x20];
2569 
2570 	u8         rx_discards_low[0x20];
2571 
2572 	u8         device_stall_minor_watermark_cnt_high[0x20];
2573 
2574 	u8         device_stall_minor_watermark_cnt_low[0x20];
2575 
2576 	u8         device_stall_critical_watermark_cnt_high[0x20];
2577 
2578 	u8         device_stall_critical_watermark_cnt_low[0x20];
2579 
2580 	u8         reserved_at_480[0x340];
2581 };
2582 
2583 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2584 	u8         port_transmit_wait_high[0x20];
2585 
2586 	u8         port_transmit_wait_low[0x20];
2587 
2588 	u8         reserved_at_40[0x100];
2589 
2590 	u8         rx_buffer_almost_full_high[0x20];
2591 
2592 	u8         rx_buffer_almost_full_low[0x20];
2593 
2594 	u8         rx_buffer_full_high[0x20];
2595 
2596 	u8         rx_buffer_full_low[0x20];
2597 
2598 	u8         rx_icrc_encapsulated_high[0x20];
2599 
2600 	u8         rx_icrc_encapsulated_low[0x20];
2601 
2602 	u8         reserved_at_200[0x5c0];
2603 };
2604 
2605 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2606 	u8         dot3stats_alignment_errors_high[0x20];
2607 
2608 	u8         dot3stats_alignment_errors_low[0x20];
2609 
2610 	u8         dot3stats_fcs_errors_high[0x20];
2611 
2612 	u8         dot3stats_fcs_errors_low[0x20];
2613 
2614 	u8         dot3stats_single_collision_frames_high[0x20];
2615 
2616 	u8         dot3stats_single_collision_frames_low[0x20];
2617 
2618 	u8         dot3stats_multiple_collision_frames_high[0x20];
2619 
2620 	u8         dot3stats_multiple_collision_frames_low[0x20];
2621 
2622 	u8         dot3stats_sqe_test_errors_high[0x20];
2623 
2624 	u8         dot3stats_sqe_test_errors_low[0x20];
2625 
2626 	u8         dot3stats_deferred_transmissions_high[0x20];
2627 
2628 	u8         dot3stats_deferred_transmissions_low[0x20];
2629 
2630 	u8         dot3stats_late_collisions_high[0x20];
2631 
2632 	u8         dot3stats_late_collisions_low[0x20];
2633 
2634 	u8         dot3stats_excessive_collisions_high[0x20];
2635 
2636 	u8         dot3stats_excessive_collisions_low[0x20];
2637 
2638 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2639 
2640 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2641 
2642 	u8         dot3stats_carrier_sense_errors_high[0x20];
2643 
2644 	u8         dot3stats_carrier_sense_errors_low[0x20];
2645 
2646 	u8         dot3stats_frame_too_longs_high[0x20];
2647 
2648 	u8         dot3stats_frame_too_longs_low[0x20];
2649 
2650 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2651 
2652 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2653 
2654 	u8         dot3stats_symbol_errors_high[0x20];
2655 
2656 	u8         dot3stats_symbol_errors_low[0x20];
2657 
2658 	u8         dot3control_in_unknown_opcodes_high[0x20];
2659 
2660 	u8         dot3control_in_unknown_opcodes_low[0x20];
2661 
2662 	u8         dot3in_pause_frames_high[0x20];
2663 
2664 	u8         dot3in_pause_frames_low[0x20];
2665 
2666 	u8         dot3out_pause_frames_high[0x20];
2667 
2668 	u8         dot3out_pause_frames_low[0x20];
2669 
2670 	u8         reserved_at_400[0x3c0];
2671 };
2672 
2673 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2674 	u8         ether_stats_drop_events_high[0x20];
2675 
2676 	u8         ether_stats_drop_events_low[0x20];
2677 
2678 	u8         ether_stats_octets_high[0x20];
2679 
2680 	u8         ether_stats_octets_low[0x20];
2681 
2682 	u8         ether_stats_pkts_high[0x20];
2683 
2684 	u8         ether_stats_pkts_low[0x20];
2685 
2686 	u8         ether_stats_broadcast_pkts_high[0x20];
2687 
2688 	u8         ether_stats_broadcast_pkts_low[0x20];
2689 
2690 	u8         ether_stats_multicast_pkts_high[0x20];
2691 
2692 	u8         ether_stats_multicast_pkts_low[0x20];
2693 
2694 	u8         ether_stats_crc_align_errors_high[0x20];
2695 
2696 	u8         ether_stats_crc_align_errors_low[0x20];
2697 
2698 	u8         ether_stats_undersize_pkts_high[0x20];
2699 
2700 	u8         ether_stats_undersize_pkts_low[0x20];
2701 
2702 	u8         ether_stats_oversize_pkts_high[0x20];
2703 
2704 	u8         ether_stats_oversize_pkts_low[0x20];
2705 
2706 	u8         ether_stats_fragments_high[0x20];
2707 
2708 	u8         ether_stats_fragments_low[0x20];
2709 
2710 	u8         ether_stats_jabbers_high[0x20];
2711 
2712 	u8         ether_stats_jabbers_low[0x20];
2713 
2714 	u8         ether_stats_collisions_high[0x20];
2715 
2716 	u8         ether_stats_collisions_low[0x20];
2717 
2718 	u8         ether_stats_pkts64octets_high[0x20];
2719 
2720 	u8         ether_stats_pkts64octets_low[0x20];
2721 
2722 	u8         ether_stats_pkts65to127octets_high[0x20];
2723 
2724 	u8         ether_stats_pkts65to127octets_low[0x20];
2725 
2726 	u8         ether_stats_pkts128to255octets_high[0x20];
2727 
2728 	u8         ether_stats_pkts128to255octets_low[0x20];
2729 
2730 	u8         ether_stats_pkts256to511octets_high[0x20];
2731 
2732 	u8         ether_stats_pkts256to511octets_low[0x20];
2733 
2734 	u8         ether_stats_pkts512to1023octets_high[0x20];
2735 
2736 	u8         ether_stats_pkts512to1023octets_low[0x20];
2737 
2738 	u8         ether_stats_pkts1024to1518octets_high[0x20];
2739 
2740 	u8         ether_stats_pkts1024to1518octets_low[0x20];
2741 
2742 	u8         ether_stats_pkts1519to2047octets_high[0x20];
2743 
2744 	u8         ether_stats_pkts1519to2047octets_low[0x20];
2745 
2746 	u8         ether_stats_pkts2048to4095octets_high[0x20];
2747 
2748 	u8         ether_stats_pkts2048to4095octets_low[0x20];
2749 
2750 	u8         ether_stats_pkts4096to8191octets_high[0x20];
2751 
2752 	u8         ether_stats_pkts4096to8191octets_low[0x20];
2753 
2754 	u8         ether_stats_pkts8192to10239octets_high[0x20];
2755 
2756 	u8         ether_stats_pkts8192to10239octets_low[0x20];
2757 
2758 	u8         reserved_at_540[0x280];
2759 };
2760 
2761 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2762 	u8         if_in_octets_high[0x20];
2763 
2764 	u8         if_in_octets_low[0x20];
2765 
2766 	u8         if_in_ucast_pkts_high[0x20];
2767 
2768 	u8         if_in_ucast_pkts_low[0x20];
2769 
2770 	u8         if_in_discards_high[0x20];
2771 
2772 	u8         if_in_discards_low[0x20];
2773 
2774 	u8         if_in_errors_high[0x20];
2775 
2776 	u8         if_in_errors_low[0x20];
2777 
2778 	u8         if_in_unknown_protos_high[0x20];
2779 
2780 	u8         if_in_unknown_protos_low[0x20];
2781 
2782 	u8         if_out_octets_high[0x20];
2783 
2784 	u8         if_out_octets_low[0x20];
2785 
2786 	u8         if_out_ucast_pkts_high[0x20];
2787 
2788 	u8         if_out_ucast_pkts_low[0x20];
2789 
2790 	u8         if_out_discards_high[0x20];
2791 
2792 	u8         if_out_discards_low[0x20];
2793 
2794 	u8         if_out_errors_high[0x20];
2795 
2796 	u8         if_out_errors_low[0x20];
2797 
2798 	u8         if_in_multicast_pkts_high[0x20];
2799 
2800 	u8         if_in_multicast_pkts_low[0x20];
2801 
2802 	u8         if_in_broadcast_pkts_high[0x20];
2803 
2804 	u8         if_in_broadcast_pkts_low[0x20];
2805 
2806 	u8         if_out_multicast_pkts_high[0x20];
2807 
2808 	u8         if_out_multicast_pkts_low[0x20];
2809 
2810 	u8         if_out_broadcast_pkts_high[0x20];
2811 
2812 	u8         if_out_broadcast_pkts_low[0x20];
2813 
2814 	u8         reserved_at_340[0x480];
2815 };
2816 
2817 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2818 	u8         a_frames_transmitted_ok_high[0x20];
2819 
2820 	u8         a_frames_transmitted_ok_low[0x20];
2821 
2822 	u8         a_frames_received_ok_high[0x20];
2823 
2824 	u8         a_frames_received_ok_low[0x20];
2825 
2826 	u8         a_frame_check_sequence_errors_high[0x20];
2827 
2828 	u8         a_frame_check_sequence_errors_low[0x20];
2829 
2830 	u8         a_alignment_errors_high[0x20];
2831 
2832 	u8         a_alignment_errors_low[0x20];
2833 
2834 	u8         a_octets_transmitted_ok_high[0x20];
2835 
2836 	u8         a_octets_transmitted_ok_low[0x20];
2837 
2838 	u8         a_octets_received_ok_high[0x20];
2839 
2840 	u8         a_octets_received_ok_low[0x20];
2841 
2842 	u8         a_multicast_frames_xmitted_ok_high[0x20];
2843 
2844 	u8         a_multicast_frames_xmitted_ok_low[0x20];
2845 
2846 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
2847 
2848 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
2849 
2850 	u8         a_multicast_frames_received_ok_high[0x20];
2851 
2852 	u8         a_multicast_frames_received_ok_low[0x20];
2853 
2854 	u8         a_broadcast_frames_received_ok_high[0x20];
2855 
2856 	u8         a_broadcast_frames_received_ok_low[0x20];
2857 
2858 	u8         a_in_range_length_errors_high[0x20];
2859 
2860 	u8         a_in_range_length_errors_low[0x20];
2861 
2862 	u8         a_out_of_range_length_field_high[0x20];
2863 
2864 	u8         a_out_of_range_length_field_low[0x20];
2865 
2866 	u8         a_frame_too_long_errors_high[0x20];
2867 
2868 	u8         a_frame_too_long_errors_low[0x20];
2869 
2870 	u8         a_symbol_error_during_carrier_high[0x20];
2871 
2872 	u8         a_symbol_error_during_carrier_low[0x20];
2873 
2874 	u8         a_mac_control_frames_transmitted_high[0x20];
2875 
2876 	u8         a_mac_control_frames_transmitted_low[0x20];
2877 
2878 	u8         a_mac_control_frames_received_high[0x20];
2879 
2880 	u8         a_mac_control_frames_received_low[0x20];
2881 
2882 	u8         a_unsupported_opcodes_received_high[0x20];
2883 
2884 	u8         a_unsupported_opcodes_received_low[0x20];
2885 
2886 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
2887 
2888 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
2889 
2890 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2891 
2892 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2893 
2894 	u8         reserved_at_4c0[0x300];
2895 };
2896 
2897 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2898 	u8         life_time_counter_high[0x20];
2899 
2900 	u8         life_time_counter_low[0x20];
2901 
2902 	u8         rx_errors[0x20];
2903 
2904 	u8         tx_errors[0x20];
2905 
2906 	u8         l0_to_recovery_eieos[0x20];
2907 
2908 	u8         l0_to_recovery_ts[0x20];
2909 
2910 	u8         l0_to_recovery_framing[0x20];
2911 
2912 	u8         l0_to_recovery_retrain[0x20];
2913 
2914 	u8         crc_error_dllp[0x20];
2915 
2916 	u8         crc_error_tlp[0x20];
2917 
2918 	u8         tx_overflow_buffer_pkt_high[0x20];
2919 
2920 	u8         tx_overflow_buffer_pkt_low[0x20];
2921 
2922 	u8         outbound_stalled_reads[0x20];
2923 
2924 	u8         outbound_stalled_writes[0x20];
2925 
2926 	u8         outbound_stalled_reads_events[0x20];
2927 
2928 	u8         outbound_stalled_writes_events[0x20];
2929 
2930 	u8         reserved_at_200[0x5c0];
2931 };
2932 
2933 struct mlx5_ifc_cmd_inter_comp_event_bits {
2934 	u8         command_completion_vector[0x20];
2935 
2936 	u8         reserved_at_20[0xc0];
2937 };
2938 
2939 struct mlx5_ifc_stall_vl_event_bits {
2940 	u8         reserved_at_0[0x18];
2941 	u8         port_num[0x1];
2942 	u8         reserved_at_19[0x3];
2943 	u8         vl[0x4];
2944 
2945 	u8         reserved_at_20[0xa0];
2946 };
2947 
2948 struct mlx5_ifc_db_bf_congestion_event_bits {
2949 	u8         event_subtype[0x8];
2950 	u8         reserved_at_8[0x8];
2951 	u8         congestion_level[0x8];
2952 	u8         reserved_at_18[0x8];
2953 
2954 	u8         reserved_at_20[0xa0];
2955 };
2956 
2957 struct mlx5_ifc_gpio_event_bits {
2958 	u8         reserved_at_0[0x60];
2959 
2960 	u8         gpio_event_hi[0x20];
2961 
2962 	u8         gpio_event_lo[0x20];
2963 
2964 	u8         reserved_at_a0[0x40];
2965 };
2966 
2967 struct mlx5_ifc_port_state_change_event_bits {
2968 	u8         reserved_at_0[0x40];
2969 
2970 	u8         port_num[0x4];
2971 	u8         reserved_at_44[0x1c];
2972 
2973 	u8         reserved_at_60[0x80];
2974 };
2975 
2976 struct mlx5_ifc_dropped_packet_logged_bits {
2977 	u8         reserved_at_0[0xe0];
2978 };
2979 
2980 struct mlx5_ifc_default_timeout_bits {
2981 	u8         to_multiplier[0x3];
2982 	u8         reserved_at_3[0x9];
2983 	u8         to_value[0x14];
2984 };
2985 
2986 struct mlx5_ifc_dtor_reg_bits {
2987 	u8         reserved_at_0[0x20];
2988 
2989 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
2990 
2991 	u8         reserved_at_40[0x60];
2992 
2993 	struct mlx5_ifc_default_timeout_bits health_poll_to;
2994 
2995 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
2996 
2997 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
2998 
2999 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3000 
3001 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3002 
3003 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3004 
3005 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3006 
3007 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3008 
3009 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3010 
3011 	u8         reserved_at_1c0[0x40];
3012 };
3013 
3014 enum {
3015 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3016 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3017 };
3018 
3019 struct mlx5_ifc_cq_error_bits {
3020 	u8         reserved_at_0[0x8];
3021 	u8         cqn[0x18];
3022 
3023 	u8         reserved_at_20[0x20];
3024 
3025 	u8         reserved_at_40[0x18];
3026 	u8         syndrome[0x8];
3027 
3028 	u8         reserved_at_60[0x80];
3029 };
3030 
3031 struct mlx5_ifc_rdma_page_fault_event_bits {
3032 	u8         bytes_committed[0x20];
3033 
3034 	u8         r_key[0x20];
3035 
3036 	u8         reserved_at_40[0x10];
3037 	u8         packet_len[0x10];
3038 
3039 	u8         rdma_op_len[0x20];
3040 
3041 	u8         rdma_va[0x40];
3042 
3043 	u8         reserved_at_c0[0x5];
3044 	u8         rdma[0x1];
3045 	u8         write[0x1];
3046 	u8         requestor[0x1];
3047 	u8         qp_number[0x18];
3048 };
3049 
3050 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3051 	u8         bytes_committed[0x20];
3052 
3053 	u8         reserved_at_20[0x10];
3054 	u8         wqe_index[0x10];
3055 
3056 	u8         reserved_at_40[0x10];
3057 	u8         len[0x10];
3058 
3059 	u8         reserved_at_60[0x60];
3060 
3061 	u8         reserved_at_c0[0x5];
3062 	u8         rdma[0x1];
3063 	u8         write_read[0x1];
3064 	u8         requestor[0x1];
3065 	u8         qpn[0x18];
3066 };
3067 
3068 struct mlx5_ifc_qp_events_bits {
3069 	u8         reserved_at_0[0xa0];
3070 
3071 	u8         type[0x8];
3072 	u8         reserved_at_a8[0x18];
3073 
3074 	u8         reserved_at_c0[0x8];
3075 	u8         qpn_rqn_sqn[0x18];
3076 };
3077 
3078 struct mlx5_ifc_dct_events_bits {
3079 	u8         reserved_at_0[0xc0];
3080 
3081 	u8         reserved_at_c0[0x8];
3082 	u8         dct_number[0x18];
3083 };
3084 
3085 struct mlx5_ifc_comp_event_bits {
3086 	u8         reserved_at_0[0xc0];
3087 
3088 	u8         reserved_at_c0[0x8];
3089 	u8         cq_number[0x18];
3090 };
3091 
3092 enum {
3093 	MLX5_QPC_STATE_RST        = 0x0,
3094 	MLX5_QPC_STATE_INIT       = 0x1,
3095 	MLX5_QPC_STATE_RTR        = 0x2,
3096 	MLX5_QPC_STATE_RTS        = 0x3,
3097 	MLX5_QPC_STATE_SQER       = 0x4,
3098 	MLX5_QPC_STATE_ERR        = 0x6,
3099 	MLX5_QPC_STATE_SQD        = 0x7,
3100 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3101 };
3102 
3103 enum {
3104 	MLX5_QPC_ST_RC            = 0x0,
3105 	MLX5_QPC_ST_UC            = 0x1,
3106 	MLX5_QPC_ST_UD            = 0x2,
3107 	MLX5_QPC_ST_XRC           = 0x3,
3108 	MLX5_QPC_ST_DCI           = 0x5,
3109 	MLX5_QPC_ST_QP0           = 0x7,
3110 	MLX5_QPC_ST_QP1           = 0x8,
3111 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3112 	MLX5_QPC_ST_REG_UMR       = 0xc,
3113 };
3114 
3115 enum {
3116 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3117 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3118 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3119 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3120 };
3121 
3122 enum {
3123 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3124 };
3125 
3126 enum {
3127 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3128 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3129 };
3130 
3131 enum {
3132 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3133 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3134 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3135 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3136 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3137 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3138 };
3139 
3140 enum {
3141 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3142 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3143 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3144 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3145 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3146 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3147 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3148 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3149 };
3150 
3151 enum {
3152 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3153 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3154 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3155 };
3156 
3157 enum {
3158 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3159 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3160 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3161 };
3162 
3163 enum {
3164 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3165 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3166 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3167 };
3168 
3169 struct mlx5_ifc_qpc_bits {
3170 	u8         state[0x4];
3171 	u8         lag_tx_port_affinity[0x4];
3172 	u8         st[0x8];
3173 	u8         reserved_at_10[0x2];
3174 	u8	   isolate_vl_tc[0x1];
3175 	u8         pm_state[0x2];
3176 	u8         reserved_at_15[0x1];
3177 	u8         req_e2e_credit_mode[0x2];
3178 	u8         offload_type[0x4];
3179 	u8         end_padding_mode[0x2];
3180 	u8         reserved_at_1e[0x2];
3181 
3182 	u8         wq_signature[0x1];
3183 	u8         block_lb_mc[0x1];
3184 	u8         atomic_like_write_en[0x1];
3185 	u8         latency_sensitive[0x1];
3186 	u8         reserved_at_24[0x1];
3187 	u8         drain_sigerr[0x1];
3188 	u8         reserved_at_26[0x2];
3189 	u8         pd[0x18];
3190 
3191 	u8         mtu[0x3];
3192 	u8         log_msg_max[0x5];
3193 	u8         reserved_at_48[0x1];
3194 	u8         log_rq_size[0x4];
3195 	u8         log_rq_stride[0x3];
3196 	u8         no_sq[0x1];
3197 	u8         log_sq_size[0x4];
3198 	u8         reserved_at_55[0x3];
3199 	u8	   ts_format[0x2];
3200 	u8         reserved_at_5a[0x1];
3201 	u8         rlky[0x1];
3202 	u8         ulp_stateless_offload_mode[0x4];
3203 
3204 	u8         counter_set_id[0x8];
3205 	u8         uar_page[0x18];
3206 
3207 	u8         reserved_at_80[0x8];
3208 	u8         user_index[0x18];
3209 
3210 	u8         reserved_at_a0[0x3];
3211 	u8         log_page_size[0x5];
3212 	u8         remote_qpn[0x18];
3213 
3214 	struct mlx5_ifc_ads_bits primary_address_path;
3215 
3216 	struct mlx5_ifc_ads_bits secondary_address_path;
3217 
3218 	u8         log_ack_req_freq[0x4];
3219 	u8         reserved_at_384[0x4];
3220 	u8         log_sra_max[0x3];
3221 	u8         reserved_at_38b[0x2];
3222 	u8         retry_count[0x3];
3223 	u8         rnr_retry[0x3];
3224 	u8         reserved_at_393[0x1];
3225 	u8         fre[0x1];
3226 	u8         cur_rnr_retry[0x3];
3227 	u8         cur_retry_count[0x3];
3228 	u8         reserved_at_39b[0x5];
3229 
3230 	u8         reserved_at_3a0[0x20];
3231 
3232 	u8         reserved_at_3c0[0x8];
3233 	u8         next_send_psn[0x18];
3234 
3235 	u8         reserved_at_3e0[0x3];
3236 	u8	   log_num_dci_stream_channels[0x5];
3237 	u8         cqn_snd[0x18];
3238 
3239 	u8         reserved_at_400[0x3];
3240 	u8	   log_num_dci_errored_streams[0x5];
3241 	u8         deth_sqpn[0x18];
3242 
3243 	u8         reserved_at_420[0x20];
3244 
3245 	u8         reserved_at_440[0x8];
3246 	u8         last_acked_psn[0x18];
3247 
3248 	u8         reserved_at_460[0x8];
3249 	u8         ssn[0x18];
3250 
3251 	u8         reserved_at_480[0x8];
3252 	u8         log_rra_max[0x3];
3253 	u8         reserved_at_48b[0x1];
3254 	u8         atomic_mode[0x4];
3255 	u8         rre[0x1];
3256 	u8         rwe[0x1];
3257 	u8         rae[0x1];
3258 	u8         reserved_at_493[0x1];
3259 	u8         page_offset[0x6];
3260 	u8         reserved_at_49a[0x3];
3261 	u8         cd_slave_receive[0x1];
3262 	u8         cd_slave_send[0x1];
3263 	u8         cd_master[0x1];
3264 
3265 	u8         reserved_at_4a0[0x3];
3266 	u8         min_rnr_nak[0x5];
3267 	u8         next_rcv_psn[0x18];
3268 
3269 	u8         reserved_at_4c0[0x8];
3270 	u8         xrcd[0x18];
3271 
3272 	u8         reserved_at_4e0[0x8];
3273 	u8         cqn_rcv[0x18];
3274 
3275 	u8         dbr_addr[0x40];
3276 
3277 	u8         q_key[0x20];
3278 
3279 	u8         reserved_at_560[0x5];
3280 	u8         rq_type[0x3];
3281 	u8         srqn_rmpn_xrqn[0x18];
3282 
3283 	u8         reserved_at_580[0x8];
3284 	u8         rmsn[0x18];
3285 
3286 	u8         hw_sq_wqebb_counter[0x10];
3287 	u8         sw_sq_wqebb_counter[0x10];
3288 
3289 	u8         hw_rq_counter[0x20];
3290 
3291 	u8         sw_rq_counter[0x20];
3292 
3293 	u8         reserved_at_600[0x20];
3294 
3295 	u8         reserved_at_620[0xf];
3296 	u8         cgs[0x1];
3297 	u8         cs_req[0x8];
3298 	u8         cs_res[0x8];
3299 
3300 	u8         dc_access_key[0x40];
3301 
3302 	u8         reserved_at_680[0x3];
3303 	u8         dbr_umem_valid[0x1];
3304 
3305 	u8         reserved_at_684[0xbc];
3306 };
3307 
3308 struct mlx5_ifc_roce_addr_layout_bits {
3309 	u8         source_l3_address[16][0x8];
3310 
3311 	u8         reserved_at_80[0x3];
3312 	u8         vlan_valid[0x1];
3313 	u8         vlan_id[0xc];
3314 	u8         source_mac_47_32[0x10];
3315 
3316 	u8         source_mac_31_0[0x20];
3317 
3318 	u8         reserved_at_c0[0x14];
3319 	u8         roce_l3_type[0x4];
3320 	u8         roce_version[0x8];
3321 
3322 	u8         reserved_at_e0[0x20];
3323 };
3324 
3325 struct mlx5_ifc_shampo_cap_bits {
3326 	u8    reserved_at_0[0x3];
3327 	u8    shampo_log_max_reservation_size[0x5];
3328 	u8    reserved_at_8[0x3];
3329 	u8    shampo_log_min_reservation_size[0x5];
3330 	u8    shampo_min_mss_size[0x10];
3331 
3332 	u8    reserved_at_20[0x3];
3333 	u8    shampo_max_log_headers_entry_size[0x5];
3334 	u8    reserved_at_28[0x18];
3335 
3336 	u8    reserved_at_40[0x7c0];
3337 };
3338 
3339 union mlx5_ifc_hca_cap_union_bits {
3340 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3341 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3342 	struct mlx5_ifc_odp_cap_bits odp_cap;
3343 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3344 	struct mlx5_ifc_roce_cap_bits roce_cap;
3345 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3346 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3347 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3348 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3349 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3350 	struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
3351 	struct mlx5_ifc_qos_cap_bits qos_cap;
3352 	struct mlx5_ifc_debug_cap_bits debug_cap;
3353 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3354 	struct mlx5_ifc_tls_cap_bits tls_cap;
3355 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3356 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3357 	struct mlx5_ifc_shampo_cap_bits shampo_cap;
3358 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3359 	u8         reserved_at_0[0x8000];
3360 };
3361 
3362 enum {
3363 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3364 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3365 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3366 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3367 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3368 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3369 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3370 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3371 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3372 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3373 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3374 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3375 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3376 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3377 };
3378 
3379 enum {
3380 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3381 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3382 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3383 };
3384 
3385 enum {
3386 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3387 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3388 };
3389 
3390 struct mlx5_ifc_vlan_bits {
3391 	u8         ethtype[0x10];
3392 	u8         prio[0x3];
3393 	u8         cfi[0x1];
3394 	u8         vid[0xc];
3395 };
3396 
3397 enum {
3398 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3399 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3400 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3401 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3402 };
3403 
3404 enum {
3405 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3406 };
3407 
3408 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3409 	u8        return_reg_id[0x4];
3410 	u8        aso_type[0x4];
3411 	u8        reserved_at_8[0x14];
3412 	u8        action[0x1];
3413 	u8        init_color[0x2];
3414 	u8        meter_id[0x1];
3415 };
3416 
3417 union mlx5_ifc_exe_aso_ctrl {
3418 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3419 };
3420 
3421 struct mlx5_ifc_execute_aso_bits {
3422 	u8        valid[0x1];
3423 	u8        reserved_at_1[0x7];
3424 	u8        aso_object_id[0x18];
3425 
3426 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3427 };
3428 
3429 struct mlx5_ifc_flow_context_bits {
3430 	struct mlx5_ifc_vlan_bits push_vlan;
3431 
3432 	u8         group_id[0x20];
3433 
3434 	u8         reserved_at_40[0x8];
3435 	u8         flow_tag[0x18];
3436 
3437 	u8         reserved_at_60[0x10];
3438 	u8         action[0x10];
3439 
3440 	u8         extended_destination[0x1];
3441 	u8         reserved_at_81[0x1];
3442 	u8         flow_source[0x2];
3443 	u8         encrypt_decrypt_type[0x4];
3444 	u8         destination_list_size[0x18];
3445 
3446 	u8         reserved_at_a0[0x8];
3447 	u8         flow_counter_list_size[0x18];
3448 
3449 	u8         packet_reformat_id[0x20];
3450 
3451 	u8         modify_header_id[0x20];
3452 
3453 	struct mlx5_ifc_vlan_bits push_vlan_2;
3454 
3455 	u8         encrypt_decrypt_obj_id[0x20];
3456 	u8         reserved_at_140[0xc0];
3457 
3458 	struct mlx5_ifc_fte_match_param_bits match_value;
3459 
3460 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3461 
3462 	u8         reserved_at_1300[0x500];
3463 
3464 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3465 };
3466 
3467 enum {
3468 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3469 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3470 };
3471 
3472 struct mlx5_ifc_xrc_srqc_bits {
3473 	u8         state[0x4];
3474 	u8         log_xrc_srq_size[0x4];
3475 	u8         reserved_at_8[0x18];
3476 
3477 	u8         wq_signature[0x1];
3478 	u8         cont_srq[0x1];
3479 	u8         reserved_at_22[0x1];
3480 	u8         rlky[0x1];
3481 	u8         basic_cyclic_rcv_wqe[0x1];
3482 	u8         log_rq_stride[0x3];
3483 	u8         xrcd[0x18];
3484 
3485 	u8         page_offset[0x6];
3486 	u8         reserved_at_46[0x1];
3487 	u8         dbr_umem_valid[0x1];
3488 	u8         cqn[0x18];
3489 
3490 	u8         reserved_at_60[0x20];
3491 
3492 	u8         user_index_equal_xrc_srqn[0x1];
3493 	u8         reserved_at_81[0x1];
3494 	u8         log_page_size[0x6];
3495 	u8         user_index[0x18];
3496 
3497 	u8         reserved_at_a0[0x20];
3498 
3499 	u8         reserved_at_c0[0x8];
3500 	u8         pd[0x18];
3501 
3502 	u8         lwm[0x10];
3503 	u8         wqe_cnt[0x10];
3504 
3505 	u8         reserved_at_100[0x40];
3506 
3507 	u8         db_record_addr_h[0x20];
3508 
3509 	u8         db_record_addr_l[0x1e];
3510 	u8         reserved_at_17e[0x2];
3511 
3512 	u8         reserved_at_180[0x80];
3513 };
3514 
3515 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3516 	u8         counter_error_queues[0x20];
3517 
3518 	u8         total_error_queues[0x20];
3519 
3520 	u8         send_queue_priority_update_flow[0x20];
3521 
3522 	u8         reserved_at_60[0x20];
3523 
3524 	u8         nic_receive_steering_discard[0x40];
3525 
3526 	u8         receive_discard_vport_down[0x40];
3527 
3528 	u8         transmit_discard_vport_down[0x40];
3529 
3530 	u8         async_eq_overrun[0x20];
3531 
3532 	u8         comp_eq_overrun[0x20];
3533 
3534 	u8         reserved_at_180[0x20];
3535 
3536 	u8         invalid_command[0x20];
3537 
3538 	u8         quota_exceeded_command[0x20];
3539 
3540 	u8         internal_rq_out_of_buffer[0x20];
3541 
3542 	u8         cq_overrun[0x20];
3543 
3544 	u8         eth_wqe_too_small[0x20];
3545 
3546 	u8         reserved_at_220[0xdc0];
3547 };
3548 
3549 struct mlx5_ifc_traffic_counter_bits {
3550 	u8         packets[0x40];
3551 
3552 	u8         octets[0x40];
3553 };
3554 
3555 struct mlx5_ifc_tisc_bits {
3556 	u8         strict_lag_tx_port_affinity[0x1];
3557 	u8         tls_en[0x1];
3558 	u8         reserved_at_2[0x2];
3559 	u8         lag_tx_port_affinity[0x04];
3560 
3561 	u8         reserved_at_8[0x4];
3562 	u8         prio[0x4];
3563 	u8         reserved_at_10[0x10];
3564 
3565 	u8         reserved_at_20[0x100];
3566 
3567 	u8         reserved_at_120[0x8];
3568 	u8         transport_domain[0x18];
3569 
3570 	u8         reserved_at_140[0x8];
3571 	u8         underlay_qpn[0x18];
3572 
3573 	u8         reserved_at_160[0x8];
3574 	u8         pd[0x18];
3575 
3576 	u8         reserved_at_180[0x380];
3577 };
3578 
3579 enum {
3580 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3581 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3582 };
3583 
3584 enum {
3585 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3586 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3587 };
3588 
3589 enum {
3590 	MLX5_RX_HASH_FN_NONE           = 0x0,
3591 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3592 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3593 };
3594 
3595 enum {
3596 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3597 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3598 };
3599 
3600 struct mlx5_ifc_tirc_bits {
3601 	u8         reserved_at_0[0x20];
3602 
3603 	u8         disp_type[0x4];
3604 	u8         tls_en[0x1];
3605 	u8         reserved_at_25[0x1b];
3606 
3607 	u8         reserved_at_40[0x40];
3608 
3609 	u8         reserved_at_80[0x4];
3610 	u8         lro_timeout_period_usecs[0x10];
3611 	u8         packet_merge_mask[0x4];
3612 	u8         lro_max_ip_payload_size[0x8];
3613 
3614 	u8         reserved_at_a0[0x40];
3615 
3616 	u8         reserved_at_e0[0x8];
3617 	u8         inline_rqn[0x18];
3618 
3619 	u8         rx_hash_symmetric[0x1];
3620 	u8         reserved_at_101[0x1];
3621 	u8         tunneled_offload_en[0x1];
3622 	u8         reserved_at_103[0x5];
3623 	u8         indirect_table[0x18];
3624 
3625 	u8         rx_hash_fn[0x4];
3626 	u8         reserved_at_124[0x2];
3627 	u8         self_lb_block[0x2];
3628 	u8         transport_domain[0x18];
3629 
3630 	u8         rx_hash_toeplitz_key[10][0x20];
3631 
3632 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3633 
3634 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3635 
3636 	u8         reserved_at_2c0[0x4c0];
3637 };
3638 
3639 enum {
3640 	MLX5_SRQC_STATE_GOOD   = 0x0,
3641 	MLX5_SRQC_STATE_ERROR  = 0x1,
3642 };
3643 
3644 struct mlx5_ifc_srqc_bits {
3645 	u8         state[0x4];
3646 	u8         log_srq_size[0x4];
3647 	u8         reserved_at_8[0x18];
3648 
3649 	u8         wq_signature[0x1];
3650 	u8         cont_srq[0x1];
3651 	u8         reserved_at_22[0x1];
3652 	u8         rlky[0x1];
3653 	u8         reserved_at_24[0x1];
3654 	u8         log_rq_stride[0x3];
3655 	u8         xrcd[0x18];
3656 
3657 	u8         page_offset[0x6];
3658 	u8         reserved_at_46[0x2];
3659 	u8         cqn[0x18];
3660 
3661 	u8         reserved_at_60[0x20];
3662 
3663 	u8         reserved_at_80[0x2];
3664 	u8         log_page_size[0x6];
3665 	u8         reserved_at_88[0x18];
3666 
3667 	u8         reserved_at_a0[0x20];
3668 
3669 	u8         reserved_at_c0[0x8];
3670 	u8         pd[0x18];
3671 
3672 	u8         lwm[0x10];
3673 	u8         wqe_cnt[0x10];
3674 
3675 	u8         reserved_at_100[0x40];
3676 
3677 	u8         dbr_addr[0x40];
3678 
3679 	u8         reserved_at_180[0x80];
3680 };
3681 
3682 enum {
3683 	MLX5_SQC_STATE_RST  = 0x0,
3684 	MLX5_SQC_STATE_RDY  = 0x1,
3685 	MLX5_SQC_STATE_ERR  = 0x3,
3686 };
3687 
3688 struct mlx5_ifc_sqc_bits {
3689 	u8         rlky[0x1];
3690 	u8         cd_master[0x1];
3691 	u8         fre[0x1];
3692 	u8         flush_in_error_en[0x1];
3693 	u8         allow_multi_pkt_send_wqe[0x1];
3694 	u8	   min_wqe_inline_mode[0x3];
3695 	u8         state[0x4];
3696 	u8         reg_umr[0x1];
3697 	u8         allow_swp[0x1];
3698 	u8         hairpin[0x1];
3699 	u8         reserved_at_f[0xb];
3700 	u8	   ts_format[0x2];
3701 	u8	   reserved_at_1c[0x4];
3702 
3703 	u8         reserved_at_20[0x8];
3704 	u8         user_index[0x18];
3705 
3706 	u8         reserved_at_40[0x8];
3707 	u8         cqn[0x18];
3708 
3709 	u8         reserved_at_60[0x8];
3710 	u8         hairpin_peer_rq[0x18];
3711 
3712 	u8         reserved_at_80[0x10];
3713 	u8         hairpin_peer_vhca[0x10];
3714 
3715 	u8         reserved_at_a0[0x20];
3716 
3717 	u8         reserved_at_c0[0x8];
3718 	u8         ts_cqe_to_dest_cqn[0x18];
3719 
3720 	u8         reserved_at_e0[0x10];
3721 	u8         packet_pacing_rate_limit_index[0x10];
3722 	u8         tis_lst_sz[0x10];
3723 	u8         qos_queue_group_id[0x10];
3724 
3725 	u8         reserved_at_120[0x40];
3726 
3727 	u8         reserved_at_160[0x8];
3728 	u8         tis_num_0[0x18];
3729 
3730 	struct mlx5_ifc_wq_bits wq;
3731 };
3732 
3733 enum {
3734 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3735 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3736 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3737 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3738 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3739 };
3740 
3741 enum {
3742 	ELEMENT_TYPE_CAP_MASK_TASR		= 1 << 0,
3743 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3744 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3745 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3746 };
3747 
3748 struct mlx5_ifc_scheduling_context_bits {
3749 	u8         element_type[0x8];
3750 	u8         reserved_at_8[0x18];
3751 
3752 	u8         element_attributes[0x20];
3753 
3754 	u8         parent_element_id[0x20];
3755 
3756 	u8         reserved_at_60[0x40];
3757 
3758 	u8         bw_share[0x20];
3759 
3760 	u8         max_average_bw[0x20];
3761 
3762 	u8         reserved_at_e0[0x120];
3763 };
3764 
3765 struct mlx5_ifc_rqtc_bits {
3766 	u8    reserved_at_0[0xa0];
3767 
3768 	u8    reserved_at_a0[0x5];
3769 	u8    list_q_type[0x3];
3770 	u8    reserved_at_a8[0x8];
3771 	u8    rqt_max_size[0x10];
3772 
3773 	u8    rq_vhca_id_format[0x1];
3774 	u8    reserved_at_c1[0xf];
3775 	u8    rqt_actual_size[0x10];
3776 
3777 	u8    reserved_at_e0[0x6a0];
3778 
3779 	struct mlx5_ifc_rq_num_bits rq_num[];
3780 };
3781 
3782 enum {
3783 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3784 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3785 };
3786 
3787 enum {
3788 	MLX5_RQC_STATE_RST  = 0x0,
3789 	MLX5_RQC_STATE_RDY  = 0x1,
3790 	MLX5_RQC_STATE_ERR  = 0x3,
3791 };
3792 
3793 enum {
3794 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3795 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3796 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3797 };
3798 
3799 enum {
3800 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3801 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3802 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3803 };
3804 
3805 struct mlx5_ifc_rqc_bits {
3806 	u8         rlky[0x1];
3807 	u8	   delay_drop_en[0x1];
3808 	u8         scatter_fcs[0x1];
3809 	u8         vsd[0x1];
3810 	u8         mem_rq_type[0x4];
3811 	u8         state[0x4];
3812 	u8         reserved_at_c[0x1];
3813 	u8         flush_in_error_en[0x1];
3814 	u8         hairpin[0x1];
3815 	u8         reserved_at_f[0xb];
3816 	u8	   ts_format[0x2];
3817 	u8	   reserved_at_1c[0x4];
3818 
3819 	u8         reserved_at_20[0x8];
3820 	u8         user_index[0x18];
3821 
3822 	u8         reserved_at_40[0x8];
3823 	u8         cqn[0x18];
3824 
3825 	u8         counter_set_id[0x8];
3826 	u8         reserved_at_68[0x18];
3827 
3828 	u8         reserved_at_80[0x8];
3829 	u8         rmpn[0x18];
3830 
3831 	u8         reserved_at_a0[0x8];
3832 	u8         hairpin_peer_sq[0x18];
3833 
3834 	u8         reserved_at_c0[0x10];
3835 	u8         hairpin_peer_vhca[0x10];
3836 
3837 	u8         reserved_at_e0[0x46];
3838 	u8         shampo_no_match_alignment_granularity[0x2];
3839 	u8         reserved_at_128[0x6];
3840 	u8         shampo_match_criteria_type[0x2];
3841 	u8         reservation_timeout[0x10];
3842 
3843 	u8         reserved_at_140[0x40];
3844 
3845 	struct mlx5_ifc_wq_bits wq;
3846 };
3847 
3848 enum {
3849 	MLX5_RMPC_STATE_RDY  = 0x1,
3850 	MLX5_RMPC_STATE_ERR  = 0x3,
3851 };
3852 
3853 struct mlx5_ifc_rmpc_bits {
3854 	u8         reserved_at_0[0x8];
3855 	u8         state[0x4];
3856 	u8         reserved_at_c[0x14];
3857 
3858 	u8         basic_cyclic_rcv_wqe[0x1];
3859 	u8         reserved_at_21[0x1f];
3860 
3861 	u8         reserved_at_40[0x140];
3862 
3863 	struct mlx5_ifc_wq_bits wq;
3864 };
3865 
3866 enum {
3867 	VHCA_ID_TYPE_HW = 0,
3868 	VHCA_ID_TYPE_SW = 1,
3869 };
3870 
3871 struct mlx5_ifc_nic_vport_context_bits {
3872 	u8         reserved_at_0[0x5];
3873 	u8         min_wqe_inline_mode[0x3];
3874 	u8         reserved_at_8[0x15];
3875 	u8         disable_mc_local_lb[0x1];
3876 	u8         disable_uc_local_lb[0x1];
3877 	u8         roce_en[0x1];
3878 
3879 	u8         arm_change_event[0x1];
3880 	u8         reserved_at_21[0x1a];
3881 	u8         event_on_mtu[0x1];
3882 	u8         event_on_promisc_change[0x1];
3883 	u8         event_on_vlan_change[0x1];
3884 	u8         event_on_mc_address_change[0x1];
3885 	u8         event_on_uc_address_change[0x1];
3886 
3887 	u8         vhca_id_type[0x1];
3888 	u8         reserved_at_41[0xb];
3889 	u8	   affiliation_criteria[0x4];
3890 	u8	   affiliated_vhca_id[0x10];
3891 
3892 	u8	   reserved_at_60[0xd0];
3893 
3894 	u8         mtu[0x10];
3895 
3896 	u8         system_image_guid[0x40];
3897 	u8         port_guid[0x40];
3898 	u8         node_guid[0x40];
3899 
3900 	u8         reserved_at_200[0x140];
3901 	u8         qkey_violation_counter[0x10];
3902 	u8         reserved_at_350[0x430];
3903 
3904 	u8         promisc_uc[0x1];
3905 	u8         promisc_mc[0x1];
3906 	u8         promisc_all[0x1];
3907 	u8         reserved_at_783[0x2];
3908 	u8         allowed_list_type[0x3];
3909 	u8         reserved_at_788[0xc];
3910 	u8         allowed_list_size[0xc];
3911 
3912 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
3913 
3914 	u8         reserved_at_7e0[0x20];
3915 
3916 	u8         current_uc_mac_address[][0x40];
3917 };
3918 
3919 enum {
3920 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3921 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3922 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3923 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3924 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3925 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3926 };
3927 
3928 struct mlx5_ifc_mkc_bits {
3929 	u8         reserved_at_0[0x1];
3930 	u8         free[0x1];
3931 	u8         reserved_at_2[0x1];
3932 	u8         access_mode_4_2[0x3];
3933 	u8         reserved_at_6[0x7];
3934 	u8         relaxed_ordering_write[0x1];
3935 	u8         reserved_at_e[0x1];
3936 	u8         small_fence_on_rdma_read_response[0x1];
3937 	u8         umr_en[0x1];
3938 	u8         a[0x1];
3939 	u8         rw[0x1];
3940 	u8         rr[0x1];
3941 	u8         lw[0x1];
3942 	u8         lr[0x1];
3943 	u8         access_mode_1_0[0x2];
3944 	u8         reserved_at_18[0x2];
3945 	u8         ma_translation_mode[0x2];
3946 	u8         reserved_at_1c[0x4];
3947 
3948 	u8         qpn[0x18];
3949 	u8         mkey_7_0[0x8];
3950 
3951 	u8         reserved_at_40[0x20];
3952 
3953 	u8         length64[0x1];
3954 	u8         bsf_en[0x1];
3955 	u8         sync_umr[0x1];
3956 	u8         reserved_at_63[0x2];
3957 	u8         expected_sigerr_count[0x1];
3958 	u8         reserved_at_66[0x1];
3959 	u8         en_rinval[0x1];
3960 	u8         pd[0x18];
3961 
3962 	u8         start_addr[0x40];
3963 
3964 	u8         len[0x40];
3965 
3966 	u8         bsf_octword_size[0x20];
3967 
3968 	u8         reserved_at_120[0x80];
3969 
3970 	u8         translations_octword_size[0x20];
3971 
3972 	u8         reserved_at_1c0[0x19];
3973 	u8         relaxed_ordering_read[0x1];
3974 	u8         reserved_at_1d9[0x1];
3975 	u8         log_page_size[0x5];
3976 
3977 	u8         reserved_at_1e0[0x20];
3978 };
3979 
3980 struct mlx5_ifc_pkey_bits {
3981 	u8         reserved_at_0[0x10];
3982 	u8         pkey[0x10];
3983 };
3984 
3985 struct mlx5_ifc_array128_auto_bits {
3986 	u8         array128_auto[16][0x8];
3987 };
3988 
3989 struct mlx5_ifc_hca_vport_context_bits {
3990 	u8         field_select[0x20];
3991 
3992 	u8         reserved_at_20[0xe0];
3993 
3994 	u8         sm_virt_aware[0x1];
3995 	u8         has_smi[0x1];
3996 	u8         has_raw[0x1];
3997 	u8         grh_required[0x1];
3998 	u8         reserved_at_104[0xc];
3999 	u8         port_physical_state[0x4];
4000 	u8         vport_state_policy[0x4];
4001 	u8         port_state[0x4];
4002 	u8         vport_state[0x4];
4003 
4004 	u8         reserved_at_120[0x20];
4005 
4006 	u8         system_image_guid[0x40];
4007 
4008 	u8         port_guid[0x40];
4009 
4010 	u8         node_guid[0x40];
4011 
4012 	u8         cap_mask1[0x20];
4013 
4014 	u8         cap_mask1_field_select[0x20];
4015 
4016 	u8         cap_mask2[0x20];
4017 
4018 	u8         cap_mask2_field_select[0x20];
4019 
4020 	u8         reserved_at_280[0x80];
4021 
4022 	u8         lid[0x10];
4023 	u8         reserved_at_310[0x4];
4024 	u8         init_type_reply[0x4];
4025 	u8         lmc[0x3];
4026 	u8         subnet_timeout[0x5];
4027 
4028 	u8         sm_lid[0x10];
4029 	u8         sm_sl[0x4];
4030 	u8         reserved_at_334[0xc];
4031 
4032 	u8         qkey_violation_counter[0x10];
4033 	u8         pkey_violation_counter[0x10];
4034 
4035 	u8         reserved_at_360[0xca0];
4036 };
4037 
4038 struct mlx5_ifc_esw_vport_context_bits {
4039 	u8         fdb_to_vport_reg_c[0x1];
4040 	u8         reserved_at_1[0x2];
4041 	u8         vport_svlan_strip[0x1];
4042 	u8         vport_cvlan_strip[0x1];
4043 	u8         vport_svlan_insert[0x1];
4044 	u8         vport_cvlan_insert[0x2];
4045 	u8         fdb_to_vport_reg_c_id[0x8];
4046 	u8         reserved_at_10[0x10];
4047 
4048 	u8         reserved_at_20[0x20];
4049 
4050 	u8         svlan_cfi[0x1];
4051 	u8         svlan_pcp[0x3];
4052 	u8         svlan_id[0xc];
4053 	u8         cvlan_cfi[0x1];
4054 	u8         cvlan_pcp[0x3];
4055 	u8         cvlan_id[0xc];
4056 
4057 	u8         reserved_at_60[0x720];
4058 
4059 	u8         sw_steering_vport_icm_address_rx[0x40];
4060 
4061 	u8         sw_steering_vport_icm_address_tx[0x40];
4062 };
4063 
4064 enum {
4065 	MLX5_EQC_STATUS_OK                = 0x0,
4066 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4067 };
4068 
4069 enum {
4070 	MLX5_EQC_ST_ARMED  = 0x9,
4071 	MLX5_EQC_ST_FIRED  = 0xa,
4072 };
4073 
4074 struct mlx5_ifc_eqc_bits {
4075 	u8         status[0x4];
4076 	u8         reserved_at_4[0x9];
4077 	u8         ec[0x1];
4078 	u8         oi[0x1];
4079 	u8         reserved_at_f[0x5];
4080 	u8         st[0x4];
4081 	u8         reserved_at_18[0x8];
4082 
4083 	u8         reserved_at_20[0x20];
4084 
4085 	u8         reserved_at_40[0x14];
4086 	u8         page_offset[0x6];
4087 	u8         reserved_at_5a[0x6];
4088 
4089 	u8         reserved_at_60[0x3];
4090 	u8         log_eq_size[0x5];
4091 	u8         uar_page[0x18];
4092 
4093 	u8         reserved_at_80[0x20];
4094 
4095 	u8         reserved_at_a0[0x14];
4096 	u8         intr[0xc];
4097 
4098 	u8         reserved_at_c0[0x3];
4099 	u8         log_page_size[0x5];
4100 	u8         reserved_at_c8[0x18];
4101 
4102 	u8         reserved_at_e0[0x60];
4103 
4104 	u8         reserved_at_140[0x8];
4105 	u8         consumer_counter[0x18];
4106 
4107 	u8         reserved_at_160[0x8];
4108 	u8         producer_counter[0x18];
4109 
4110 	u8         reserved_at_180[0x80];
4111 };
4112 
4113 enum {
4114 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4115 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4116 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4117 };
4118 
4119 enum {
4120 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4121 	MLX5_DCTC_CS_RES_NA         = 0x1,
4122 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4123 };
4124 
4125 enum {
4126 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4127 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4128 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4129 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4130 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4131 };
4132 
4133 struct mlx5_ifc_dctc_bits {
4134 	u8         reserved_at_0[0x4];
4135 	u8         state[0x4];
4136 	u8         reserved_at_8[0x18];
4137 
4138 	u8         reserved_at_20[0x8];
4139 	u8         user_index[0x18];
4140 
4141 	u8         reserved_at_40[0x8];
4142 	u8         cqn[0x18];
4143 
4144 	u8         counter_set_id[0x8];
4145 	u8         atomic_mode[0x4];
4146 	u8         rre[0x1];
4147 	u8         rwe[0x1];
4148 	u8         rae[0x1];
4149 	u8         atomic_like_write_en[0x1];
4150 	u8         latency_sensitive[0x1];
4151 	u8         rlky[0x1];
4152 	u8         free_ar[0x1];
4153 	u8         reserved_at_73[0xd];
4154 
4155 	u8         reserved_at_80[0x8];
4156 	u8         cs_res[0x8];
4157 	u8         reserved_at_90[0x3];
4158 	u8         min_rnr_nak[0x5];
4159 	u8         reserved_at_98[0x8];
4160 
4161 	u8         reserved_at_a0[0x8];
4162 	u8         srqn_xrqn[0x18];
4163 
4164 	u8         reserved_at_c0[0x8];
4165 	u8         pd[0x18];
4166 
4167 	u8         tclass[0x8];
4168 	u8         reserved_at_e8[0x4];
4169 	u8         flow_label[0x14];
4170 
4171 	u8         dc_access_key[0x40];
4172 
4173 	u8         reserved_at_140[0x5];
4174 	u8         mtu[0x3];
4175 	u8         port[0x8];
4176 	u8         pkey_index[0x10];
4177 
4178 	u8         reserved_at_160[0x8];
4179 	u8         my_addr_index[0x8];
4180 	u8         reserved_at_170[0x8];
4181 	u8         hop_limit[0x8];
4182 
4183 	u8         dc_access_key_violation_count[0x20];
4184 
4185 	u8         reserved_at_1a0[0x14];
4186 	u8         dei_cfi[0x1];
4187 	u8         eth_prio[0x3];
4188 	u8         ecn[0x2];
4189 	u8         dscp[0x6];
4190 
4191 	u8         reserved_at_1c0[0x20];
4192 	u8         ece[0x20];
4193 };
4194 
4195 enum {
4196 	MLX5_CQC_STATUS_OK             = 0x0,
4197 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4198 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4199 };
4200 
4201 enum {
4202 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4203 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4204 };
4205 
4206 enum {
4207 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4208 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4209 	MLX5_CQC_ST_FIRED                                 = 0xa,
4210 };
4211 
4212 enum {
4213 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4214 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4215 	MLX5_CQ_PERIOD_NUM_MODES
4216 };
4217 
4218 struct mlx5_ifc_cqc_bits {
4219 	u8         status[0x4];
4220 	u8         reserved_at_4[0x2];
4221 	u8         dbr_umem_valid[0x1];
4222 	u8         apu_cq[0x1];
4223 	u8         cqe_sz[0x3];
4224 	u8         cc[0x1];
4225 	u8         reserved_at_c[0x1];
4226 	u8         scqe_break_moderation_en[0x1];
4227 	u8         oi[0x1];
4228 	u8         cq_period_mode[0x2];
4229 	u8         cqe_comp_en[0x1];
4230 	u8         mini_cqe_res_format[0x2];
4231 	u8         st[0x4];
4232 	u8         reserved_at_18[0x6];
4233 	u8         cqe_compression_layout[0x2];
4234 
4235 	u8         reserved_at_20[0x20];
4236 
4237 	u8         reserved_at_40[0x14];
4238 	u8         page_offset[0x6];
4239 	u8         reserved_at_5a[0x6];
4240 
4241 	u8         reserved_at_60[0x3];
4242 	u8         log_cq_size[0x5];
4243 	u8         uar_page[0x18];
4244 
4245 	u8         reserved_at_80[0x4];
4246 	u8         cq_period[0xc];
4247 	u8         cq_max_count[0x10];
4248 
4249 	u8         c_eqn_or_apu_element[0x20];
4250 
4251 	u8         reserved_at_c0[0x3];
4252 	u8         log_page_size[0x5];
4253 	u8         reserved_at_c8[0x18];
4254 
4255 	u8         reserved_at_e0[0x20];
4256 
4257 	u8         reserved_at_100[0x8];
4258 	u8         last_notified_index[0x18];
4259 
4260 	u8         reserved_at_120[0x8];
4261 	u8         last_solicit_index[0x18];
4262 
4263 	u8         reserved_at_140[0x8];
4264 	u8         consumer_counter[0x18];
4265 
4266 	u8         reserved_at_160[0x8];
4267 	u8         producer_counter[0x18];
4268 
4269 	u8         reserved_at_180[0x40];
4270 
4271 	u8         dbr_addr[0x40];
4272 };
4273 
4274 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4275 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4276 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4277 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4278 	u8         reserved_at_0[0x800];
4279 };
4280 
4281 struct mlx5_ifc_query_adapter_param_block_bits {
4282 	u8         reserved_at_0[0xc0];
4283 
4284 	u8         reserved_at_c0[0x8];
4285 	u8         ieee_vendor_id[0x18];
4286 
4287 	u8         reserved_at_e0[0x10];
4288 	u8         vsd_vendor_id[0x10];
4289 
4290 	u8         vsd[208][0x8];
4291 
4292 	u8         vsd_contd_psid[16][0x8];
4293 };
4294 
4295 enum {
4296 	MLX5_XRQC_STATE_GOOD   = 0x0,
4297 	MLX5_XRQC_STATE_ERROR  = 0x1,
4298 };
4299 
4300 enum {
4301 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4302 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4303 };
4304 
4305 enum {
4306 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4307 };
4308 
4309 struct mlx5_ifc_tag_matching_topology_context_bits {
4310 	u8         log_matching_list_sz[0x4];
4311 	u8         reserved_at_4[0xc];
4312 	u8         append_next_index[0x10];
4313 
4314 	u8         sw_phase_cnt[0x10];
4315 	u8         hw_phase_cnt[0x10];
4316 
4317 	u8         reserved_at_40[0x40];
4318 };
4319 
4320 struct mlx5_ifc_xrqc_bits {
4321 	u8         state[0x4];
4322 	u8         rlkey[0x1];
4323 	u8         reserved_at_5[0xf];
4324 	u8         topology[0x4];
4325 	u8         reserved_at_18[0x4];
4326 	u8         offload[0x4];
4327 
4328 	u8         reserved_at_20[0x8];
4329 	u8         user_index[0x18];
4330 
4331 	u8         reserved_at_40[0x8];
4332 	u8         cqn[0x18];
4333 
4334 	u8         reserved_at_60[0xa0];
4335 
4336 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4337 
4338 	u8         reserved_at_180[0x280];
4339 
4340 	struct mlx5_ifc_wq_bits wq;
4341 };
4342 
4343 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4344 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4345 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4346 	u8         reserved_at_0[0x20];
4347 };
4348 
4349 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4350 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4351 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4352 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4353 	u8         reserved_at_0[0x20];
4354 };
4355 
4356 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4357 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4358 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4359 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4360 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4361 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4362 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4363 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4364 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4365 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4366 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4367 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4368 	u8         reserved_at_0[0x7c0];
4369 };
4370 
4371 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4372 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4373 	u8         reserved_at_0[0x7c0];
4374 };
4375 
4376 union mlx5_ifc_event_auto_bits {
4377 	struct mlx5_ifc_comp_event_bits comp_event;
4378 	struct mlx5_ifc_dct_events_bits dct_events;
4379 	struct mlx5_ifc_qp_events_bits qp_events;
4380 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4381 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4382 	struct mlx5_ifc_cq_error_bits cq_error;
4383 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4384 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4385 	struct mlx5_ifc_gpio_event_bits gpio_event;
4386 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4387 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4388 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4389 	u8         reserved_at_0[0xe0];
4390 };
4391 
4392 struct mlx5_ifc_health_buffer_bits {
4393 	u8         reserved_at_0[0x100];
4394 
4395 	u8         assert_existptr[0x20];
4396 
4397 	u8         assert_callra[0x20];
4398 
4399 	u8         reserved_at_140[0x20];
4400 
4401 	u8         time[0x20];
4402 
4403 	u8         fw_version[0x20];
4404 
4405 	u8         hw_id[0x20];
4406 
4407 	u8         rfr[0x1];
4408 	u8         reserved_at_1c1[0x3];
4409 	u8         valid[0x1];
4410 	u8         severity[0x3];
4411 	u8         reserved_at_1c8[0x18];
4412 
4413 	u8         irisc_index[0x8];
4414 	u8         synd[0x8];
4415 	u8         ext_synd[0x10];
4416 };
4417 
4418 struct mlx5_ifc_register_loopback_control_bits {
4419 	u8         no_lb[0x1];
4420 	u8         reserved_at_1[0x7];
4421 	u8         port[0x8];
4422 	u8         reserved_at_10[0x10];
4423 
4424 	u8         reserved_at_20[0x60];
4425 };
4426 
4427 struct mlx5_ifc_vport_tc_element_bits {
4428 	u8         traffic_class[0x4];
4429 	u8         reserved_at_4[0xc];
4430 	u8         vport_number[0x10];
4431 };
4432 
4433 struct mlx5_ifc_vport_element_bits {
4434 	u8         reserved_at_0[0x10];
4435 	u8         vport_number[0x10];
4436 };
4437 
4438 enum {
4439 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4440 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4441 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4442 };
4443 
4444 struct mlx5_ifc_tsar_element_bits {
4445 	u8         reserved_at_0[0x8];
4446 	u8         tsar_type[0x8];
4447 	u8         reserved_at_10[0x10];
4448 };
4449 
4450 enum {
4451 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4452 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4453 };
4454 
4455 struct mlx5_ifc_teardown_hca_out_bits {
4456 	u8         status[0x8];
4457 	u8         reserved_at_8[0x18];
4458 
4459 	u8         syndrome[0x20];
4460 
4461 	u8         reserved_at_40[0x3f];
4462 
4463 	u8         state[0x1];
4464 };
4465 
4466 enum {
4467 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4468 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4469 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4470 };
4471 
4472 struct mlx5_ifc_teardown_hca_in_bits {
4473 	u8         opcode[0x10];
4474 	u8         reserved_at_10[0x10];
4475 
4476 	u8         reserved_at_20[0x10];
4477 	u8         op_mod[0x10];
4478 
4479 	u8         reserved_at_40[0x10];
4480 	u8         profile[0x10];
4481 
4482 	u8         reserved_at_60[0x20];
4483 };
4484 
4485 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4486 	u8         status[0x8];
4487 	u8         reserved_at_8[0x18];
4488 
4489 	u8         syndrome[0x20];
4490 
4491 	u8         reserved_at_40[0x40];
4492 };
4493 
4494 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4495 	u8         opcode[0x10];
4496 	u8         uid[0x10];
4497 
4498 	u8         reserved_at_20[0x10];
4499 	u8         op_mod[0x10];
4500 
4501 	u8         reserved_at_40[0x8];
4502 	u8         qpn[0x18];
4503 
4504 	u8         reserved_at_60[0x20];
4505 
4506 	u8         opt_param_mask[0x20];
4507 
4508 	u8         reserved_at_a0[0x20];
4509 
4510 	struct mlx5_ifc_qpc_bits qpc;
4511 
4512 	u8         reserved_at_800[0x80];
4513 };
4514 
4515 struct mlx5_ifc_sqd2rts_qp_out_bits {
4516 	u8         status[0x8];
4517 	u8         reserved_at_8[0x18];
4518 
4519 	u8         syndrome[0x20];
4520 
4521 	u8         reserved_at_40[0x40];
4522 };
4523 
4524 struct mlx5_ifc_sqd2rts_qp_in_bits {
4525 	u8         opcode[0x10];
4526 	u8         uid[0x10];
4527 
4528 	u8         reserved_at_20[0x10];
4529 	u8         op_mod[0x10];
4530 
4531 	u8         reserved_at_40[0x8];
4532 	u8         qpn[0x18];
4533 
4534 	u8         reserved_at_60[0x20];
4535 
4536 	u8         opt_param_mask[0x20];
4537 
4538 	u8         reserved_at_a0[0x20];
4539 
4540 	struct mlx5_ifc_qpc_bits qpc;
4541 
4542 	u8         reserved_at_800[0x80];
4543 };
4544 
4545 struct mlx5_ifc_set_roce_address_out_bits {
4546 	u8         status[0x8];
4547 	u8         reserved_at_8[0x18];
4548 
4549 	u8         syndrome[0x20];
4550 
4551 	u8         reserved_at_40[0x40];
4552 };
4553 
4554 struct mlx5_ifc_set_roce_address_in_bits {
4555 	u8         opcode[0x10];
4556 	u8         reserved_at_10[0x10];
4557 
4558 	u8         reserved_at_20[0x10];
4559 	u8         op_mod[0x10];
4560 
4561 	u8         roce_address_index[0x10];
4562 	u8         reserved_at_50[0xc];
4563 	u8	   vhca_port_num[0x4];
4564 
4565 	u8         reserved_at_60[0x20];
4566 
4567 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4568 };
4569 
4570 struct mlx5_ifc_set_mad_demux_out_bits {
4571 	u8         status[0x8];
4572 	u8         reserved_at_8[0x18];
4573 
4574 	u8         syndrome[0x20];
4575 
4576 	u8         reserved_at_40[0x40];
4577 };
4578 
4579 enum {
4580 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4581 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4582 };
4583 
4584 struct mlx5_ifc_set_mad_demux_in_bits {
4585 	u8         opcode[0x10];
4586 	u8         reserved_at_10[0x10];
4587 
4588 	u8         reserved_at_20[0x10];
4589 	u8         op_mod[0x10];
4590 
4591 	u8         reserved_at_40[0x20];
4592 
4593 	u8         reserved_at_60[0x6];
4594 	u8         demux_mode[0x2];
4595 	u8         reserved_at_68[0x18];
4596 };
4597 
4598 struct mlx5_ifc_set_l2_table_entry_out_bits {
4599 	u8         status[0x8];
4600 	u8         reserved_at_8[0x18];
4601 
4602 	u8         syndrome[0x20];
4603 
4604 	u8         reserved_at_40[0x40];
4605 };
4606 
4607 struct mlx5_ifc_set_l2_table_entry_in_bits {
4608 	u8         opcode[0x10];
4609 	u8         reserved_at_10[0x10];
4610 
4611 	u8         reserved_at_20[0x10];
4612 	u8         op_mod[0x10];
4613 
4614 	u8         reserved_at_40[0x60];
4615 
4616 	u8         reserved_at_a0[0x8];
4617 	u8         table_index[0x18];
4618 
4619 	u8         reserved_at_c0[0x20];
4620 
4621 	u8         reserved_at_e0[0x13];
4622 	u8         vlan_valid[0x1];
4623 	u8         vlan[0xc];
4624 
4625 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4626 
4627 	u8         reserved_at_140[0xc0];
4628 };
4629 
4630 struct mlx5_ifc_set_issi_out_bits {
4631 	u8         status[0x8];
4632 	u8         reserved_at_8[0x18];
4633 
4634 	u8         syndrome[0x20];
4635 
4636 	u8         reserved_at_40[0x40];
4637 };
4638 
4639 struct mlx5_ifc_set_issi_in_bits {
4640 	u8         opcode[0x10];
4641 	u8         reserved_at_10[0x10];
4642 
4643 	u8         reserved_at_20[0x10];
4644 	u8         op_mod[0x10];
4645 
4646 	u8         reserved_at_40[0x10];
4647 	u8         current_issi[0x10];
4648 
4649 	u8         reserved_at_60[0x20];
4650 };
4651 
4652 struct mlx5_ifc_set_hca_cap_out_bits {
4653 	u8         status[0x8];
4654 	u8         reserved_at_8[0x18];
4655 
4656 	u8         syndrome[0x20];
4657 
4658 	u8         reserved_at_40[0x40];
4659 };
4660 
4661 struct mlx5_ifc_set_hca_cap_in_bits {
4662 	u8         opcode[0x10];
4663 	u8         reserved_at_10[0x10];
4664 
4665 	u8         reserved_at_20[0x10];
4666 	u8         op_mod[0x10];
4667 
4668 	u8         other_function[0x1];
4669 	u8         reserved_at_41[0xf];
4670 	u8         function_id[0x10];
4671 
4672 	u8         reserved_at_60[0x20];
4673 
4674 	union mlx5_ifc_hca_cap_union_bits capability;
4675 };
4676 
4677 enum {
4678 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4679 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4680 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4681 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4682 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4683 };
4684 
4685 struct mlx5_ifc_set_fte_out_bits {
4686 	u8         status[0x8];
4687 	u8         reserved_at_8[0x18];
4688 
4689 	u8         syndrome[0x20];
4690 
4691 	u8         reserved_at_40[0x40];
4692 };
4693 
4694 struct mlx5_ifc_set_fte_in_bits {
4695 	u8         opcode[0x10];
4696 	u8         reserved_at_10[0x10];
4697 
4698 	u8         reserved_at_20[0x10];
4699 	u8         op_mod[0x10];
4700 
4701 	u8         other_vport[0x1];
4702 	u8         reserved_at_41[0xf];
4703 	u8         vport_number[0x10];
4704 
4705 	u8         reserved_at_60[0x20];
4706 
4707 	u8         table_type[0x8];
4708 	u8         reserved_at_88[0x18];
4709 
4710 	u8         reserved_at_a0[0x8];
4711 	u8         table_id[0x18];
4712 
4713 	u8         ignore_flow_level[0x1];
4714 	u8         reserved_at_c1[0x17];
4715 	u8         modify_enable_mask[0x8];
4716 
4717 	u8         reserved_at_e0[0x20];
4718 
4719 	u8         flow_index[0x20];
4720 
4721 	u8         reserved_at_120[0xe0];
4722 
4723 	struct mlx5_ifc_flow_context_bits flow_context;
4724 };
4725 
4726 struct mlx5_ifc_rts2rts_qp_out_bits {
4727 	u8         status[0x8];
4728 	u8         reserved_at_8[0x18];
4729 
4730 	u8         syndrome[0x20];
4731 
4732 	u8         reserved_at_40[0x20];
4733 	u8         ece[0x20];
4734 };
4735 
4736 struct mlx5_ifc_rts2rts_qp_in_bits {
4737 	u8         opcode[0x10];
4738 	u8         uid[0x10];
4739 
4740 	u8         reserved_at_20[0x10];
4741 	u8         op_mod[0x10];
4742 
4743 	u8         reserved_at_40[0x8];
4744 	u8         qpn[0x18];
4745 
4746 	u8         reserved_at_60[0x20];
4747 
4748 	u8         opt_param_mask[0x20];
4749 
4750 	u8         ece[0x20];
4751 
4752 	struct mlx5_ifc_qpc_bits qpc;
4753 
4754 	u8         reserved_at_800[0x80];
4755 };
4756 
4757 struct mlx5_ifc_rtr2rts_qp_out_bits {
4758 	u8         status[0x8];
4759 	u8         reserved_at_8[0x18];
4760 
4761 	u8         syndrome[0x20];
4762 
4763 	u8         reserved_at_40[0x20];
4764 	u8         ece[0x20];
4765 };
4766 
4767 struct mlx5_ifc_rtr2rts_qp_in_bits {
4768 	u8         opcode[0x10];
4769 	u8         uid[0x10];
4770 
4771 	u8         reserved_at_20[0x10];
4772 	u8         op_mod[0x10];
4773 
4774 	u8         reserved_at_40[0x8];
4775 	u8         qpn[0x18];
4776 
4777 	u8         reserved_at_60[0x20];
4778 
4779 	u8         opt_param_mask[0x20];
4780 
4781 	u8         ece[0x20];
4782 
4783 	struct mlx5_ifc_qpc_bits qpc;
4784 
4785 	u8         reserved_at_800[0x80];
4786 };
4787 
4788 struct mlx5_ifc_rst2init_qp_out_bits {
4789 	u8         status[0x8];
4790 	u8         reserved_at_8[0x18];
4791 
4792 	u8         syndrome[0x20];
4793 
4794 	u8         reserved_at_40[0x20];
4795 	u8         ece[0x20];
4796 };
4797 
4798 struct mlx5_ifc_rst2init_qp_in_bits {
4799 	u8         opcode[0x10];
4800 	u8         uid[0x10];
4801 
4802 	u8         reserved_at_20[0x10];
4803 	u8         op_mod[0x10];
4804 
4805 	u8         reserved_at_40[0x8];
4806 	u8         qpn[0x18];
4807 
4808 	u8         reserved_at_60[0x20];
4809 
4810 	u8         opt_param_mask[0x20];
4811 
4812 	u8         ece[0x20];
4813 
4814 	struct mlx5_ifc_qpc_bits qpc;
4815 
4816 	u8         reserved_at_800[0x80];
4817 };
4818 
4819 struct mlx5_ifc_query_xrq_out_bits {
4820 	u8         status[0x8];
4821 	u8         reserved_at_8[0x18];
4822 
4823 	u8         syndrome[0x20];
4824 
4825 	u8         reserved_at_40[0x40];
4826 
4827 	struct mlx5_ifc_xrqc_bits xrq_context;
4828 };
4829 
4830 struct mlx5_ifc_query_xrq_in_bits {
4831 	u8         opcode[0x10];
4832 	u8         reserved_at_10[0x10];
4833 
4834 	u8         reserved_at_20[0x10];
4835 	u8         op_mod[0x10];
4836 
4837 	u8         reserved_at_40[0x8];
4838 	u8         xrqn[0x18];
4839 
4840 	u8         reserved_at_60[0x20];
4841 };
4842 
4843 struct mlx5_ifc_query_xrc_srq_out_bits {
4844 	u8         status[0x8];
4845 	u8         reserved_at_8[0x18];
4846 
4847 	u8         syndrome[0x20];
4848 
4849 	u8         reserved_at_40[0x40];
4850 
4851 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4852 
4853 	u8         reserved_at_280[0x600];
4854 
4855 	u8         pas[][0x40];
4856 };
4857 
4858 struct mlx5_ifc_query_xrc_srq_in_bits {
4859 	u8         opcode[0x10];
4860 	u8         reserved_at_10[0x10];
4861 
4862 	u8         reserved_at_20[0x10];
4863 	u8         op_mod[0x10];
4864 
4865 	u8         reserved_at_40[0x8];
4866 	u8         xrc_srqn[0x18];
4867 
4868 	u8         reserved_at_60[0x20];
4869 };
4870 
4871 enum {
4872 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4873 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4874 };
4875 
4876 struct mlx5_ifc_query_vport_state_out_bits {
4877 	u8         status[0x8];
4878 	u8         reserved_at_8[0x18];
4879 
4880 	u8         syndrome[0x20];
4881 
4882 	u8         reserved_at_40[0x20];
4883 
4884 	u8         reserved_at_60[0x18];
4885 	u8         admin_state[0x4];
4886 	u8         state[0x4];
4887 };
4888 
4889 enum {
4890 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4891 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4892 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4893 };
4894 
4895 struct mlx5_ifc_arm_monitor_counter_in_bits {
4896 	u8         opcode[0x10];
4897 	u8         uid[0x10];
4898 
4899 	u8         reserved_at_20[0x10];
4900 	u8         op_mod[0x10];
4901 
4902 	u8         reserved_at_40[0x20];
4903 
4904 	u8         reserved_at_60[0x20];
4905 };
4906 
4907 struct mlx5_ifc_arm_monitor_counter_out_bits {
4908 	u8         status[0x8];
4909 	u8         reserved_at_8[0x18];
4910 
4911 	u8         syndrome[0x20];
4912 
4913 	u8         reserved_at_40[0x40];
4914 };
4915 
4916 enum {
4917 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4918 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4919 };
4920 
4921 enum mlx5_monitor_counter_ppcnt {
4922 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4923 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4924 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4925 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4926 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4927 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4928 };
4929 
4930 enum {
4931 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4932 };
4933 
4934 struct mlx5_ifc_monitor_counter_output_bits {
4935 	u8         reserved_at_0[0x4];
4936 	u8         type[0x4];
4937 	u8         reserved_at_8[0x8];
4938 	u8         counter[0x10];
4939 
4940 	u8         counter_group_id[0x20];
4941 };
4942 
4943 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4944 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4945 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4946 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4947 
4948 struct mlx5_ifc_set_monitor_counter_in_bits {
4949 	u8         opcode[0x10];
4950 	u8         uid[0x10];
4951 
4952 	u8         reserved_at_20[0x10];
4953 	u8         op_mod[0x10];
4954 
4955 	u8         reserved_at_40[0x10];
4956 	u8         num_of_counters[0x10];
4957 
4958 	u8         reserved_at_60[0x20];
4959 
4960 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4961 };
4962 
4963 struct mlx5_ifc_set_monitor_counter_out_bits {
4964 	u8         status[0x8];
4965 	u8         reserved_at_8[0x18];
4966 
4967 	u8         syndrome[0x20];
4968 
4969 	u8         reserved_at_40[0x40];
4970 };
4971 
4972 struct mlx5_ifc_query_vport_state_in_bits {
4973 	u8         opcode[0x10];
4974 	u8         reserved_at_10[0x10];
4975 
4976 	u8         reserved_at_20[0x10];
4977 	u8         op_mod[0x10];
4978 
4979 	u8         other_vport[0x1];
4980 	u8         reserved_at_41[0xf];
4981 	u8         vport_number[0x10];
4982 
4983 	u8         reserved_at_60[0x20];
4984 };
4985 
4986 struct mlx5_ifc_query_vnic_env_out_bits {
4987 	u8         status[0x8];
4988 	u8         reserved_at_8[0x18];
4989 
4990 	u8         syndrome[0x20];
4991 
4992 	u8         reserved_at_40[0x40];
4993 
4994 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4995 };
4996 
4997 enum {
4998 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4999 };
5000 
5001 struct mlx5_ifc_query_vnic_env_in_bits {
5002 	u8         opcode[0x10];
5003 	u8         reserved_at_10[0x10];
5004 
5005 	u8         reserved_at_20[0x10];
5006 	u8         op_mod[0x10];
5007 
5008 	u8         other_vport[0x1];
5009 	u8         reserved_at_41[0xf];
5010 	u8         vport_number[0x10];
5011 
5012 	u8         reserved_at_60[0x20];
5013 };
5014 
5015 struct mlx5_ifc_query_vport_counter_out_bits {
5016 	u8         status[0x8];
5017 	u8         reserved_at_8[0x18];
5018 
5019 	u8         syndrome[0x20];
5020 
5021 	u8         reserved_at_40[0x40];
5022 
5023 	struct mlx5_ifc_traffic_counter_bits received_errors;
5024 
5025 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5026 
5027 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5028 
5029 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5030 
5031 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5032 
5033 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5034 
5035 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5036 
5037 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5038 
5039 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5040 
5041 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5042 
5043 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5044 
5045 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5046 
5047 	u8         reserved_at_680[0xa00];
5048 };
5049 
5050 enum {
5051 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5052 };
5053 
5054 struct mlx5_ifc_query_vport_counter_in_bits {
5055 	u8         opcode[0x10];
5056 	u8         reserved_at_10[0x10];
5057 
5058 	u8         reserved_at_20[0x10];
5059 	u8         op_mod[0x10];
5060 
5061 	u8         other_vport[0x1];
5062 	u8         reserved_at_41[0xb];
5063 	u8	   port_num[0x4];
5064 	u8         vport_number[0x10];
5065 
5066 	u8         reserved_at_60[0x60];
5067 
5068 	u8         clear[0x1];
5069 	u8         reserved_at_c1[0x1f];
5070 
5071 	u8         reserved_at_e0[0x20];
5072 };
5073 
5074 struct mlx5_ifc_query_tis_out_bits {
5075 	u8         status[0x8];
5076 	u8         reserved_at_8[0x18];
5077 
5078 	u8         syndrome[0x20];
5079 
5080 	u8         reserved_at_40[0x40];
5081 
5082 	struct mlx5_ifc_tisc_bits tis_context;
5083 };
5084 
5085 struct mlx5_ifc_query_tis_in_bits {
5086 	u8         opcode[0x10];
5087 	u8         reserved_at_10[0x10];
5088 
5089 	u8         reserved_at_20[0x10];
5090 	u8         op_mod[0x10];
5091 
5092 	u8         reserved_at_40[0x8];
5093 	u8         tisn[0x18];
5094 
5095 	u8         reserved_at_60[0x20];
5096 };
5097 
5098 struct mlx5_ifc_query_tir_out_bits {
5099 	u8         status[0x8];
5100 	u8         reserved_at_8[0x18];
5101 
5102 	u8         syndrome[0x20];
5103 
5104 	u8         reserved_at_40[0xc0];
5105 
5106 	struct mlx5_ifc_tirc_bits tir_context;
5107 };
5108 
5109 struct mlx5_ifc_query_tir_in_bits {
5110 	u8         opcode[0x10];
5111 	u8         reserved_at_10[0x10];
5112 
5113 	u8         reserved_at_20[0x10];
5114 	u8         op_mod[0x10];
5115 
5116 	u8         reserved_at_40[0x8];
5117 	u8         tirn[0x18];
5118 
5119 	u8         reserved_at_60[0x20];
5120 };
5121 
5122 struct mlx5_ifc_query_srq_out_bits {
5123 	u8         status[0x8];
5124 	u8         reserved_at_8[0x18];
5125 
5126 	u8         syndrome[0x20];
5127 
5128 	u8         reserved_at_40[0x40];
5129 
5130 	struct mlx5_ifc_srqc_bits srq_context_entry;
5131 
5132 	u8         reserved_at_280[0x600];
5133 
5134 	u8         pas[][0x40];
5135 };
5136 
5137 struct mlx5_ifc_query_srq_in_bits {
5138 	u8         opcode[0x10];
5139 	u8         reserved_at_10[0x10];
5140 
5141 	u8         reserved_at_20[0x10];
5142 	u8         op_mod[0x10];
5143 
5144 	u8         reserved_at_40[0x8];
5145 	u8         srqn[0x18];
5146 
5147 	u8         reserved_at_60[0x20];
5148 };
5149 
5150 struct mlx5_ifc_query_sq_out_bits {
5151 	u8         status[0x8];
5152 	u8         reserved_at_8[0x18];
5153 
5154 	u8         syndrome[0x20];
5155 
5156 	u8         reserved_at_40[0xc0];
5157 
5158 	struct mlx5_ifc_sqc_bits sq_context;
5159 };
5160 
5161 struct mlx5_ifc_query_sq_in_bits {
5162 	u8         opcode[0x10];
5163 	u8         reserved_at_10[0x10];
5164 
5165 	u8         reserved_at_20[0x10];
5166 	u8         op_mod[0x10];
5167 
5168 	u8         reserved_at_40[0x8];
5169 	u8         sqn[0x18];
5170 
5171 	u8         reserved_at_60[0x20];
5172 };
5173 
5174 struct mlx5_ifc_query_special_contexts_out_bits {
5175 	u8         status[0x8];
5176 	u8         reserved_at_8[0x18];
5177 
5178 	u8         syndrome[0x20];
5179 
5180 	u8         dump_fill_mkey[0x20];
5181 
5182 	u8         resd_lkey[0x20];
5183 
5184 	u8         null_mkey[0x20];
5185 
5186 	u8         reserved_at_a0[0x60];
5187 };
5188 
5189 struct mlx5_ifc_query_special_contexts_in_bits {
5190 	u8         opcode[0x10];
5191 	u8         reserved_at_10[0x10];
5192 
5193 	u8         reserved_at_20[0x10];
5194 	u8         op_mod[0x10];
5195 
5196 	u8         reserved_at_40[0x40];
5197 };
5198 
5199 struct mlx5_ifc_query_scheduling_element_out_bits {
5200 	u8         opcode[0x10];
5201 	u8         reserved_at_10[0x10];
5202 
5203 	u8         reserved_at_20[0x10];
5204 	u8         op_mod[0x10];
5205 
5206 	u8         reserved_at_40[0xc0];
5207 
5208 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5209 
5210 	u8         reserved_at_300[0x100];
5211 };
5212 
5213 enum {
5214 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5215 	SCHEDULING_HIERARCHY_NIC = 0x3,
5216 };
5217 
5218 struct mlx5_ifc_query_scheduling_element_in_bits {
5219 	u8         opcode[0x10];
5220 	u8         reserved_at_10[0x10];
5221 
5222 	u8         reserved_at_20[0x10];
5223 	u8         op_mod[0x10];
5224 
5225 	u8         scheduling_hierarchy[0x8];
5226 	u8         reserved_at_48[0x18];
5227 
5228 	u8         scheduling_element_id[0x20];
5229 
5230 	u8         reserved_at_80[0x180];
5231 };
5232 
5233 struct mlx5_ifc_query_rqt_out_bits {
5234 	u8         status[0x8];
5235 	u8         reserved_at_8[0x18];
5236 
5237 	u8         syndrome[0x20];
5238 
5239 	u8         reserved_at_40[0xc0];
5240 
5241 	struct mlx5_ifc_rqtc_bits rqt_context;
5242 };
5243 
5244 struct mlx5_ifc_query_rqt_in_bits {
5245 	u8         opcode[0x10];
5246 	u8         reserved_at_10[0x10];
5247 
5248 	u8         reserved_at_20[0x10];
5249 	u8         op_mod[0x10];
5250 
5251 	u8         reserved_at_40[0x8];
5252 	u8         rqtn[0x18];
5253 
5254 	u8         reserved_at_60[0x20];
5255 };
5256 
5257 struct mlx5_ifc_query_rq_out_bits {
5258 	u8         status[0x8];
5259 	u8         reserved_at_8[0x18];
5260 
5261 	u8         syndrome[0x20];
5262 
5263 	u8         reserved_at_40[0xc0];
5264 
5265 	struct mlx5_ifc_rqc_bits rq_context;
5266 };
5267 
5268 struct mlx5_ifc_query_rq_in_bits {
5269 	u8         opcode[0x10];
5270 	u8         reserved_at_10[0x10];
5271 
5272 	u8         reserved_at_20[0x10];
5273 	u8         op_mod[0x10];
5274 
5275 	u8         reserved_at_40[0x8];
5276 	u8         rqn[0x18];
5277 
5278 	u8         reserved_at_60[0x20];
5279 };
5280 
5281 struct mlx5_ifc_query_roce_address_out_bits {
5282 	u8         status[0x8];
5283 	u8         reserved_at_8[0x18];
5284 
5285 	u8         syndrome[0x20];
5286 
5287 	u8         reserved_at_40[0x40];
5288 
5289 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5290 };
5291 
5292 struct mlx5_ifc_query_roce_address_in_bits {
5293 	u8         opcode[0x10];
5294 	u8         reserved_at_10[0x10];
5295 
5296 	u8         reserved_at_20[0x10];
5297 	u8         op_mod[0x10];
5298 
5299 	u8         roce_address_index[0x10];
5300 	u8         reserved_at_50[0xc];
5301 	u8	   vhca_port_num[0x4];
5302 
5303 	u8         reserved_at_60[0x20];
5304 };
5305 
5306 struct mlx5_ifc_query_rmp_out_bits {
5307 	u8         status[0x8];
5308 	u8         reserved_at_8[0x18];
5309 
5310 	u8         syndrome[0x20];
5311 
5312 	u8         reserved_at_40[0xc0];
5313 
5314 	struct mlx5_ifc_rmpc_bits rmp_context;
5315 };
5316 
5317 struct mlx5_ifc_query_rmp_in_bits {
5318 	u8         opcode[0x10];
5319 	u8         reserved_at_10[0x10];
5320 
5321 	u8         reserved_at_20[0x10];
5322 	u8         op_mod[0x10];
5323 
5324 	u8         reserved_at_40[0x8];
5325 	u8         rmpn[0x18];
5326 
5327 	u8         reserved_at_60[0x20];
5328 };
5329 
5330 struct mlx5_ifc_query_qp_out_bits {
5331 	u8         status[0x8];
5332 	u8         reserved_at_8[0x18];
5333 
5334 	u8         syndrome[0x20];
5335 
5336 	u8         reserved_at_40[0x40];
5337 
5338 	u8         opt_param_mask[0x20];
5339 
5340 	u8         ece[0x20];
5341 
5342 	struct mlx5_ifc_qpc_bits qpc;
5343 
5344 	u8         reserved_at_800[0x80];
5345 
5346 	u8         pas[][0x40];
5347 };
5348 
5349 struct mlx5_ifc_query_qp_in_bits {
5350 	u8         opcode[0x10];
5351 	u8         reserved_at_10[0x10];
5352 
5353 	u8         reserved_at_20[0x10];
5354 	u8         op_mod[0x10];
5355 
5356 	u8         reserved_at_40[0x8];
5357 	u8         qpn[0x18];
5358 
5359 	u8         reserved_at_60[0x20];
5360 };
5361 
5362 struct mlx5_ifc_query_q_counter_out_bits {
5363 	u8         status[0x8];
5364 	u8         reserved_at_8[0x18];
5365 
5366 	u8         syndrome[0x20];
5367 
5368 	u8         reserved_at_40[0x40];
5369 
5370 	u8         rx_write_requests[0x20];
5371 
5372 	u8         reserved_at_a0[0x20];
5373 
5374 	u8         rx_read_requests[0x20];
5375 
5376 	u8         reserved_at_e0[0x20];
5377 
5378 	u8         rx_atomic_requests[0x20];
5379 
5380 	u8         reserved_at_120[0x20];
5381 
5382 	u8         rx_dct_connect[0x20];
5383 
5384 	u8         reserved_at_160[0x20];
5385 
5386 	u8         out_of_buffer[0x20];
5387 
5388 	u8         reserved_at_1a0[0x20];
5389 
5390 	u8         out_of_sequence[0x20];
5391 
5392 	u8         reserved_at_1e0[0x20];
5393 
5394 	u8         duplicate_request[0x20];
5395 
5396 	u8         reserved_at_220[0x20];
5397 
5398 	u8         rnr_nak_retry_err[0x20];
5399 
5400 	u8         reserved_at_260[0x20];
5401 
5402 	u8         packet_seq_err[0x20];
5403 
5404 	u8         reserved_at_2a0[0x20];
5405 
5406 	u8         implied_nak_seq_err[0x20];
5407 
5408 	u8         reserved_at_2e0[0x20];
5409 
5410 	u8         local_ack_timeout_err[0x20];
5411 
5412 	u8         reserved_at_320[0xa0];
5413 
5414 	u8         resp_local_length_error[0x20];
5415 
5416 	u8         req_local_length_error[0x20];
5417 
5418 	u8         resp_local_qp_error[0x20];
5419 
5420 	u8         local_operation_error[0x20];
5421 
5422 	u8         resp_local_protection[0x20];
5423 
5424 	u8         req_local_protection[0x20];
5425 
5426 	u8         resp_cqe_error[0x20];
5427 
5428 	u8         req_cqe_error[0x20];
5429 
5430 	u8         req_mw_binding[0x20];
5431 
5432 	u8         req_bad_response[0x20];
5433 
5434 	u8         req_remote_invalid_request[0x20];
5435 
5436 	u8         resp_remote_invalid_request[0x20];
5437 
5438 	u8         req_remote_access_errors[0x20];
5439 
5440 	u8	   resp_remote_access_errors[0x20];
5441 
5442 	u8         req_remote_operation_errors[0x20];
5443 
5444 	u8         req_transport_retries_exceeded[0x20];
5445 
5446 	u8         cq_overflow[0x20];
5447 
5448 	u8         resp_cqe_flush_error[0x20];
5449 
5450 	u8         req_cqe_flush_error[0x20];
5451 
5452 	u8         reserved_at_620[0x20];
5453 
5454 	u8         roce_adp_retrans[0x20];
5455 
5456 	u8         roce_adp_retrans_to[0x20];
5457 
5458 	u8         roce_slow_restart[0x20];
5459 
5460 	u8         roce_slow_restart_cnps[0x20];
5461 
5462 	u8         roce_slow_restart_trans[0x20];
5463 
5464 	u8         reserved_at_6e0[0x120];
5465 };
5466 
5467 struct mlx5_ifc_query_q_counter_in_bits {
5468 	u8         opcode[0x10];
5469 	u8         reserved_at_10[0x10];
5470 
5471 	u8         reserved_at_20[0x10];
5472 	u8         op_mod[0x10];
5473 
5474 	u8         reserved_at_40[0x80];
5475 
5476 	u8         clear[0x1];
5477 	u8         reserved_at_c1[0x1f];
5478 
5479 	u8         reserved_at_e0[0x18];
5480 	u8         counter_set_id[0x8];
5481 };
5482 
5483 struct mlx5_ifc_query_pages_out_bits {
5484 	u8         status[0x8];
5485 	u8         reserved_at_8[0x18];
5486 
5487 	u8         syndrome[0x20];
5488 
5489 	u8         embedded_cpu_function[0x1];
5490 	u8         reserved_at_41[0xf];
5491 	u8         function_id[0x10];
5492 
5493 	u8         num_pages[0x20];
5494 };
5495 
5496 enum {
5497 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5498 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5499 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5500 };
5501 
5502 struct mlx5_ifc_query_pages_in_bits {
5503 	u8         opcode[0x10];
5504 	u8         reserved_at_10[0x10];
5505 
5506 	u8         reserved_at_20[0x10];
5507 	u8         op_mod[0x10];
5508 
5509 	u8         embedded_cpu_function[0x1];
5510 	u8         reserved_at_41[0xf];
5511 	u8         function_id[0x10];
5512 
5513 	u8         reserved_at_60[0x20];
5514 };
5515 
5516 struct mlx5_ifc_query_nic_vport_context_out_bits {
5517 	u8         status[0x8];
5518 	u8         reserved_at_8[0x18];
5519 
5520 	u8         syndrome[0x20];
5521 
5522 	u8         reserved_at_40[0x40];
5523 
5524 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5525 };
5526 
5527 struct mlx5_ifc_query_nic_vport_context_in_bits {
5528 	u8         opcode[0x10];
5529 	u8         reserved_at_10[0x10];
5530 
5531 	u8         reserved_at_20[0x10];
5532 	u8         op_mod[0x10];
5533 
5534 	u8         other_vport[0x1];
5535 	u8         reserved_at_41[0xf];
5536 	u8         vport_number[0x10];
5537 
5538 	u8         reserved_at_60[0x5];
5539 	u8         allowed_list_type[0x3];
5540 	u8         reserved_at_68[0x18];
5541 };
5542 
5543 struct mlx5_ifc_query_mkey_out_bits {
5544 	u8         status[0x8];
5545 	u8         reserved_at_8[0x18];
5546 
5547 	u8         syndrome[0x20];
5548 
5549 	u8         reserved_at_40[0x40];
5550 
5551 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5552 
5553 	u8         reserved_at_280[0x600];
5554 
5555 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5556 
5557 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5558 };
5559 
5560 struct mlx5_ifc_query_mkey_in_bits {
5561 	u8         opcode[0x10];
5562 	u8         reserved_at_10[0x10];
5563 
5564 	u8         reserved_at_20[0x10];
5565 	u8         op_mod[0x10];
5566 
5567 	u8         reserved_at_40[0x8];
5568 	u8         mkey_index[0x18];
5569 
5570 	u8         pg_access[0x1];
5571 	u8         reserved_at_61[0x1f];
5572 };
5573 
5574 struct mlx5_ifc_query_mad_demux_out_bits {
5575 	u8         status[0x8];
5576 	u8         reserved_at_8[0x18];
5577 
5578 	u8         syndrome[0x20];
5579 
5580 	u8         reserved_at_40[0x40];
5581 
5582 	u8         mad_dumux_parameters_block[0x20];
5583 };
5584 
5585 struct mlx5_ifc_query_mad_demux_in_bits {
5586 	u8         opcode[0x10];
5587 	u8         reserved_at_10[0x10];
5588 
5589 	u8         reserved_at_20[0x10];
5590 	u8         op_mod[0x10];
5591 
5592 	u8         reserved_at_40[0x40];
5593 };
5594 
5595 struct mlx5_ifc_query_l2_table_entry_out_bits {
5596 	u8         status[0x8];
5597 	u8         reserved_at_8[0x18];
5598 
5599 	u8         syndrome[0x20];
5600 
5601 	u8         reserved_at_40[0xa0];
5602 
5603 	u8         reserved_at_e0[0x13];
5604 	u8         vlan_valid[0x1];
5605 	u8         vlan[0xc];
5606 
5607 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5608 
5609 	u8         reserved_at_140[0xc0];
5610 };
5611 
5612 struct mlx5_ifc_query_l2_table_entry_in_bits {
5613 	u8         opcode[0x10];
5614 	u8         reserved_at_10[0x10];
5615 
5616 	u8         reserved_at_20[0x10];
5617 	u8         op_mod[0x10];
5618 
5619 	u8         reserved_at_40[0x60];
5620 
5621 	u8         reserved_at_a0[0x8];
5622 	u8         table_index[0x18];
5623 
5624 	u8         reserved_at_c0[0x140];
5625 };
5626 
5627 struct mlx5_ifc_query_issi_out_bits {
5628 	u8         status[0x8];
5629 	u8         reserved_at_8[0x18];
5630 
5631 	u8         syndrome[0x20];
5632 
5633 	u8         reserved_at_40[0x10];
5634 	u8         current_issi[0x10];
5635 
5636 	u8         reserved_at_60[0xa0];
5637 
5638 	u8         reserved_at_100[76][0x8];
5639 	u8         supported_issi_dw0[0x20];
5640 };
5641 
5642 struct mlx5_ifc_query_issi_in_bits {
5643 	u8         opcode[0x10];
5644 	u8         reserved_at_10[0x10];
5645 
5646 	u8         reserved_at_20[0x10];
5647 	u8         op_mod[0x10];
5648 
5649 	u8         reserved_at_40[0x40];
5650 };
5651 
5652 struct mlx5_ifc_set_driver_version_out_bits {
5653 	u8         status[0x8];
5654 	u8         reserved_0[0x18];
5655 
5656 	u8         syndrome[0x20];
5657 	u8         reserved_1[0x40];
5658 };
5659 
5660 struct mlx5_ifc_set_driver_version_in_bits {
5661 	u8         opcode[0x10];
5662 	u8         reserved_0[0x10];
5663 
5664 	u8         reserved_1[0x10];
5665 	u8         op_mod[0x10];
5666 
5667 	u8         reserved_2[0x40];
5668 	u8         driver_version[64][0x8];
5669 };
5670 
5671 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5672 	u8         status[0x8];
5673 	u8         reserved_at_8[0x18];
5674 
5675 	u8         syndrome[0x20];
5676 
5677 	u8         reserved_at_40[0x40];
5678 
5679 	struct mlx5_ifc_pkey_bits pkey[];
5680 };
5681 
5682 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5683 	u8         opcode[0x10];
5684 	u8         reserved_at_10[0x10];
5685 
5686 	u8         reserved_at_20[0x10];
5687 	u8         op_mod[0x10];
5688 
5689 	u8         other_vport[0x1];
5690 	u8         reserved_at_41[0xb];
5691 	u8         port_num[0x4];
5692 	u8         vport_number[0x10];
5693 
5694 	u8         reserved_at_60[0x10];
5695 	u8         pkey_index[0x10];
5696 };
5697 
5698 enum {
5699 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5700 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5701 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5702 };
5703 
5704 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5705 	u8         status[0x8];
5706 	u8         reserved_at_8[0x18];
5707 
5708 	u8         syndrome[0x20];
5709 
5710 	u8         reserved_at_40[0x20];
5711 
5712 	u8         gids_num[0x10];
5713 	u8         reserved_at_70[0x10];
5714 
5715 	struct mlx5_ifc_array128_auto_bits gid[];
5716 };
5717 
5718 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5719 	u8         opcode[0x10];
5720 	u8         reserved_at_10[0x10];
5721 
5722 	u8         reserved_at_20[0x10];
5723 	u8         op_mod[0x10];
5724 
5725 	u8         other_vport[0x1];
5726 	u8         reserved_at_41[0xb];
5727 	u8         port_num[0x4];
5728 	u8         vport_number[0x10];
5729 
5730 	u8         reserved_at_60[0x10];
5731 	u8         gid_index[0x10];
5732 };
5733 
5734 struct mlx5_ifc_query_hca_vport_context_out_bits {
5735 	u8         status[0x8];
5736 	u8         reserved_at_8[0x18];
5737 
5738 	u8         syndrome[0x20];
5739 
5740 	u8         reserved_at_40[0x40];
5741 
5742 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5743 };
5744 
5745 struct mlx5_ifc_query_hca_vport_context_in_bits {
5746 	u8         opcode[0x10];
5747 	u8         reserved_at_10[0x10];
5748 
5749 	u8         reserved_at_20[0x10];
5750 	u8         op_mod[0x10];
5751 
5752 	u8         other_vport[0x1];
5753 	u8         reserved_at_41[0xb];
5754 	u8         port_num[0x4];
5755 	u8         vport_number[0x10];
5756 
5757 	u8         reserved_at_60[0x20];
5758 };
5759 
5760 struct mlx5_ifc_query_hca_cap_out_bits {
5761 	u8         status[0x8];
5762 	u8         reserved_at_8[0x18];
5763 
5764 	u8         syndrome[0x20];
5765 
5766 	u8         reserved_at_40[0x40];
5767 
5768 	union mlx5_ifc_hca_cap_union_bits capability;
5769 };
5770 
5771 struct mlx5_ifc_query_hca_cap_in_bits {
5772 	u8         opcode[0x10];
5773 	u8         reserved_at_10[0x10];
5774 
5775 	u8         reserved_at_20[0x10];
5776 	u8         op_mod[0x10];
5777 
5778 	u8         other_function[0x1];
5779 	u8         reserved_at_41[0xf];
5780 	u8         function_id[0x10];
5781 
5782 	u8         reserved_at_60[0x20];
5783 };
5784 
5785 struct mlx5_ifc_other_hca_cap_bits {
5786 	u8         roce[0x1];
5787 	u8         reserved_at_1[0x27f];
5788 };
5789 
5790 struct mlx5_ifc_query_other_hca_cap_out_bits {
5791 	u8         status[0x8];
5792 	u8         reserved_at_8[0x18];
5793 
5794 	u8         syndrome[0x20];
5795 
5796 	u8         reserved_at_40[0x40];
5797 
5798 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5799 };
5800 
5801 struct mlx5_ifc_query_other_hca_cap_in_bits {
5802 	u8         opcode[0x10];
5803 	u8         reserved_at_10[0x10];
5804 
5805 	u8         reserved_at_20[0x10];
5806 	u8         op_mod[0x10];
5807 
5808 	u8         reserved_at_40[0x10];
5809 	u8         function_id[0x10];
5810 
5811 	u8         reserved_at_60[0x20];
5812 };
5813 
5814 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5815 	u8         status[0x8];
5816 	u8         reserved_at_8[0x18];
5817 
5818 	u8         syndrome[0x20];
5819 
5820 	u8         reserved_at_40[0x40];
5821 };
5822 
5823 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5824 	u8         opcode[0x10];
5825 	u8         reserved_at_10[0x10];
5826 
5827 	u8         reserved_at_20[0x10];
5828 	u8         op_mod[0x10];
5829 
5830 	u8         reserved_at_40[0x10];
5831 	u8         function_id[0x10];
5832 	u8         field_select[0x20];
5833 
5834 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5835 };
5836 
5837 struct mlx5_ifc_flow_table_context_bits {
5838 	u8         reformat_en[0x1];
5839 	u8         decap_en[0x1];
5840 	u8         sw_owner[0x1];
5841 	u8         termination_table[0x1];
5842 	u8         table_miss_action[0x4];
5843 	u8         level[0x8];
5844 	u8         reserved_at_10[0x8];
5845 	u8         log_size[0x8];
5846 
5847 	u8         reserved_at_20[0x8];
5848 	u8         table_miss_id[0x18];
5849 
5850 	u8         reserved_at_40[0x8];
5851 	u8         lag_master_next_table_id[0x18];
5852 
5853 	u8         reserved_at_60[0x60];
5854 
5855 	u8         sw_owner_icm_root_1[0x40];
5856 
5857 	u8         sw_owner_icm_root_0[0x40];
5858 
5859 };
5860 
5861 struct mlx5_ifc_query_flow_table_out_bits {
5862 	u8         status[0x8];
5863 	u8         reserved_at_8[0x18];
5864 
5865 	u8         syndrome[0x20];
5866 
5867 	u8         reserved_at_40[0x80];
5868 
5869 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
5870 };
5871 
5872 struct mlx5_ifc_query_flow_table_in_bits {
5873 	u8         opcode[0x10];
5874 	u8         reserved_at_10[0x10];
5875 
5876 	u8         reserved_at_20[0x10];
5877 	u8         op_mod[0x10];
5878 
5879 	u8         reserved_at_40[0x40];
5880 
5881 	u8         table_type[0x8];
5882 	u8         reserved_at_88[0x18];
5883 
5884 	u8         reserved_at_a0[0x8];
5885 	u8         table_id[0x18];
5886 
5887 	u8         reserved_at_c0[0x140];
5888 };
5889 
5890 struct mlx5_ifc_query_fte_out_bits {
5891 	u8         status[0x8];
5892 	u8         reserved_at_8[0x18];
5893 
5894 	u8         syndrome[0x20];
5895 
5896 	u8         reserved_at_40[0x1c0];
5897 
5898 	struct mlx5_ifc_flow_context_bits flow_context;
5899 };
5900 
5901 struct mlx5_ifc_query_fte_in_bits {
5902 	u8         opcode[0x10];
5903 	u8         reserved_at_10[0x10];
5904 
5905 	u8         reserved_at_20[0x10];
5906 	u8         op_mod[0x10];
5907 
5908 	u8         reserved_at_40[0x40];
5909 
5910 	u8         table_type[0x8];
5911 	u8         reserved_at_88[0x18];
5912 
5913 	u8         reserved_at_a0[0x8];
5914 	u8         table_id[0x18];
5915 
5916 	u8         reserved_at_c0[0x40];
5917 
5918 	u8         flow_index[0x20];
5919 
5920 	u8         reserved_at_120[0xe0];
5921 };
5922 
5923 struct mlx5_ifc_match_definer_format_0_bits {
5924 	u8         reserved_at_0[0x100];
5925 
5926 	u8         metadata_reg_c_0[0x20];
5927 
5928 	u8         metadata_reg_c_1[0x20];
5929 
5930 	u8         outer_dmac_47_16[0x20];
5931 
5932 	u8         outer_dmac_15_0[0x10];
5933 	u8         outer_ethertype[0x10];
5934 
5935 	u8         reserved_at_180[0x1];
5936 	u8         sx_sniffer[0x1];
5937 	u8         functional_lb[0x1];
5938 	u8         outer_ip_frag[0x1];
5939 	u8         outer_qp_type[0x2];
5940 	u8         outer_encap_type[0x2];
5941 	u8         port_number[0x2];
5942 	u8         outer_l3_type[0x2];
5943 	u8         outer_l4_type[0x2];
5944 	u8         outer_first_vlan_type[0x2];
5945 	u8         outer_first_vlan_prio[0x3];
5946 	u8         outer_first_vlan_cfi[0x1];
5947 	u8         outer_first_vlan_vid[0xc];
5948 
5949 	u8         outer_l4_type_ext[0x4];
5950 	u8         reserved_at_1a4[0x2];
5951 	u8         outer_ipsec_layer[0x2];
5952 	u8         outer_l2_type[0x2];
5953 	u8         force_lb[0x1];
5954 	u8         outer_l2_ok[0x1];
5955 	u8         outer_l3_ok[0x1];
5956 	u8         outer_l4_ok[0x1];
5957 	u8         outer_second_vlan_type[0x2];
5958 	u8         outer_second_vlan_prio[0x3];
5959 	u8         outer_second_vlan_cfi[0x1];
5960 	u8         outer_second_vlan_vid[0xc];
5961 
5962 	u8         outer_smac_47_16[0x20];
5963 
5964 	u8         outer_smac_15_0[0x10];
5965 	u8         inner_ipv4_checksum_ok[0x1];
5966 	u8         inner_l4_checksum_ok[0x1];
5967 	u8         outer_ipv4_checksum_ok[0x1];
5968 	u8         outer_l4_checksum_ok[0x1];
5969 	u8         inner_l3_ok[0x1];
5970 	u8         inner_l4_ok[0x1];
5971 	u8         outer_l3_ok_duplicate[0x1];
5972 	u8         outer_l4_ok_duplicate[0x1];
5973 	u8         outer_tcp_cwr[0x1];
5974 	u8         outer_tcp_ece[0x1];
5975 	u8         outer_tcp_urg[0x1];
5976 	u8         outer_tcp_ack[0x1];
5977 	u8         outer_tcp_psh[0x1];
5978 	u8         outer_tcp_rst[0x1];
5979 	u8         outer_tcp_syn[0x1];
5980 	u8         outer_tcp_fin[0x1];
5981 };
5982 
5983 struct mlx5_ifc_match_definer_format_22_bits {
5984 	u8         reserved_at_0[0x100];
5985 
5986 	u8         outer_ip_src_addr[0x20];
5987 
5988 	u8         outer_ip_dest_addr[0x20];
5989 
5990 	u8         outer_l4_sport[0x10];
5991 	u8         outer_l4_dport[0x10];
5992 
5993 	u8         reserved_at_160[0x1];
5994 	u8         sx_sniffer[0x1];
5995 	u8         functional_lb[0x1];
5996 	u8         outer_ip_frag[0x1];
5997 	u8         outer_qp_type[0x2];
5998 	u8         outer_encap_type[0x2];
5999 	u8         port_number[0x2];
6000 	u8         outer_l3_type[0x2];
6001 	u8         outer_l4_type[0x2];
6002 	u8         outer_first_vlan_type[0x2];
6003 	u8         outer_first_vlan_prio[0x3];
6004 	u8         outer_first_vlan_cfi[0x1];
6005 	u8         outer_first_vlan_vid[0xc];
6006 
6007 	u8         metadata_reg_c_0[0x20];
6008 
6009 	u8         outer_dmac_47_16[0x20];
6010 
6011 	u8         outer_smac_47_16[0x20];
6012 
6013 	u8         outer_smac_15_0[0x10];
6014 	u8         outer_dmac_15_0[0x10];
6015 };
6016 
6017 struct mlx5_ifc_match_definer_format_23_bits {
6018 	u8         reserved_at_0[0x100];
6019 
6020 	u8         inner_ip_src_addr[0x20];
6021 
6022 	u8         inner_ip_dest_addr[0x20];
6023 
6024 	u8         inner_l4_sport[0x10];
6025 	u8         inner_l4_dport[0x10];
6026 
6027 	u8         reserved_at_160[0x1];
6028 	u8         sx_sniffer[0x1];
6029 	u8         functional_lb[0x1];
6030 	u8         inner_ip_frag[0x1];
6031 	u8         inner_qp_type[0x2];
6032 	u8         inner_encap_type[0x2];
6033 	u8         port_number[0x2];
6034 	u8         inner_l3_type[0x2];
6035 	u8         inner_l4_type[0x2];
6036 	u8         inner_first_vlan_type[0x2];
6037 	u8         inner_first_vlan_prio[0x3];
6038 	u8         inner_first_vlan_cfi[0x1];
6039 	u8         inner_first_vlan_vid[0xc];
6040 
6041 	u8         tunnel_header_0[0x20];
6042 
6043 	u8         inner_dmac_47_16[0x20];
6044 
6045 	u8         inner_smac_47_16[0x20];
6046 
6047 	u8         inner_smac_15_0[0x10];
6048 	u8         inner_dmac_15_0[0x10];
6049 };
6050 
6051 struct mlx5_ifc_match_definer_format_29_bits {
6052 	u8         reserved_at_0[0xc0];
6053 
6054 	u8         outer_ip_dest_addr[0x80];
6055 
6056 	u8         outer_ip_src_addr[0x80];
6057 
6058 	u8         outer_l4_sport[0x10];
6059 	u8         outer_l4_dport[0x10];
6060 
6061 	u8         reserved_at_1e0[0x20];
6062 };
6063 
6064 struct mlx5_ifc_match_definer_format_30_bits {
6065 	u8         reserved_at_0[0xa0];
6066 
6067 	u8         outer_ip_dest_addr[0x80];
6068 
6069 	u8         outer_ip_src_addr[0x80];
6070 
6071 	u8         outer_dmac_47_16[0x20];
6072 
6073 	u8         outer_smac_47_16[0x20];
6074 
6075 	u8         outer_smac_15_0[0x10];
6076 	u8         outer_dmac_15_0[0x10];
6077 };
6078 
6079 struct mlx5_ifc_match_definer_format_31_bits {
6080 	u8         reserved_at_0[0xc0];
6081 
6082 	u8         inner_ip_dest_addr[0x80];
6083 
6084 	u8         inner_ip_src_addr[0x80];
6085 
6086 	u8         inner_l4_sport[0x10];
6087 	u8         inner_l4_dport[0x10];
6088 
6089 	u8         reserved_at_1e0[0x20];
6090 };
6091 
6092 struct mlx5_ifc_match_definer_format_32_bits {
6093 	u8         reserved_at_0[0xa0];
6094 
6095 	u8         inner_ip_dest_addr[0x80];
6096 
6097 	u8         inner_ip_src_addr[0x80];
6098 
6099 	u8         inner_dmac_47_16[0x20];
6100 
6101 	u8         inner_smac_47_16[0x20];
6102 
6103 	u8         inner_smac_15_0[0x10];
6104 	u8         inner_dmac_15_0[0x10];
6105 };
6106 
6107 struct mlx5_ifc_match_definer_bits {
6108 	u8         modify_field_select[0x40];
6109 
6110 	u8         reserved_at_40[0x40];
6111 
6112 	u8         reserved_at_80[0x10];
6113 	u8         format_id[0x10];
6114 
6115 	u8         reserved_at_a0[0x160];
6116 
6117 	u8         match_mask[16][0x20];
6118 };
6119 
6120 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6121 	u8         opcode[0x10];
6122 	u8         uid[0x10];
6123 
6124 	u8         vhca_tunnel_id[0x10];
6125 	u8         obj_type[0x10];
6126 
6127 	u8         obj_id[0x20];
6128 
6129 	u8         reserved_at_60[0x3];
6130 	u8         log_obj_range[0x5];
6131 	u8         reserved_at_68[0x18];
6132 };
6133 
6134 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6135 	u8         status[0x8];
6136 	u8         reserved_at_8[0x18];
6137 
6138 	u8         syndrome[0x20];
6139 
6140 	u8         obj_id[0x20];
6141 
6142 	u8         reserved_at_60[0x20];
6143 };
6144 
6145 struct mlx5_ifc_create_match_definer_in_bits {
6146 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6147 
6148 	struct mlx5_ifc_match_definer_bits obj_context;
6149 };
6150 
6151 struct mlx5_ifc_create_match_definer_out_bits {
6152 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6153 };
6154 
6155 enum {
6156 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6157 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6158 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6159 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6160 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6161 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6162 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6163 };
6164 
6165 struct mlx5_ifc_query_flow_group_out_bits {
6166 	u8         status[0x8];
6167 	u8         reserved_at_8[0x18];
6168 
6169 	u8         syndrome[0x20];
6170 
6171 	u8         reserved_at_40[0xa0];
6172 
6173 	u8         start_flow_index[0x20];
6174 
6175 	u8         reserved_at_100[0x20];
6176 
6177 	u8         end_flow_index[0x20];
6178 
6179 	u8         reserved_at_140[0xa0];
6180 
6181 	u8         reserved_at_1e0[0x18];
6182 	u8         match_criteria_enable[0x8];
6183 
6184 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6185 
6186 	u8         reserved_at_1200[0xe00];
6187 };
6188 
6189 struct mlx5_ifc_query_flow_group_in_bits {
6190 	u8         opcode[0x10];
6191 	u8         reserved_at_10[0x10];
6192 
6193 	u8         reserved_at_20[0x10];
6194 	u8         op_mod[0x10];
6195 
6196 	u8         reserved_at_40[0x40];
6197 
6198 	u8         table_type[0x8];
6199 	u8         reserved_at_88[0x18];
6200 
6201 	u8         reserved_at_a0[0x8];
6202 	u8         table_id[0x18];
6203 
6204 	u8         group_id[0x20];
6205 
6206 	u8         reserved_at_e0[0x120];
6207 };
6208 
6209 struct mlx5_ifc_query_flow_counter_out_bits {
6210 	u8         status[0x8];
6211 	u8         reserved_at_8[0x18];
6212 
6213 	u8         syndrome[0x20];
6214 
6215 	u8         reserved_at_40[0x40];
6216 
6217 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6218 };
6219 
6220 struct mlx5_ifc_query_flow_counter_in_bits {
6221 	u8         opcode[0x10];
6222 	u8         reserved_at_10[0x10];
6223 
6224 	u8         reserved_at_20[0x10];
6225 	u8         op_mod[0x10];
6226 
6227 	u8         reserved_at_40[0x80];
6228 
6229 	u8         clear[0x1];
6230 	u8         reserved_at_c1[0xf];
6231 	u8         num_of_counters[0x10];
6232 
6233 	u8         flow_counter_id[0x20];
6234 };
6235 
6236 struct mlx5_ifc_query_esw_vport_context_out_bits {
6237 	u8         status[0x8];
6238 	u8         reserved_at_8[0x18];
6239 
6240 	u8         syndrome[0x20];
6241 
6242 	u8         reserved_at_40[0x40];
6243 
6244 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6245 };
6246 
6247 struct mlx5_ifc_query_esw_vport_context_in_bits {
6248 	u8         opcode[0x10];
6249 	u8         reserved_at_10[0x10];
6250 
6251 	u8         reserved_at_20[0x10];
6252 	u8         op_mod[0x10];
6253 
6254 	u8         other_vport[0x1];
6255 	u8         reserved_at_41[0xf];
6256 	u8         vport_number[0x10];
6257 
6258 	u8         reserved_at_60[0x20];
6259 };
6260 
6261 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6262 	u8         status[0x8];
6263 	u8         reserved_at_8[0x18];
6264 
6265 	u8         syndrome[0x20];
6266 
6267 	u8         reserved_at_40[0x40];
6268 };
6269 
6270 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6271 	u8         reserved_at_0[0x1b];
6272 	u8         fdb_to_vport_reg_c_id[0x1];
6273 	u8         vport_cvlan_insert[0x1];
6274 	u8         vport_svlan_insert[0x1];
6275 	u8         vport_cvlan_strip[0x1];
6276 	u8         vport_svlan_strip[0x1];
6277 };
6278 
6279 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6280 	u8         opcode[0x10];
6281 	u8         reserved_at_10[0x10];
6282 
6283 	u8         reserved_at_20[0x10];
6284 	u8         op_mod[0x10];
6285 
6286 	u8         other_vport[0x1];
6287 	u8         reserved_at_41[0xf];
6288 	u8         vport_number[0x10];
6289 
6290 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6291 
6292 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6293 };
6294 
6295 struct mlx5_ifc_query_eq_out_bits {
6296 	u8         status[0x8];
6297 	u8         reserved_at_8[0x18];
6298 
6299 	u8         syndrome[0x20];
6300 
6301 	u8         reserved_at_40[0x40];
6302 
6303 	struct mlx5_ifc_eqc_bits eq_context_entry;
6304 
6305 	u8         reserved_at_280[0x40];
6306 
6307 	u8         event_bitmask[0x40];
6308 
6309 	u8         reserved_at_300[0x580];
6310 
6311 	u8         pas[][0x40];
6312 };
6313 
6314 struct mlx5_ifc_query_eq_in_bits {
6315 	u8         opcode[0x10];
6316 	u8         reserved_at_10[0x10];
6317 
6318 	u8         reserved_at_20[0x10];
6319 	u8         op_mod[0x10];
6320 
6321 	u8         reserved_at_40[0x18];
6322 	u8         eq_number[0x8];
6323 
6324 	u8         reserved_at_60[0x20];
6325 };
6326 
6327 struct mlx5_ifc_packet_reformat_context_in_bits {
6328 	u8         reformat_type[0x8];
6329 	u8         reserved_at_8[0x4];
6330 	u8         reformat_param_0[0x4];
6331 	u8         reserved_at_10[0x6];
6332 	u8         reformat_data_size[0xa];
6333 
6334 	u8         reformat_param_1[0x8];
6335 	u8         reserved_at_28[0x8];
6336 	u8         reformat_data[2][0x8];
6337 
6338 	u8         more_reformat_data[][0x8];
6339 };
6340 
6341 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6342 	u8         status[0x8];
6343 	u8         reserved_at_8[0x18];
6344 
6345 	u8         syndrome[0x20];
6346 
6347 	u8         reserved_at_40[0xa0];
6348 
6349 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6350 };
6351 
6352 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6353 	u8         opcode[0x10];
6354 	u8         reserved_at_10[0x10];
6355 
6356 	u8         reserved_at_20[0x10];
6357 	u8         op_mod[0x10];
6358 
6359 	u8         packet_reformat_id[0x20];
6360 
6361 	u8         reserved_at_60[0xa0];
6362 };
6363 
6364 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6365 	u8         status[0x8];
6366 	u8         reserved_at_8[0x18];
6367 
6368 	u8         syndrome[0x20];
6369 
6370 	u8         packet_reformat_id[0x20];
6371 
6372 	u8         reserved_at_60[0x20];
6373 };
6374 
6375 enum {
6376 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6377 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6378 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6379 };
6380 
6381 enum mlx5_reformat_ctx_type {
6382 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6383 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6384 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6385 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6386 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6387 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6388 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6389 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6390 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6391 };
6392 
6393 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6394 	u8         opcode[0x10];
6395 	u8         reserved_at_10[0x10];
6396 
6397 	u8         reserved_at_20[0x10];
6398 	u8         op_mod[0x10];
6399 
6400 	u8         reserved_at_40[0xa0];
6401 
6402 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6403 };
6404 
6405 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6406 	u8         status[0x8];
6407 	u8         reserved_at_8[0x18];
6408 
6409 	u8         syndrome[0x20];
6410 
6411 	u8         reserved_at_40[0x40];
6412 };
6413 
6414 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6415 	u8         opcode[0x10];
6416 	u8         reserved_at_10[0x10];
6417 
6418 	u8         reserved_20[0x10];
6419 	u8         op_mod[0x10];
6420 
6421 	u8         packet_reformat_id[0x20];
6422 
6423 	u8         reserved_60[0x20];
6424 };
6425 
6426 struct mlx5_ifc_set_action_in_bits {
6427 	u8         action_type[0x4];
6428 	u8         field[0xc];
6429 	u8         reserved_at_10[0x3];
6430 	u8         offset[0x5];
6431 	u8         reserved_at_18[0x3];
6432 	u8         length[0x5];
6433 
6434 	u8         data[0x20];
6435 };
6436 
6437 struct mlx5_ifc_add_action_in_bits {
6438 	u8         action_type[0x4];
6439 	u8         field[0xc];
6440 	u8         reserved_at_10[0x10];
6441 
6442 	u8         data[0x20];
6443 };
6444 
6445 struct mlx5_ifc_copy_action_in_bits {
6446 	u8         action_type[0x4];
6447 	u8         src_field[0xc];
6448 	u8         reserved_at_10[0x3];
6449 	u8         src_offset[0x5];
6450 	u8         reserved_at_18[0x3];
6451 	u8         length[0x5];
6452 
6453 	u8         reserved_at_20[0x4];
6454 	u8         dst_field[0xc];
6455 	u8         reserved_at_30[0x3];
6456 	u8         dst_offset[0x5];
6457 	u8         reserved_at_38[0x8];
6458 };
6459 
6460 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6461 	struct mlx5_ifc_set_action_in_bits  set_action_in;
6462 	struct mlx5_ifc_add_action_in_bits  add_action_in;
6463 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6464 	u8         reserved_at_0[0x40];
6465 };
6466 
6467 enum {
6468 	MLX5_ACTION_TYPE_SET   = 0x1,
6469 	MLX5_ACTION_TYPE_ADD   = 0x2,
6470 	MLX5_ACTION_TYPE_COPY  = 0x3,
6471 };
6472 
6473 enum {
6474 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6475 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6476 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6477 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6478 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6479 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6480 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6481 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6482 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6483 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6484 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6485 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6486 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6487 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6488 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6489 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6490 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6491 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6492 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6493 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6494 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6495 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6496 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6497 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6498 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6499 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6500 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6501 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6502 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6503 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6504 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6505 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6506 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6507 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6508 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6509 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6510 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6511 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6512 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6513 };
6514 
6515 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6516 	u8         status[0x8];
6517 	u8         reserved_at_8[0x18];
6518 
6519 	u8         syndrome[0x20];
6520 
6521 	u8         modify_header_id[0x20];
6522 
6523 	u8         reserved_at_60[0x20];
6524 };
6525 
6526 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6527 	u8         opcode[0x10];
6528 	u8         reserved_at_10[0x10];
6529 
6530 	u8         reserved_at_20[0x10];
6531 	u8         op_mod[0x10];
6532 
6533 	u8         reserved_at_40[0x20];
6534 
6535 	u8         table_type[0x8];
6536 	u8         reserved_at_68[0x10];
6537 	u8         num_of_actions[0x8];
6538 
6539 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6540 };
6541 
6542 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6543 	u8         status[0x8];
6544 	u8         reserved_at_8[0x18];
6545 
6546 	u8         syndrome[0x20];
6547 
6548 	u8         reserved_at_40[0x40];
6549 };
6550 
6551 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6552 	u8         opcode[0x10];
6553 	u8         reserved_at_10[0x10];
6554 
6555 	u8         reserved_at_20[0x10];
6556 	u8         op_mod[0x10];
6557 
6558 	u8         modify_header_id[0x20];
6559 
6560 	u8         reserved_at_60[0x20];
6561 };
6562 
6563 struct mlx5_ifc_query_modify_header_context_in_bits {
6564 	u8         opcode[0x10];
6565 	u8         uid[0x10];
6566 
6567 	u8         reserved_at_20[0x10];
6568 	u8         op_mod[0x10];
6569 
6570 	u8         modify_header_id[0x20];
6571 
6572 	u8         reserved_at_60[0xa0];
6573 };
6574 
6575 struct mlx5_ifc_query_dct_out_bits {
6576 	u8         status[0x8];
6577 	u8         reserved_at_8[0x18];
6578 
6579 	u8         syndrome[0x20];
6580 
6581 	u8         reserved_at_40[0x40];
6582 
6583 	struct mlx5_ifc_dctc_bits dct_context_entry;
6584 
6585 	u8         reserved_at_280[0x180];
6586 };
6587 
6588 struct mlx5_ifc_query_dct_in_bits {
6589 	u8         opcode[0x10];
6590 	u8         reserved_at_10[0x10];
6591 
6592 	u8         reserved_at_20[0x10];
6593 	u8         op_mod[0x10];
6594 
6595 	u8         reserved_at_40[0x8];
6596 	u8         dctn[0x18];
6597 
6598 	u8         reserved_at_60[0x20];
6599 };
6600 
6601 struct mlx5_ifc_query_cq_out_bits {
6602 	u8         status[0x8];
6603 	u8         reserved_at_8[0x18];
6604 
6605 	u8         syndrome[0x20];
6606 
6607 	u8         reserved_at_40[0x40];
6608 
6609 	struct mlx5_ifc_cqc_bits cq_context;
6610 
6611 	u8         reserved_at_280[0x600];
6612 
6613 	u8         pas[][0x40];
6614 };
6615 
6616 struct mlx5_ifc_query_cq_in_bits {
6617 	u8         opcode[0x10];
6618 	u8         reserved_at_10[0x10];
6619 
6620 	u8         reserved_at_20[0x10];
6621 	u8         op_mod[0x10];
6622 
6623 	u8         reserved_at_40[0x8];
6624 	u8         cqn[0x18];
6625 
6626 	u8         reserved_at_60[0x20];
6627 };
6628 
6629 struct mlx5_ifc_query_cong_status_out_bits {
6630 	u8         status[0x8];
6631 	u8         reserved_at_8[0x18];
6632 
6633 	u8         syndrome[0x20];
6634 
6635 	u8         reserved_at_40[0x20];
6636 
6637 	u8         enable[0x1];
6638 	u8         tag_enable[0x1];
6639 	u8         reserved_at_62[0x1e];
6640 };
6641 
6642 struct mlx5_ifc_query_cong_status_in_bits {
6643 	u8         opcode[0x10];
6644 	u8         reserved_at_10[0x10];
6645 
6646 	u8         reserved_at_20[0x10];
6647 	u8         op_mod[0x10];
6648 
6649 	u8         reserved_at_40[0x18];
6650 	u8         priority[0x4];
6651 	u8         cong_protocol[0x4];
6652 
6653 	u8         reserved_at_60[0x20];
6654 };
6655 
6656 struct mlx5_ifc_query_cong_statistics_out_bits {
6657 	u8         status[0x8];
6658 	u8         reserved_at_8[0x18];
6659 
6660 	u8         syndrome[0x20];
6661 
6662 	u8         reserved_at_40[0x40];
6663 
6664 	u8         rp_cur_flows[0x20];
6665 
6666 	u8         sum_flows[0x20];
6667 
6668 	u8         rp_cnp_ignored_high[0x20];
6669 
6670 	u8         rp_cnp_ignored_low[0x20];
6671 
6672 	u8         rp_cnp_handled_high[0x20];
6673 
6674 	u8         rp_cnp_handled_low[0x20];
6675 
6676 	u8         reserved_at_140[0x100];
6677 
6678 	u8         time_stamp_high[0x20];
6679 
6680 	u8         time_stamp_low[0x20];
6681 
6682 	u8         accumulators_period[0x20];
6683 
6684 	u8         np_ecn_marked_roce_packets_high[0x20];
6685 
6686 	u8         np_ecn_marked_roce_packets_low[0x20];
6687 
6688 	u8         np_cnp_sent_high[0x20];
6689 
6690 	u8         np_cnp_sent_low[0x20];
6691 
6692 	u8         reserved_at_320[0x560];
6693 };
6694 
6695 struct mlx5_ifc_query_cong_statistics_in_bits {
6696 	u8         opcode[0x10];
6697 	u8         reserved_at_10[0x10];
6698 
6699 	u8         reserved_at_20[0x10];
6700 	u8         op_mod[0x10];
6701 
6702 	u8         clear[0x1];
6703 	u8         reserved_at_41[0x1f];
6704 
6705 	u8         reserved_at_60[0x20];
6706 };
6707 
6708 struct mlx5_ifc_query_cong_params_out_bits {
6709 	u8         status[0x8];
6710 	u8         reserved_at_8[0x18];
6711 
6712 	u8         syndrome[0x20];
6713 
6714 	u8         reserved_at_40[0x40];
6715 
6716 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6717 };
6718 
6719 struct mlx5_ifc_query_cong_params_in_bits {
6720 	u8         opcode[0x10];
6721 	u8         reserved_at_10[0x10];
6722 
6723 	u8         reserved_at_20[0x10];
6724 	u8         op_mod[0x10];
6725 
6726 	u8         reserved_at_40[0x1c];
6727 	u8         cong_protocol[0x4];
6728 
6729 	u8         reserved_at_60[0x20];
6730 };
6731 
6732 struct mlx5_ifc_query_adapter_out_bits {
6733 	u8         status[0x8];
6734 	u8         reserved_at_8[0x18];
6735 
6736 	u8         syndrome[0x20];
6737 
6738 	u8         reserved_at_40[0x40];
6739 
6740 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6741 };
6742 
6743 struct mlx5_ifc_query_adapter_in_bits {
6744 	u8         opcode[0x10];
6745 	u8         reserved_at_10[0x10];
6746 
6747 	u8         reserved_at_20[0x10];
6748 	u8         op_mod[0x10];
6749 
6750 	u8         reserved_at_40[0x40];
6751 };
6752 
6753 struct mlx5_ifc_qp_2rst_out_bits {
6754 	u8         status[0x8];
6755 	u8         reserved_at_8[0x18];
6756 
6757 	u8         syndrome[0x20];
6758 
6759 	u8         reserved_at_40[0x40];
6760 };
6761 
6762 struct mlx5_ifc_qp_2rst_in_bits {
6763 	u8         opcode[0x10];
6764 	u8         uid[0x10];
6765 
6766 	u8         reserved_at_20[0x10];
6767 	u8         op_mod[0x10];
6768 
6769 	u8         reserved_at_40[0x8];
6770 	u8         qpn[0x18];
6771 
6772 	u8         reserved_at_60[0x20];
6773 };
6774 
6775 struct mlx5_ifc_qp_2err_out_bits {
6776 	u8         status[0x8];
6777 	u8         reserved_at_8[0x18];
6778 
6779 	u8         syndrome[0x20];
6780 
6781 	u8         reserved_at_40[0x40];
6782 };
6783 
6784 struct mlx5_ifc_qp_2err_in_bits {
6785 	u8         opcode[0x10];
6786 	u8         uid[0x10];
6787 
6788 	u8         reserved_at_20[0x10];
6789 	u8         op_mod[0x10];
6790 
6791 	u8         reserved_at_40[0x8];
6792 	u8         qpn[0x18];
6793 
6794 	u8         reserved_at_60[0x20];
6795 };
6796 
6797 struct mlx5_ifc_page_fault_resume_out_bits {
6798 	u8         status[0x8];
6799 	u8         reserved_at_8[0x18];
6800 
6801 	u8         syndrome[0x20];
6802 
6803 	u8         reserved_at_40[0x40];
6804 };
6805 
6806 struct mlx5_ifc_page_fault_resume_in_bits {
6807 	u8         opcode[0x10];
6808 	u8         reserved_at_10[0x10];
6809 
6810 	u8         reserved_at_20[0x10];
6811 	u8         op_mod[0x10];
6812 
6813 	u8         error[0x1];
6814 	u8         reserved_at_41[0x4];
6815 	u8         page_fault_type[0x3];
6816 	u8         wq_number[0x18];
6817 
6818 	u8         reserved_at_60[0x8];
6819 	u8         token[0x18];
6820 };
6821 
6822 struct mlx5_ifc_nop_out_bits {
6823 	u8         status[0x8];
6824 	u8         reserved_at_8[0x18];
6825 
6826 	u8         syndrome[0x20];
6827 
6828 	u8         reserved_at_40[0x40];
6829 };
6830 
6831 struct mlx5_ifc_nop_in_bits {
6832 	u8         opcode[0x10];
6833 	u8         reserved_at_10[0x10];
6834 
6835 	u8         reserved_at_20[0x10];
6836 	u8         op_mod[0x10];
6837 
6838 	u8         reserved_at_40[0x40];
6839 };
6840 
6841 struct mlx5_ifc_modify_vport_state_out_bits {
6842 	u8         status[0x8];
6843 	u8         reserved_at_8[0x18];
6844 
6845 	u8         syndrome[0x20];
6846 
6847 	u8         reserved_at_40[0x40];
6848 };
6849 
6850 struct mlx5_ifc_modify_vport_state_in_bits {
6851 	u8         opcode[0x10];
6852 	u8         reserved_at_10[0x10];
6853 
6854 	u8         reserved_at_20[0x10];
6855 	u8         op_mod[0x10];
6856 
6857 	u8         other_vport[0x1];
6858 	u8         reserved_at_41[0xf];
6859 	u8         vport_number[0x10];
6860 
6861 	u8         reserved_at_60[0x18];
6862 	u8         admin_state[0x4];
6863 	u8         reserved_at_7c[0x4];
6864 };
6865 
6866 struct mlx5_ifc_modify_tis_out_bits {
6867 	u8         status[0x8];
6868 	u8         reserved_at_8[0x18];
6869 
6870 	u8         syndrome[0x20];
6871 
6872 	u8         reserved_at_40[0x40];
6873 };
6874 
6875 struct mlx5_ifc_modify_tis_bitmask_bits {
6876 	u8         reserved_at_0[0x20];
6877 
6878 	u8         reserved_at_20[0x1d];
6879 	u8         lag_tx_port_affinity[0x1];
6880 	u8         strict_lag_tx_port_affinity[0x1];
6881 	u8         prio[0x1];
6882 };
6883 
6884 struct mlx5_ifc_modify_tis_in_bits {
6885 	u8         opcode[0x10];
6886 	u8         uid[0x10];
6887 
6888 	u8         reserved_at_20[0x10];
6889 	u8         op_mod[0x10];
6890 
6891 	u8         reserved_at_40[0x8];
6892 	u8         tisn[0x18];
6893 
6894 	u8         reserved_at_60[0x20];
6895 
6896 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6897 
6898 	u8         reserved_at_c0[0x40];
6899 
6900 	struct mlx5_ifc_tisc_bits ctx;
6901 };
6902 
6903 struct mlx5_ifc_modify_tir_bitmask_bits {
6904 	u8	   reserved_at_0[0x20];
6905 
6906 	u8         reserved_at_20[0x1b];
6907 	u8         self_lb_en[0x1];
6908 	u8         reserved_at_3c[0x1];
6909 	u8         hash[0x1];
6910 	u8         reserved_at_3e[0x1];
6911 	u8         packet_merge[0x1];
6912 };
6913 
6914 struct mlx5_ifc_modify_tir_out_bits {
6915 	u8         status[0x8];
6916 	u8         reserved_at_8[0x18];
6917 
6918 	u8         syndrome[0x20];
6919 
6920 	u8         reserved_at_40[0x40];
6921 };
6922 
6923 struct mlx5_ifc_modify_tir_in_bits {
6924 	u8         opcode[0x10];
6925 	u8         uid[0x10];
6926 
6927 	u8         reserved_at_20[0x10];
6928 	u8         op_mod[0x10];
6929 
6930 	u8         reserved_at_40[0x8];
6931 	u8         tirn[0x18];
6932 
6933 	u8         reserved_at_60[0x20];
6934 
6935 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6936 
6937 	u8         reserved_at_c0[0x40];
6938 
6939 	struct mlx5_ifc_tirc_bits ctx;
6940 };
6941 
6942 struct mlx5_ifc_modify_sq_out_bits {
6943 	u8         status[0x8];
6944 	u8         reserved_at_8[0x18];
6945 
6946 	u8         syndrome[0x20];
6947 
6948 	u8         reserved_at_40[0x40];
6949 };
6950 
6951 struct mlx5_ifc_modify_sq_in_bits {
6952 	u8         opcode[0x10];
6953 	u8         uid[0x10];
6954 
6955 	u8         reserved_at_20[0x10];
6956 	u8         op_mod[0x10];
6957 
6958 	u8         sq_state[0x4];
6959 	u8         reserved_at_44[0x4];
6960 	u8         sqn[0x18];
6961 
6962 	u8         reserved_at_60[0x20];
6963 
6964 	u8         modify_bitmask[0x40];
6965 
6966 	u8         reserved_at_c0[0x40];
6967 
6968 	struct mlx5_ifc_sqc_bits ctx;
6969 };
6970 
6971 struct mlx5_ifc_modify_scheduling_element_out_bits {
6972 	u8         status[0x8];
6973 	u8         reserved_at_8[0x18];
6974 
6975 	u8         syndrome[0x20];
6976 
6977 	u8         reserved_at_40[0x1c0];
6978 };
6979 
6980 enum {
6981 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6982 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6983 };
6984 
6985 struct mlx5_ifc_modify_scheduling_element_in_bits {
6986 	u8         opcode[0x10];
6987 	u8         reserved_at_10[0x10];
6988 
6989 	u8         reserved_at_20[0x10];
6990 	u8         op_mod[0x10];
6991 
6992 	u8         scheduling_hierarchy[0x8];
6993 	u8         reserved_at_48[0x18];
6994 
6995 	u8         scheduling_element_id[0x20];
6996 
6997 	u8         reserved_at_80[0x20];
6998 
6999 	u8         modify_bitmask[0x20];
7000 
7001 	u8         reserved_at_c0[0x40];
7002 
7003 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7004 
7005 	u8         reserved_at_300[0x100];
7006 };
7007 
7008 struct mlx5_ifc_modify_rqt_out_bits {
7009 	u8         status[0x8];
7010 	u8         reserved_at_8[0x18];
7011 
7012 	u8         syndrome[0x20];
7013 
7014 	u8         reserved_at_40[0x40];
7015 };
7016 
7017 struct mlx5_ifc_rqt_bitmask_bits {
7018 	u8	   reserved_at_0[0x20];
7019 
7020 	u8         reserved_at_20[0x1f];
7021 	u8         rqn_list[0x1];
7022 };
7023 
7024 struct mlx5_ifc_modify_rqt_in_bits {
7025 	u8         opcode[0x10];
7026 	u8         uid[0x10];
7027 
7028 	u8         reserved_at_20[0x10];
7029 	u8         op_mod[0x10];
7030 
7031 	u8         reserved_at_40[0x8];
7032 	u8         rqtn[0x18];
7033 
7034 	u8         reserved_at_60[0x20];
7035 
7036 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7037 
7038 	u8         reserved_at_c0[0x40];
7039 
7040 	struct mlx5_ifc_rqtc_bits ctx;
7041 };
7042 
7043 struct mlx5_ifc_modify_rq_out_bits {
7044 	u8         status[0x8];
7045 	u8         reserved_at_8[0x18];
7046 
7047 	u8         syndrome[0x20];
7048 
7049 	u8         reserved_at_40[0x40];
7050 };
7051 
7052 enum {
7053 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7054 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7055 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7056 };
7057 
7058 struct mlx5_ifc_modify_rq_in_bits {
7059 	u8         opcode[0x10];
7060 	u8         uid[0x10];
7061 
7062 	u8         reserved_at_20[0x10];
7063 	u8         op_mod[0x10];
7064 
7065 	u8         rq_state[0x4];
7066 	u8         reserved_at_44[0x4];
7067 	u8         rqn[0x18];
7068 
7069 	u8         reserved_at_60[0x20];
7070 
7071 	u8         modify_bitmask[0x40];
7072 
7073 	u8         reserved_at_c0[0x40];
7074 
7075 	struct mlx5_ifc_rqc_bits ctx;
7076 };
7077 
7078 struct mlx5_ifc_modify_rmp_out_bits {
7079 	u8         status[0x8];
7080 	u8         reserved_at_8[0x18];
7081 
7082 	u8         syndrome[0x20];
7083 
7084 	u8         reserved_at_40[0x40];
7085 };
7086 
7087 struct mlx5_ifc_rmp_bitmask_bits {
7088 	u8	   reserved_at_0[0x20];
7089 
7090 	u8         reserved_at_20[0x1f];
7091 	u8         lwm[0x1];
7092 };
7093 
7094 struct mlx5_ifc_modify_rmp_in_bits {
7095 	u8         opcode[0x10];
7096 	u8         uid[0x10];
7097 
7098 	u8         reserved_at_20[0x10];
7099 	u8         op_mod[0x10];
7100 
7101 	u8         rmp_state[0x4];
7102 	u8         reserved_at_44[0x4];
7103 	u8         rmpn[0x18];
7104 
7105 	u8         reserved_at_60[0x20];
7106 
7107 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7108 
7109 	u8         reserved_at_c0[0x40];
7110 
7111 	struct mlx5_ifc_rmpc_bits ctx;
7112 };
7113 
7114 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7115 	u8         status[0x8];
7116 	u8         reserved_at_8[0x18];
7117 
7118 	u8         syndrome[0x20];
7119 
7120 	u8         reserved_at_40[0x40];
7121 };
7122 
7123 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7124 	u8         reserved_at_0[0x12];
7125 	u8	   affiliation[0x1];
7126 	u8	   reserved_at_13[0x1];
7127 	u8         disable_uc_local_lb[0x1];
7128 	u8         disable_mc_local_lb[0x1];
7129 	u8         node_guid[0x1];
7130 	u8         port_guid[0x1];
7131 	u8         min_inline[0x1];
7132 	u8         mtu[0x1];
7133 	u8         change_event[0x1];
7134 	u8         promisc[0x1];
7135 	u8         permanent_address[0x1];
7136 	u8         addresses_list[0x1];
7137 	u8         roce_en[0x1];
7138 	u8         reserved_at_1f[0x1];
7139 };
7140 
7141 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7142 	u8         opcode[0x10];
7143 	u8         reserved_at_10[0x10];
7144 
7145 	u8         reserved_at_20[0x10];
7146 	u8         op_mod[0x10];
7147 
7148 	u8         other_vport[0x1];
7149 	u8         reserved_at_41[0xf];
7150 	u8         vport_number[0x10];
7151 
7152 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7153 
7154 	u8         reserved_at_80[0x780];
7155 
7156 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7157 };
7158 
7159 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7160 	u8         status[0x8];
7161 	u8         reserved_at_8[0x18];
7162 
7163 	u8         syndrome[0x20];
7164 
7165 	u8         reserved_at_40[0x40];
7166 };
7167 
7168 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7169 	u8         opcode[0x10];
7170 	u8         reserved_at_10[0x10];
7171 
7172 	u8         reserved_at_20[0x10];
7173 	u8         op_mod[0x10];
7174 
7175 	u8         other_vport[0x1];
7176 	u8         reserved_at_41[0xb];
7177 	u8         port_num[0x4];
7178 	u8         vport_number[0x10];
7179 
7180 	u8         reserved_at_60[0x20];
7181 
7182 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7183 };
7184 
7185 struct mlx5_ifc_modify_cq_out_bits {
7186 	u8         status[0x8];
7187 	u8         reserved_at_8[0x18];
7188 
7189 	u8         syndrome[0x20];
7190 
7191 	u8         reserved_at_40[0x40];
7192 };
7193 
7194 enum {
7195 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7196 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7197 };
7198 
7199 struct mlx5_ifc_modify_cq_in_bits {
7200 	u8         opcode[0x10];
7201 	u8         uid[0x10];
7202 
7203 	u8         reserved_at_20[0x10];
7204 	u8         op_mod[0x10];
7205 
7206 	u8         reserved_at_40[0x8];
7207 	u8         cqn[0x18];
7208 
7209 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7210 
7211 	struct mlx5_ifc_cqc_bits cq_context;
7212 
7213 	u8         reserved_at_280[0x60];
7214 
7215 	u8         cq_umem_valid[0x1];
7216 	u8         reserved_at_2e1[0x1f];
7217 
7218 	u8         reserved_at_300[0x580];
7219 
7220 	u8         pas[][0x40];
7221 };
7222 
7223 struct mlx5_ifc_modify_cong_status_out_bits {
7224 	u8         status[0x8];
7225 	u8         reserved_at_8[0x18];
7226 
7227 	u8         syndrome[0x20];
7228 
7229 	u8         reserved_at_40[0x40];
7230 };
7231 
7232 struct mlx5_ifc_modify_cong_status_in_bits {
7233 	u8         opcode[0x10];
7234 	u8         reserved_at_10[0x10];
7235 
7236 	u8         reserved_at_20[0x10];
7237 	u8         op_mod[0x10];
7238 
7239 	u8         reserved_at_40[0x18];
7240 	u8         priority[0x4];
7241 	u8         cong_protocol[0x4];
7242 
7243 	u8         enable[0x1];
7244 	u8         tag_enable[0x1];
7245 	u8         reserved_at_62[0x1e];
7246 };
7247 
7248 struct mlx5_ifc_modify_cong_params_out_bits {
7249 	u8         status[0x8];
7250 	u8         reserved_at_8[0x18];
7251 
7252 	u8         syndrome[0x20];
7253 
7254 	u8         reserved_at_40[0x40];
7255 };
7256 
7257 struct mlx5_ifc_modify_cong_params_in_bits {
7258 	u8         opcode[0x10];
7259 	u8         reserved_at_10[0x10];
7260 
7261 	u8         reserved_at_20[0x10];
7262 	u8         op_mod[0x10];
7263 
7264 	u8         reserved_at_40[0x1c];
7265 	u8         cong_protocol[0x4];
7266 
7267 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7268 
7269 	u8         reserved_at_80[0x80];
7270 
7271 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7272 };
7273 
7274 struct mlx5_ifc_manage_pages_out_bits {
7275 	u8         status[0x8];
7276 	u8         reserved_at_8[0x18];
7277 
7278 	u8         syndrome[0x20];
7279 
7280 	u8         output_num_entries[0x20];
7281 
7282 	u8         reserved_at_60[0x20];
7283 
7284 	u8         pas[][0x40];
7285 };
7286 
7287 enum {
7288 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7289 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7290 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7291 };
7292 
7293 struct mlx5_ifc_manage_pages_in_bits {
7294 	u8         opcode[0x10];
7295 	u8         reserved_at_10[0x10];
7296 
7297 	u8         reserved_at_20[0x10];
7298 	u8         op_mod[0x10];
7299 
7300 	u8         embedded_cpu_function[0x1];
7301 	u8         reserved_at_41[0xf];
7302 	u8         function_id[0x10];
7303 
7304 	u8         input_num_entries[0x20];
7305 
7306 	u8         pas[][0x40];
7307 };
7308 
7309 struct mlx5_ifc_mad_ifc_out_bits {
7310 	u8         status[0x8];
7311 	u8         reserved_at_8[0x18];
7312 
7313 	u8         syndrome[0x20];
7314 
7315 	u8         reserved_at_40[0x40];
7316 
7317 	u8         response_mad_packet[256][0x8];
7318 };
7319 
7320 struct mlx5_ifc_mad_ifc_in_bits {
7321 	u8         opcode[0x10];
7322 	u8         reserved_at_10[0x10];
7323 
7324 	u8         reserved_at_20[0x10];
7325 	u8         op_mod[0x10];
7326 
7327 	u8         remote_lid[0x10];
7328 	u8         reserved_at_50[0x8];
7329 	u8         port[0x8];
7330 
7331 	u8         reserved_at_60[0x20];
7332 
7333 	u8         mad[256][0x8];
7334 };
7335 
7336 struct mlx5_ifc_init_hca_out_bits {
7337 	u8         status[0x8];
7338 	u8         reserved_at_8[0x18];
7339 
7340 	u8         syndrome[0x20];
7341 
7342 	u8         reserved_at_40[0x40];
7343 };
7344 
7345 struct mlx5_ifc_init_hca_in_bits {
7346 	u8         opcode[0x10];
7347 	u8         reserved_at_10[0x10];
7348 
7349 	u8         reserved_at_20[0x10];
7350 	u8         op_mod[0x10];
7351 
7352 	u8         reserved_at_40[0x20];
7353 
7354 	u8         reserved_at_60[0x2];
7355 	u8         sw_vhca_id[0xe];
7356 	u8         reserved_at_70[0x10];
7357 
7358 	u8	   sw_owner_id[4][0x20];
7359 };
7360 
7361 struct mlx5_ifc_init2rtr_qp_out_bits {
7362 	u8         status[0x8];
7363 	u8         reserved_at_8[0x18];
7364 
7365 	u8         syndrome[0x20];
7366 
7367 	u8         reserved_at_40[0x20];
7368 	u8         ece[0x20];
7369 };
7370 
7371 struct mlx5_ifc_init2rtr_qp_in_bits {
7372 	u8         opcode[0x10];
7373 	u8         uid[0x10];
7374 
7375 	u8         reserved_at_20[0x10];
7376 	u8         op_mod[0x10];
7377 
7378 	u8         reserved_at_40[0x8];
7379 	u8         qpn[0x18];
7380 
7381 	u8         reserved_at_60[0x20];
7382 
7383 	u8         opt_param_mask[0x20];
7384 
7385 	u8         ece[0x20];
7386 
7387 	struct mlx5_ifc_qpc_bits qpc;
7388 
7389 	u8         reserved_at_800[0x80];
7390 };
7391 
7392 struct mlx5_ifc_init2init_qp_out_bits {
7393 	u8         status[0x8];
7394 	u8         reserved_at_8[0x18];
7395 
7396 	u8         syndrome[0x20];
7397 
7398 	u8         reserved_at_40[0x20];
7399 	u8         ece[0x20];
7400 };
7401 
7402 struct mlx5_ifc_init2init_qp_in_bits {
7403 	u8         opcode[0x10];
7404 	u8         uid[0x10];
7405 
7406 	u8         reserved_at_20[0x10];
7407 	u8         op_mod[0x10];
7408 
7409 	u8         reserved_at_40[0x8];
7410 	u8         qpn[0x18];
7411 
7412 	u8         reserved_at_60[0x20];
7413 
7414 	u8         opt_param_mask[0x20];
7415 
7416 	u8         ece[0x20];
7417 
7418 	struct mlx5_ifc_qpc_bits qpc;
7419 
7420 	u8         reserved_at_800[0x80];
7421 };
7422 
7423 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7424 	u8         status[0x8];
7425 	u8         reserved_at_8[0x18];
7426 
7427 	u8         syndrome[0x20];
7428 
7429 	u8         reserved_at_40[0x40];
7430 
7431 	u8         packet_headers_log[128][0x8];
7432 
7433 	u8         packet_syndrome[64][0x8];
7434 };
7435 
7436 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7437 	u8         opcode[0x10];
7438 	u8         reserved_at_10[0x10];
7439 
7440 	u8         reserved_at_20[0x10];
7441 	u8         op_mod[0x10];
7442 
7443 	u8         reserved_at_40[0x40];
7444 };
7445 
7446 struct mlx5_ifc_gen_eqe_in_bits {
7447 	u8         opcode[0x10];
7448 	u8         reserved_at_10[0x10];
7449 
7450 	u8         reserved_at_20[0x10];
7451 	u8         op_mod[0x10];
7452 
7453 	u8         reserved_at_40[0x18];
7454 	u8         eq_number[0x8];
7455 
7456 	u8         reserved_at_60[0x20];
7457 
7458 	u8         eqe[64][0x8];
7459 };
7460 
7461 struct mlx5_ifc_gen_eq_out_bits {
7462 	u8         status[0x8];
7463 	u8         reserved_at_8[0x18];
7464 
7465 	u8         syndrome[0x20];
7466 
7467 	u8         reserved_at_40[0x40];
7468 };
7469 
7470 struct mlx5_ifc_enable_hca_out_bits {
7471 	u8         status[0x8];
7472 	u8         reserved_at_8[0x18];
7473 
7474 	u8         syndrome[0x20];
7475 
7476 	u8         reserved_at_40[0x20];
7477 };
7478 
7479 struct mlx5_ifc_enable_hca_in_bits {
7480 	u8         opcode[0x10];
7481 	u8         reserved_at_10[0x10];
7482 
7483 	u8         reserved_at_20[0x10];
7484 	u8         op_mod[0x10];
7485 
7486 	u8         embedded_cpu_function[0x1];
7487 	u8         reserved_at_41[0xf];
7488 	u8         function_id[0x10];
7489 
7490 	u8         reserved_at_60[0x20];
7491 };
7492 
7493 struct mlx5_ifc_drain_dct_out_bits {
7494 	u8         status[0x8];
7495 	u8         reserved_at_8[0x18];
7496 
7497 	u8         syndrome[0x20];
7498 
7499 	u8         reserved_at_40[0x40];
7500 };
7501 
7502 struct mlx5_ifc_drain_dct_in_bits {
7503 	u8         opcode[0x10];
7504 	u8         uid[0x10];
7505 
7506 	u8         reserved_at_20[0x10];
7507 	u8         op_mod[0x10];
7508 
7509 	u8         reserved_at_40[0x8];
7510 	u8         dctn[0x18];
7511 
7512 	u8         reserved_at_60[0x20];
7513 };
7514 
7515 struct mlx5_ifc_disable_hca_out_bits {
7516 	u8         status[0x8];
7517 	u8         reserved_at_8[0x18];
7518 
7519 	u8         syndrome[0x20];
7520 
7521 	u8         reserved_at_40[0x20];
7522 };
7523 
7524 struct mlx5_ifc_disable_hca_in_bits {
7525 	u8         opcode[0x10];
7526 	u8         reserved_at_10[0x10];
7527 
7528 	u8         reserved_at_20[0x10];
7529 	u8         op_mod[0x10];
7530 
7531 	u8         embedded_cpu_function[0x1];
7532 	u8         reserved_at_41[0xf];
7533 	u8         function_id[0x10];
7534 
7535 	u8         reserved_at_60[0x20];
7536 };
7537 
7538 struct mlx5_ifc_detach_from_mcg_out_bits {
7539 	u8         status[0x8];
7540 	u8         reserved_at_8[0x18];
7541 
7542 	u8         syndrome[0x20];
7543 
7544 	u8         reserved_at_40[0x40];
7545 };
7546 
7547 struct mlx5_ifc_detach_from_mcg_in_bits {
7548 	u8         opcode[0x10];
7549 	u8         uid[0x10];
7550 
7551 	u8         reserved_at_20[0x10];
7552 	u8         op_mod[0x10];
7553 
7554 	u8         reserved_at_40[0x8];
7555 	u8         qpn[0x18];
7556 
7557 	u8         reserved_at_60[0x20];
7558 
7559 	u8         multicast_gid[16][0x8];
7560 };
7561 
7562 struct mlx5_ifc_destroy_xrq_out_bits {
7563 	u8         status[0x8];
7564 	u8         reserved_at_8[0x18];
7565 
7566 	u8         syndrome[0x20];
7567 
7568 	u8         reserved_at_40[0x40];
7569 };
7570 
7571 struct mlx5_ifc_destroy_xrq_in_bits {
7572 	u8         opcode[0x10];
7573 	u8         uid[0x10];
7574 
7575 	u8         reserved_at_20[0x10];
7576 	u8         op_mod[0x10];
7577 
7578 	u8         reserved_at_40[0x8];
7579 	u8         xrqn[0x18];
7580 
7581 	u8         reserved_at_60[0x20];
7582 };
7583 
7584 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7585 	u8         status[0x8];
7586 	u8         reserved_at_8[0x18];
7587 
7588 	u8         syndrome[0x20];
7589 
7590 	u8         reserved_at_40[0x40];
7591 };
7592 
7593 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7594 	u8         opcode[0x10];
7595 	u8         uid[0x10];
7596 
7597 	u8         reserved_at_20[0x10];
7598 	u8         op_mod[0x10];
7599 
7600 	u8         reserved_at_40[0x8];
7601 	u8         xrc_srqn[0x18];
7602 
7603 	u8         reserved_at_60[0x20];
7604 };
7605 
7606 struct mlx5_ifc_destroy_tis_out_bits {
7607 	u8         status[0x8];
7608 	u8         reserved_at_8[0x18];
7609 
7610 	u8         syndrome[0x20];
7611 
7612 	u8         reserved_at_40[0x40];
7613 };
7614 
7615 struct mlx5_ifc_destroy_tis_in_bits {
7616 	u8         opcode[0x10];
7617 	u8         uid[0x10];
7618 
7619 	u8         reserved_at_20[0x10];
7620 	u8         op_mod[0x10];
7621 
7622 	u8         reserved_at_40[0x8];
7623 	u8         tisn[0x18];
7624 
7625 	u8         reserved_at_60[0x20];
7626 };
7627 
7628 struct mlx5_ifc_destroy_tir_out_bits {
7629 	u8         status[0x8];
7630 	u8         reserved_at_8[0x18];
7631 
7632 	u8         syndrome[0x20];
7633 
7634 	u8         reserved_at_40[0x40];
7635 };
7636 
7637 struct mlx5_ifc_destroy_tir_in_bits {
7638 	u8         opcode[0x10];
7639 	u8         uid[0x10];
7640 
7641 	u8         reserved_at_20[0x10];
7642 	u8         op_mod[0x10];
7643 
7644 	u8         reserved_at_40[0x8];
7645 	u8         tirn[0x18];
7646 
7647 	u8         reserved_at_60[0x20];
7648 };
7649 
7650 struct mlx5_ifc_destroy_srq_out_bits {
7651 	u8         status[0x8];
7652 	u8         reserved_at_8[0x18];
7653 
7654 	u8         syndrome[0x20];
7655 
7656 	u8         reserved_at_40[0x40];
7657 };
7658 
7659 struct mlx5_ifc_destroy_srq_in_bits {
7660 	u8         opcode[0x10];
7661 	u8         uid[0x10];
7662 
7663 	u8         reserved_at_20[0x10];
7664 	u8         op_mod[0x10];
7665 
7666 	u8         reserved_at_40[0x8];
7667 	u8         srqn[0x18];
7668 
7669 	u8         reserved_at_60[0x20];
7670 };
7671 
7672 struct mlx5_ifc_destroy_sq_out_bits {
7673 	u8         status[0x8];
7674 	u8         reserved_at_8[0x18];
7675 
7676 	u8         syndrome[0x20];
7677 
7678 	u8         reserved_at_40[0x40];
7679 };
7680 
7681 struct mlx5_ifc_destroy_sq_in_bits {
7682 	u8         opcode[0x10];
7683 	u8         uid[0x10];
7684 
7685 	u8         reserved_at_20[0x10];
7686 	u8         op_mod[0x10];
7687 
7688 	u8         reserved_at_40[0x8];
7689 	u8         sqn[0x18];
7690 
7691 	u8         reserved_at_60[0x20];
7692 };
7693 
7694 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7695 	u8         status[0x8];
7696 	u8         reserved_at_8[0x18];
7697 
7698 	u8         syndrome[0x20];
7699 
7700 	u8         reserved_at_40[0x1c0];
7701 };
7702 
7703 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7704 	u8         opcode[0x10];
7705 	u8         reserved_at_10[0x10];
7706 
7707 	u8         reserved_at_20[0x10];
7708 	u8         op_mod[0x10];
7709 
7710 	u8         scheduling_hierarchy[0x8];
7711 	u8         reserved_at_48[0x18];
7712 
7713 	u8         scheduling_element_id[0x20];
7714 
7715 	u8         reserved_at_80[0x180];
7716 };
7717 
7718 struct mlx5_ifc_destroy_rqt_out_bits {
7719 	u8         status[0x8];
7720 	u8         reserved_at_8[0x18];
7721 
7722 	u8         syndrome[0x20];
7723 
7724 	u8         reserved_at_40[0x40];
7725 };
7726 
7727 struct mlx5_ifc_destroy_rqt_in_bits {
7728 	u8         opcode[0x10];
7729 	u8         uid[0x10];
7730 
7731 	u8         reserved_at_20[0x10];
7732 	u8         op_mod[0x10];
7733 
7734 	u8         reserved_at_40[0x8];
7735 	u8         rqtn[0x18];
7736 
7737 	u8         reserved_at_60[0x20];
7738 };
7739 
7740 struct mlx5_ifc_destroy_rq_out_bits {
7741 	u8         status[0x8];
7742 	u8         reserved_at_8[0x18];
7743 
7744 	u8         syndrome[0x20];
7745 
7746 	u8         reserved_at_40[0x40];
7747 };
7748 
7749 struct mlx5_ifc_destroy_rq_in_bits {
7750 	u8         opcode[0x10];
7751 	u8         uid[0x10];
7752 
7753 	u8         reserved_at_20[0x10];
7754 	u8         op_mod[0x10];
7755 
7756 	u8         reserved_at_40[0x8];
7757 	u8         rqn[0x18];
7758 
7759 	u8         reserved_at_60[0x20];
7760 };
7761 
7762 struct mlx5_ifc_set_delay_drop_params_in_bits {
7763 	u8         opcode[0x10];
7764 	u8         reserved_at_10[0x10];
7765 
7766 	u8         reserved_at_20[0x10];
7767 	u8         op_mod[0x10];
7768 
7769 	u8         reserved_at_40[0x20];
7770 
7771 	u8         reserved_at_60[0x10];
7772 	u8         delay_drop_timeout[0x10];
7773 };
7774 
7775 struct mlx5_ifc_set_delay_drop_params_out_bits {
7776 	u8         status[0x8];
7777 	u8         reserved_at_8[0x18];
7778 
7779 	u8         syndrome[0x20];
7780 
7781 	u8         reserved_at_40[0x40];
7782 };
7783 
7784 struct mlx5_ifc_destroy_rmp_out_bits {
7785 	u8         status[0x8];
7786 	u8         reserved_at_8[0x18];
7787 
7788 	u8         syndrome[0x20];
7789 
7790 	u8         reserved_at_40[0x40];
7791 };
7792 
7793 struct mlx5_ifc_destroy_rmp_in_bits {
7794 	u8         opcode[0x10];
7795 	u8         uid[0x10];
7796 
7797 	u8         reserved_at_20[0x10];
7798 	u8         op_mod[0x10];
7799 
7800 	u8         reserved_at_40[0x8];
7801 	u8         rmpn[0x18];
7802 
7803 	u8         reserved_at_60[0x20];
7804 };
7805 
7806 struct mlx5_ifc_destroy_qp_out_bits {
7807 	u8         status[0x8];
7808 	u8         reserved_at_8[0x18];
7809 
7810 	u8         syndrome[0x20];
7811 
7812 	u8         reserved_at_40[0x40];
7813 };
7814 
7815 struct mlx5_ifc_destroy_qp_in_bits {
7816 	u8         opcode[0x10];
7817 	u8         uid[0x10];
7818 
7819 	u8         reserved_at_20[0x10];
7820 	u8         op_mod[0x10];
7821 
7822 	u8         reserved_at_40[0x8];
7823 	u8         qpn[0x18];
7824 
7825 	u8         reserved_at_60[0x20];
7826 };
7827 
7828 struct mlx5_ifc_destroy_psv_out_bits {
7829 	u8         status[0x8];
7830 	u8         reserved_at_8[0x18];
7831 
7832 	u8         syndrome[0x20];
7833 
7834 	u8         reserved_at_40[0x40];
7835 };
7836 
7837 struct mlx5_ifc_destroy_psv_in_bits {
7838 	u8         opcode[0x10];
7839 	u8         reserved_at_10[0x10];
7840 
7841 	u8         reserved_at_20[0x10];
7842 	u8         op_mod[0x10];
7843 
7844 	u8         reserved_at_40[0x8];
7845 	u8         psvn[0x18];
7846 
7847 	u8         reserved_at_60[0x20];
7848 };
7849 
7850 struct mlx5_ifc_destroy_mkey_out_bits {
7851 	u8         status[0x8];
7852 	u8         reserved_at_8[0x18];
7853 
7854 	u8         syndrome[0x20];
7855 
7856 	u8         reserved_at_40[0x40];
7857 };
7858 
7859 struct mlx5_ifc_destroy_mkey_in_bits {
7860 	u8         opcode[0x10];
7861 	u8         uid[0x10];
7862 
7863 	u8         reserved_at_20[0x10];
7864 	u8         op_mod[0x10];
7865 
7866 	u8         reserved_at_40[0x8];
7867 	u8         mkey_index[0x18];
7868 
7869 	u8         reserved_at_60[0x20];
7870 };
7871 
7872 struct mlx5_ifc_destroy_flow_table_out_bits {
7873 	u8         status[0x8];
7874 	u8         reserved_at_8[0x18];
7875 
7876 	u8         syndrome[0x20];
7877 
7878 	u8         reserved_at_40[0x40];
7879 };
7880 
7881 struct mlx5_ifc_destroy_flow_table_in_bits {
7882 	u8         opcode[0x10];
7883 	u8         reserved_at_10[0x10];
7884 
7885 	u8         reserved_at_20[0x10];
7886 	u8         op_mod[0x10];
7887 
7888 	u8         other_vport[0x1];
7889 	u8         reserved_at_41[0xf];
7890 	u8         vport_number[0x10];
7891 
7892 	u8         reserved_at_60[0x20];
7893 
7894 	u8         table_type[0x8];
7895 	u8         reserved_at_88[0x18];
7896 
7897 	u8         reserved_at_a0[0x8];
7898 	u8         table_id[0x18];
7899 
7900 	u8         reserved_at_c0[0x140];
7901 };
7902 
7903 struct mlx5_ifc_destroy_flow_group_out_bits {
7904 	u8         status[0x8];
7905 	u8         reserved_at_8[0x18];
7906 
7907 	u8         syndrome[0x20];
7908 
7909 	u8         reserved_at_40[0x40];
7910 };
7911 
7912 struct mlx5_ifc_destroy_flow_group_in_bits {
7913 	u8         opcode[0x10];
7914 	u8         reserved_at_10[0x10];
7915 
7916 	u8         reserved_at_20[0x10];
7917 	u8         op_mod[0x10];
7918 
7919 	u8         other_vport[0x1];
7920 	u8         reserved_at_41[0xf];
7921 	u8         vport_number[0x10];
7922 
7923 	u8         reserved_at_60[0x20];
7924 
7925 	u8         table_type[0x8];
7926 	u8         reserved_at_88[0x18];
7927 
7928 	u8         reserved_at_a0[0x8];
7929 	u8         table_id[0x18];
7930 
7931 	u8         group_id[0x20];
7932 
7933 	u8         reserved_at_e0[0x120];
7934 };
7935 
7936 struct mlx5_ifc_destroy_eq_out_bits {
7937 	u8         status[0x8];
7938 	u8         reserved_at_8[0x18];
7939 
7940 	u8         syndrome[0x20];
7941 
7942 	u8         reserved_at_40[0x40];
7943 };
7944 
7945 struct mlx5_ifc_destroy_eq_in_bits {
7946 	u8         opcode[0x10];
7947 	u8         reserved_at_10[0x10];
7948 
7949 	u8         reserved_at_20[0x10];
7950 	u8         op_mod[0x10];
7951 
7952 	u8         reserved_at_40[0x18];
7953 	u8         eq_number[0x8];
7954 
7955 	u8         reserved_at_60[0x20];
7956 };
7957 
7958 struct mlx5_ifc_destroy_dct_out_bits {
7959 	u8         status[0x8];
7960 	u8         reserved_at_8[0x18];
7961 
7962 	u8         syndrome[0x20];
7963 
7964 	u8         reserved_at_40[0x40];
7965 };
7966 
7967 struct mlx5_ifc_destroy_dct_in_bits {
7968 	u8         opcode[0x10];
7969 	u8         uid[0x10];
7970 
7971 	u8         reserved_at_20[0x10];
7972 	u8         op_mod[0x10];
7973 
7974 	u8         reserved_at_40[0x8];
7975 	u8         dctn[0x18];
7976 
7977 	u8         reserved_at_60[0x20];
7978 };
7979 
7980 struct mlx5_ifc_destroy_cq_out_bits {
7981 	u8         status[0x8];
7982 	u8         reserved_at_8[0x18];
7983 
7984 	u8         syndrome[0x20];
7985 
7986 	u8         reserved_at_40[0x40];
7987 };
7988 
7989 struct mlx5_ifc_destroy_cq_in_bits {
7990 	u8         opcode[0x10];
7991 	u8         uid[0x10];
7992 
7993 	u8         reserved_at_20[0x10];
7994 	u8         op_mod[0x10];
7995 
7996 	u8         reserved_at_40[0x8];
7997 	u8         cqn[0x18];
7998 
7999 	u8         reserved_at_60[0x20];
8000 };
8001 
8002 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8003 	u8         status[0x8];
8004 	u8         reserved_at_8[0x18];
8005 
8006 	u8         syndrome[0x20];
8007 
8008 	u8         reserved_at_40[0x40];
8009 };
8010 
8011 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8012 	u8         opcode[0x10];
8013 	u8         reserved_at_10[0x10];
8014 
8015 	u8         reserved_at_20[0x10];
8016 	u8         op_mod[0x10];
8017 
8018 	u8         reserved_at_40[0x20];
8019 
8020 	u8         reserved_at_60[0x10];
8021 	u8         vxlan_udp_port[0x10];
8022 };
8023 
8024 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8025 	u8         status[0x8];
8026 	u8         reserved_at_8[0x18];
8027 
8028 	u8         syndrome[0x20];
8029 
8030 	u8         reserved_at_40[0x40];
8031 };
8032 
8033 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8034 	u8         opcode[0x10];
8035 	u8         reserved_at_10[0x10];
8036 
8037 	u8         reserved_at_20[0x10];
8038 	u8         op_mod[0x10];
8039 
8040 	u8         reserved_at_40[0x60];
8041 
8042 	u8         reserved_at_a0[0x8];
8043 	u8         table_index[0x18];
8044 
8045 	u8         reserved_at_c0[0x140];
8046 };
8047 
8048 struct mlx5_ifc_delete_fte_out_bits {
8049 	u8         status[0x8];
8050 	u8         reserved_at_8[0x18];
8051 
8052 	u8         syndrome[0x20];
8053 
8054 	u8         reserved_at_40[0x40];
8055 };
8056 
8057 struct mlx5_ifc_delete_fte_in_bits {
8058 	u8         opcode[0x10];
8059 	u8         reserved_at_10[0x10];
8060 
8061 	u8         reserved_at_20[0x10];
8062 	u8         op_mod[0x10];
8063 
8064 	u8         other_vport[0x1];
8065 	u8         reserved_at_41[0xf];
8066 	u8         vport_number[0x10];
8067 
8068 	u8         reserved_at_60[0x20];
8069 
8070 	u8         table_type[0x8];
8071 	u8         reserved_at_88[0x18];
8072 
8073 	u8         reserved_at_a0[0x8];
8074 	u8         table_id[0x18];
8075 
8076 	u8         reserved_at_c0[0x40];
8077 
8078 	u8         flow_index[0x20];
8079 
8080 	u8         reserved_at_120[0xe0];
8081 };
8082 
8083 struct mlx5_ifc_dealloc_xrcd_out_bits {
8084 	u8         status[0x8];
8085 	u8         reserved_at_8[0x18];
8086 
8087 	u8         syndrome[0x20];
8088 
8089 	u8         reserved_at_40[0x40];
8090 };
8091 
8092 struct mlx5_ifc_dealloc_xrcd_in_bits {
8093 	u8         opcode[0x10];
8094 	u8         uid[0x10];
8095 
8096 	u8         reserved_at_20[0x10];
8097 	u8         op_mod[0x10];
8098 
8099 	u8         reserved_at_40[0x8];
8100 	u8         xrcd[0x18];
8101 
8102 	u8         reserved_at_60[0x20];
8103 };
8104 
8105 struct mlx5_ifc_dealloc_uar_out_bits {
8106 	u8         status[0x8];
8107 	u8         reserved_at_8[0x18];
8108 
8109 	u8         syndrome[0x20];
8110 
8111 	u8         reserved_at_40[0x40];
8112 };
8113 
8114 struct mlx5_ifc_dealloc_uar_in_bits {
8115 	u8         opcode[0x10];
8116 	u8         uid[0x10];
8117 
8118 	u8         reserved_at_20[0x10];
8119 	u8         op_mod[0x10];
8120 
8121 	u8         reserved_at_40[0x8];
8122 	u8         uar[0x18];
8123 
8124 	u8         reserved_at_60[0x20];
8125 };
8126 
8127 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8128 	u8         status[0x8];
8129 	u8         reserved_at_8[0x18];
8130 
8131 	u8         syndrome[0x20];
8132 
8133 	u8         reserved_at_40[0x40];
8134 };
8135 
8136 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8137 	u8         opcode[0x10];
8138 	u8         uid[0x10];
8139 
8140 	u8         reserved_at_20[0x10];
8141 	u8         op_mod[0x10];
8142 
8143 	u8         reserved_at_40[0x8];
8144 	u8         transport_domain[0x18];
8145 
8146 	u8         reserved_at_60[0x20];
8147 };
8148 
8149 struct mlx5_ifc_dealloc_q_counter_out_bits {
8150 	u8         status[0x8];
8151 	u8         reserved_at_8[0x18];
8152 
8153 	u8         syndrome[0x20];
8154 
8155 	u8         reserved_at_40[0x40];
8156 };
8157 
8158 struct mlx5_ifc_dealloc_q_counter_in_bits {
8159 	u8         opcode[0x10];
8160 	u8         reserved_at_10[0x10];
8161 
8162 	u8         reserved_at_20[0x10];
8163 	u8         op_mod[0x10];
8164 
8165 	u8         reserved_at_40[0x18];
8166 	u8         counter_set_id[0x8];
8167 
8168 	u8         reserved_at_60[0x20];
8169 };
8170 
8171 struct mlx5_ifc_dealloc_pd_out_bits {
8172 	u8         status[0x8];
8173 	u8         reserved_at_8[0x18];
8174 
8175 	u8         syndrome[0x20];
8176 
8177 	u8         reserved_at_40[0x40];
8178 };
8179 
8180 struct mlx5_ifc_dealloc_pd_in_bits {
8181 	u8         opcode[0x10];
8182 	u8         uid[0x10];
8183 
8184 	u8         reserved_at_20[0x10];
8185 	u8         op_mod[0x10];
8186 
8187 	u8         reserved_at_40[0x8];
8188 	u8         pd[0x18];
8189 
8190 	u8         reserved_at_60[0x20];
8191 };
8192 
8193 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8194 	u8         status[0x8];
8195 	u8         reserved_at_8[0x18];
8196 
8197 	u8         syndrome[0x20];
8198 
8199 	u8         reserved_at_40[0x40];
8200 };
8201 
8202 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8203 	u8         opcode[0x10];
8204 	u8         reserved_at_10[0x10];
8205 
8206 	u8         reserved_at_20[0x10];
8207 	u8         op_mod[0x10];
8208 
8209 	u8         flow_counter_id[0x20];
8210 
8211 	u8         reserved_at_60[0x20];
8212 };
8213 
8214 struct mlx5_ifc_create_xrq_out_bits {
8215 	u8         status[0x8];
8216 	u8         reserved_at_8[0x18];
8217 
8218 	u8         syndrome[0x20];
8219 
8220 	u8         reserved_at_40[0x8];
8221 	u8         xrqn[0x18];
8222 
8223 	u8         reserved_at_60[0x20];
8224 };
8225 
8226 struct mlx5_ifc_create_xrq_in_bits {
8227 	u8         opcode[0x10];
8228 	u8         uid[0x10];
8229 
8230 	u8         reserved_at_20[0x10];
8231 	u8         op_mod[0x10];
8232 
8233 	u8         reserved_at_40[0x40];
8234 
8235 	struct mlx5_ifc_xrqc_bits xrq_context;
8236 };
8237 
8238 struct mlx5_ifc_create_xrc_srq_out_bits {
8239 	u8         status[0x8];
8240 	u8         reserved_at_8[0x18];
8241 
8242 	u8         syndrome[0x20];
8243 
8244 	u8         reserved_at_40[0x8];
8245 	u8         xrc_srqn[0x18];
8246 
8247 	u8         reserved_at_60[0x20];
8248 };
8249 
8250 struct mlx5_ifc_create_xrc_srq_in_bits {
8251 	u8         opcode[0x10];
8252 	u8         uid[0x10];
8253 
8254 	u8         reserved_at_20[0x10];
8255 	u8         op_mod[0x10];
8256 
8257 	u8         reserved_at_40[0x40];
8258 
8259 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8260 
8261 	u8         reserved_at_280[0x60];
8262 
8263 	u8         xrc_srq_umem_valid[0x1];
8264 	u8         reserved_at_2e1[0x1f];
8265 
8266 	u8         reserved_at_300[0x580];
8267 
8268 	u8         pas[][0x40];
8269 };
8270 
8271 struct mlx5_ifc_create_tis_out_bits {
8272 	u8         status[0x8];
8273 	u8         reserved_at_8[0x18];
8274 
8275 	u8         syndrome[0x20];
8276 
8277 	u8         reserved_at_40[0x8];
8278 	u8         tisn[0x18];
8279 
8280 	u8         reserved_at_60[0x20];
8281 };
8282 
8283 struct mlx5_ifc_create_tis_in_bits {
8284 	u8         opcode[0x10];
8285 	u8         uid[0x10];
8286 
8287 	u8         reserved_at_20[0x10];
8288 	u8         op_mod[0x10];
8289 
8290 	u8         reserved_at_40[0xc0];
8291 
8292 	struct mlx5_ifc_tisc_bits ctx;
8293 };
8294 
8295 struct mlx5_ifc_create_tir_out_bits {
8296 	u8         status[0x8];
8297 	u8         icm_address_63_40[0x18];
8298 
8299 	u8         syndrome[0x20];
8300 
8301 	u8         icm_address_39_32[0x8];
8302 	u8         tirn[0x18];
8303 
8304 	u8         icm_address_31_0[0x20];
8305 };
8306 
8307 struct mlx5_ifc_create_tir_in_bits {
8308 	u8         opcode[0x10];
8309 	u8         uid[0x10];
8310 
8311 	u8         reserved_at_20[0x10];
8312 	u8         op_mod[0x10];
8313 
8314 	u8         reserved_at_40[0xc0];
8315 
8316 	struct mlx5_ifc_tirc_bits ctx;
8317 };
8318 
8319 struct mlx5_ifc_create_srq_out_bits {
8320 	u8         status[0x8];
8321 	u8         reserved_at_8[0x18];
8322 
8323 	u8         syndrome[0x20];
8324 
8325 	u8         reserved_at_40[0x8];
8326 	u8         srqn[0x18];
8327 
8328 	u8         reserved_at_60[0x20];
8329 };
8330 
8331 struct mlx5_ifc_create_srq_in_bits {
8332 	u8         opcode[0x10];
8333 	u8         uid[0x10];
8334 
8335 	u8         reserved_at_20[0x10];
8336 	u8         op_mod[0x10];
8337 
8338 	u8         reserved_at_40[0x40];
8339 
8340 	struct mlx5_ifc_srqc_bits srq_context_entry;
8341 
8342 	u8         reserved_at_280[0x600];
8343 
8344 	u8         pas[][0x40];
8345 };
8346 
8347 struct mlx5_ifc_create_sq_out_bits {
8348 	u8         status[0x8];
8349 	u8         reserved_at_8[0x18];
8350 
8351 	u8         syndrome[0x20];
8352 
8353 	u8         reserved_at_40[0x8];
8354 	u8         sqn[0x18];
8355 
8356 	u8         reserved_at_60[0x20];
8357 };
8358 
8359 struct mlx5_ifc_create_sq_in_bits {
8360 	u8         opcode[0x10];
8361 	u8         uid[0x10];
8362 
8363 	u8         reserved_at_20[0x10];
8364 	u8         op_mod[0x10];
8365 
8366 	u8         reserved_at_40[0xc0];
8367 
8368 	struct mlx5_ifc_sqc_bits ctx;
8369 };
8370 
8371 struct mlx5_ifc_create_scheduling_element_out_bits {
8372 	u8         status[0x8];
8373 	u8         reserved_at_8[0x18];
8374 
8375 	u8         syndrome[0x20];
8376 
8377 	u8         reserved_at_40[0x40];
8378 
8379 	u8         scheduling_element_id[0x20];
8380 
8381 	u8         reserved_at_a0[0x160];
8382 };
8383 
8384 struct mlx5_ifc_create_scheduling_element_in_bits {
8385 	u8         opcode[0x10];
8386 	u8         reserved_at_10[0x10];
8387 
8388 	u8         reserved_at_20[0x10];
8389 	u8         op_mod[0x10];
8390 
8391 	u8         scheduling_hierarchy[0x8];
8392 	u8         reserved_at_48[0x18];
8393 
8394 	u8         reserved_at_60[0xa0];
8395 
8396 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8397 
8398 	u8         reserved_at_300[0x100];
8399 };
8400 
8401 struct mlx5_ifc_create_rqt_out_bits {
8402 	u8         status[0x8];
8403 	u8         reserved_at_8[0x18];
8404 
8405 	u8         syndrome[0x20];
8406 
8407 	u8         reserved_at_40[0x8];
8408 	u8         rqtn[0x18];
8409 
8410 	u8         reserved_at_60[0x20];
8411 };
8412 
8413 struct mlx5_ifc_create_rqt_in_bits {
8414 	u8         opcode[0x10];
8415 	u8         uid[0x10];
8416 
8417 	u8         reserved_at_20[0x10];
8418 	u8         op_mod[0x10];
8419 
8420 	u8         reserved_at_40[0xc0];
8421 
8422 	struct mlx5_ifc_rqtc_bits rqt_context;
8423 };
8424 
8425 struct mlx5_ifc_create_rq_out_bits {
8426 	u8         status[0x8];
8427 	u8         reserved_at_8[0x18];
8428 
8429 	u8         syndrome[0x20];
8430 
8431 	u8         reserved_at_40[0x8];
8432 	u8         rqn[0x18];
8433 
8434 	u8         reserved_at_60[0x20];
8435 };
8436 
8437 struct mlx5_ifc_create_rq_in_bits {
8438 	u8         opcode[0x10];
8439 	u8         uid[0x10];
8440 
8441 	u8         reserved_at_20[0x10];
8442 	u8         op_mod[0x10];
8443 
8444 	u8         reserved_at_40[0xc0];
8445 
8446 	struct mlx5_ifc_rqc_bits ctx;
8447 };
8448 
8449 struct mlx5_ifc_create_rmp_out_bits {
8450 	u8         status[0x8];
8451 	u8         reserved_at_8[0x18];
8452 
8453 	u8         syndrome[0x20];
8454 
8455 	u8         reserved_at_40[0x8];
8456 	u8         rmpn[0x18];
8457 
8458 	u8         reserved_at_60[0x20];
8459 };
8460 
8461 struct mlx5_ifc_create_rmp_in_bits {
8462 	u8         opcode[0x10];
8463 	u8         uid[0x10];
8464 
8465 	u8         reserved_at_20[0x10];
8466 	u8         op_mod[0x10];
8467 
8468 	u8         reserved_at_40[0xc0];
8469 
8470 	struct mlx5_ifc_rmpc_bits ctx;
8471 };
8472 
8473 struct mlx5_ifc_create_qp_out_bits {
8474 	u8         status[0x8];
8475 	u8         reserved_at_8[0x18];
8476 
8477 	u8         syndrome[0x20];
8478 
8479 	u8         reserved_at_40[0x8];
8480 	u8         qpn[0x18];
8481 
8482 	u8         ece[0x20];
8483 };
8484 
8485 struct mlx5_ifc_create_qp_in_bits {
8486 	u8         opcode[0x10];
8487 	u8         uid[0x10];
8488 
8489 	u8         reserved_at_20[0x10];
8490 	u8         op_mod[0x10];
8491 
8492 	u8         reserved_at_40[0x8];
8493 	u8         input_qpn[0x18];
8494 
8495 	u8         reserved_at_60[0x20];
8496 	u8         opt_param_mask[0x20];
8497 
8498 	u8         ece[0x20];
8499 
8500 	struct mlx5_ifc_qpc_bits qpc;
8501 
8502 	u8         reserved_at_800[0x60];
8503 
8504 	u8         wq_umem_valid[0x1];
8505 	u8         reserved_at_861[0x1f];
8506 
8507 	u8         pas[][0x40];
8508 };
8509 
8510 struct mlx5_ifc_create_psv_out_bits {
8511 	u8         status[0x8];
8512 	u8         reserved_at_8[0x18];
8513 
8514 	u8         syndrome[0x20];
8515 
8516 	u8         reserved_at_40[0x40];
8517 
8518 	u8         reserved_at_80[0x8];
8519 	u8         psv0_index[0x18];
8520 
8521 	u8         reserved_at_a0[0x8];
8522 	u8         psv1_index[0x18];
8523 
8524 	u8         reserved_at_c0[0x8];
8525 	u8         psv2_index[0x18];
8526 
8527 	u8         reserved_at_e0[0x8];
8528 	u8         psv3_index[0x18];
8529 };
8530 
8531 struct mlx5_ifc_create_psv_in_bits {
8532 	u8         opcode[0x10];
8533 	u8         reserved_at_10[0x10];
8534 
8535 	u8         reserved_at_20[0x10];
8536 	u8         op_mod[0x10];
8537 
8538 	u8         num_psv[0x4];
8539 	u8         reserved_at_44[0x4];
8540 	u8         pd[0x18];
8541 
8542 	u8         reserved_at_60[0x20];
8543 };
8544 
8545 struct mlx5_ifc_create_mkey_out_bits {
8546 	u8         status[0x8];
8547 	u8         reserved_at_8[0x18];
8548 
8549 	u8         syndrome[0x20];
8550 
8551 	u8         reserved_at_40[0x8];
8552 	u8         mkey_index[0x18];
8553 
8554 	u8         reserved_at_60[0x20];
8555 };
8556 
8557 struct mlx5_ifc_create_mkey_in_bits {
8558 	u8         opcode[0x10];
8559 	u8         uid[0x10];
8560 
8561 	u8         reserved_at_20[0x10];
8562 	u8         op_mod[0x10];
8563 
8564 	u8         reserved_at_40[0x20];
8565 
8566 	u8         pg_access[0x1];
8567 	u8         mkey_umem_valid[0x1];
8568 	u8         reserved_at_62[0x1e];
8569 
8570 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8571 
8572 	u8         reserved_at_280[0x80];
8573 
8574 	u8         translations_octword_actual_size[0x20];
8575 
8576 	u8         reserved_at_320[0x560];
8577 
8578 	u8         klm_pas_mtt[][0x20];
8579 };
8580 
8581 enum {
8582 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8583 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8584 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8585 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8586 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8587 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8588 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8589 };
8590 
8591 struct mlx5_ifc_create_flow_table_out_bits {
8592 	u8         status[0x8];
8593 	u8         icm_address_63_40[0x18];
8594 
8595 	u8         syndrome[0x20];
8596 
8597 	u8         icm_address_39_32[0x8];
8598 	u8         table_id[0x18];
8599 
8600 	u8         icm_address_31_0[0x20];
8601 };
8602 
8603 struct mlx5_ifc_create_flow_table_in_bits {
8604 	u8         opcode[0x10];
8605 	u8         uid[0x10];
8606 
8607 	u8         reserved_at_20[0x10];
8608 	u8         op_mod[0x10];
8609 
8610 	u8         other_vport[0x1];
8611 	u8         reserved_at_41[0xf];
8612 	u8         vport_number[0x10];
8613 
8614 	u8         reserved_at_60[0x20];
8615 
8616 	u8         table_type[0x8];
8617 	u8         reserved_at_88[0x18];
8618 
8619 	u8         reserved_at_a0[0x20];
8620 
8621 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8622 };
8623 
8624 struct mlx5_ifc_create_flow_group_out_bits {
8625 	u8         status[0x8];
8626 	u8         reserved_at_8[0x18];
8627 
8628 	u8         syndrome[0x20];
8629 
8630 	u8         reserved_at_40[0x8];
8631 	u8         group_id[0x18];
8632 
8633 	u8         reserved_at_60[0x20];
8634 };
8635 
8636 enum {
8637 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8638 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8639 };
8640 
8641 enum {
8642 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8643 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8644 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8645 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8646 };
8647 
8648 struct mlx5_ifc_create_flow_group_in_bits {
8649 	u8         opcode[0x10];
8650 	u8         reserved_at_10[0x10];
8651 
8652 	u8         reserved_at_20[0x10];
8653 	u8         op_mod[0x10];
8654 
8655 	u8         other_vport[0x1];
8656 	u8         reserved_at_41[0xf];
8657 	u8         vport_number[0x10];
8658 
8659 	u8         reserved_at_60[0x20];
8660 
8661 	u8         table_type[0x8];
8662 	u8         reserved_at_88[0x4];
8663 	u8         group_type[0x4];
8664 	u8         reserved_at_90[0x10];
8665 
8666 	u8         reserved_at_a0[0x8];
8667 	u8         table_id[0x18];
8668 
8669 	u8         source_eswitch_owner_vhca_id_valid[0x1];
8670 
8671 	u8         reserved_at_c1[0x1f];
8672 
8673 	u8         start_flow_index[0x20];
8674 
8675 	u8         reserved_at_100[0x20];
8676 
8677 	u8         end_flow_index[0x20];
8678 
8679 	u8         reserved_at_140[0x10];
8680 	u8         match_definer_id[0x10];
8681 
8682 	u8         reserved_at_160[0x80];
8683 
8684 	u8         reserved_at_1e0[0x18];
8685 	u8         match_criteria_enable[0x8];
8686 
8687 	struct mlx5_ifc_fte_match_param_bits match_criteria;
8688 
8689 	u8         reserved_at_1200[0xe00];
8690 };
8691 
8692 struct mlx5_ifc_create_eq_out_bits {
8693 	u8         status[0x8];
8694 	u8         reserved_at_8[0x18];
8695 
8696 	u8         syndrome[0x20];
8697 
8698 	u8         reserved_at_40[0x18];
8699 	u8         eq_number[0x8];
8700 
8701 	u8         reserved_at_60[0x20];
8702 };
8703 
8704 struct mlx5_ifc_create_eq_in_bits {
8705 	u8         opcode[0x10];
8706 	u8         uid[0x10];
8707 
8708 	u8         reserved_at_20[0x10];
8709 	u8         op_mod[0x10];
8710 
8711 	u8         reserved_at_40[0x40];
8712 
8713 	struct mlx5_ifc_eqc_bits eq_context_entry;
8714 
8715 	u8         reserved_at_280[0x40];
8716 
8717 	u8         event_bitmask[4][0x40];
8718 
8719 	u8         reserved_at_3c0[0x4c0];
8720 
8721 	u8         pas[][0x40];
8722 };
8723 
8724 struct mlx5_ifc_create_dct_out_bits {
8725 	u8         status[0x8];
8726 	u8         reserved_at_8[0x18];
8727 
8728 	u8         syndrome[0x20];
8729 
8730 	u8         reserved_at_40[0x8];
8731 	u8         dctn[0x18];
8732 
8733 	u8         ece[0x20];
8734 };
8735 
8736 struct mlx5_ifc_create_dct_in_bits {
8737 	u8         opcode[0x10];
8738 	u8         uid[0x10];
8739 
8740 	u8         reserved_at_20[0x10];
8741 	u8         op_mod[0x10];
8742 
8743 	u8         reserved_at_40[0x40];
8744 
8745 	struct mlx5_ifc_dctc_bits dct_context_entry;
8746 
8747 	u8         reserved_at_280[0x180];
8748 };
8749 
8750 struct mlx5_ifc_create_cq_out_bits {
8751 	u8         status[0x8];
8752 	u8         reserved_at_8[0x18];
8753 
8754 	u8         syndrome[0x20];
8755 
8756 	u8         reserved_at_40[0x8];
8757 	u8         cqn[0x18];
8758 
8759 	u8         reserved_at_60[0x20];
8760 };
8761 
8762 struct mlx5_ifc_create_cq_in_bits {
8763 	u8         opcode[0x10];
8764 	u8         uid[0x10];
8765 
8766 	u8         reserved_at_20[0x10];
8767 	u8         op_mod[0x10];
8768 
8769 	u8         reserved_at_40[0x40];
8770 
8771 	struct mlx5_ifc_cqc_bits cq_context;
8772 
8773 	u8         reserved_at_280[0x60];
8774 
8775 	u8         cq_umem_valid[0x1];
8776 	u8         reserved_at_2e1[0x59f];
8777 
8778 	u8         pas[][0x40];
8779 };
8780 
8781 struct mlx5_ifc_config_int_moderation_out_bits {
8782 	u8         status[0x8];
8783 	u8         reserved_at_8[0x18];
8784 
8785 	u8         syndrome[0x20];
8786 
8787 	u8         reserved_at_40[0x4];
8788 	u8         min_delay[0xc];
8789 	u8         int_vector[0x10];
8790 
8791 	u8         reserved_at_60[0x20];
8792 };
8793 
8794 enum {
8795 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
8796 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
8797 };
8798 
8799 struct mlx5_ifc_config_int_moderation_in_bits {
8800 	u8         opcode[0x10];
8801 	u8         reserved_at_10[0x10];
8802 
8803 	u8         reserved_at_20[0x10];
8804 	u8         op_mod[0x10];
8805 
8806 	u8         reserved_at_40[0x4];
8807 	u8         min_delay[0xc];
8808 	u8         int_vector[0x10];
8809 
8810 	u8         reserved_at_60[0x20];
8811 };
8812 
8813 struct mlx5_ifc_attach_to_mcg_out_bits {
8814 	u8         status[0x8];
8815 	u8         reserved_at_8[0x18];
8816 
8817 	u8         syndrome[0x20];
8818 
8819 	u8         reserved_at_40[0x40];
8820 };
8821 
8822 struct mlx5_ifc_attach_to_mcg_in_bits {
8823 	u8         opcode[0x10];
8824 	u8         uid[0x10];
8825 
8826 	u8         reserved_at_20[0x10];
8827 	u8         op_mod[0x10];
8828 
8829 	u8         reserved_at_40[0x8];
8830 	u8         qpn[0x18];
8831 
8832 	u8         reserved_at_60[0x20];
8833 
8834 	u8         multicast_gid[16][0x8];
8835 };
8836 
8837 struct mlx5_ifc_arm_xrq_out_bits {
8838 	u8         status[0x8];
8839 	u8         reserved_at_8[0x18];
8840 
8841 	u8         syndrome[0x20];
8842 
8843 	u8         reserved_at_40[0x40];
8844 };
8845 
8846 struct mlx5_ifc_arm_xrq_in_bits {
8847 	u8         opcode[0x10];
8848 	u8         reserved_at_10[0x10];
8849 
8850 	u8         reserved_at_20[0x10];
8851 	u8         op_mod[0x10];
8852 
8853 	u8         reserved_at_40[0x8];
8854 	u8         xrqn[0x18];
8855 
8856 	u8         reserved_at_60[0x10];
8857 	u8         lwm[0x10];
8858 };
8859 
8860 struct mlx5_ifc_arm_xrc_srq_out_bits {
8861 	u8         status[0x8];
8862 	u8         reserved_at_8[0x18];
8863 
8864 	u8         syndrome[0x20];
8865 
8866 	u8         reserved_at_40[0x40];
8867 };
8868 
8869 enum {
8870 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
8871 };
8872 
8873 struct mlx5_ifc_arm_xrc_srq_in_bits {
8874 	u8         opcode[0x10];
8875 	u8         uid[0x10];
8876 
8877 	u8         reserved_at_20[0x10];
8878 	u8         op_mod[0x10];
8879 
8880 	u8         reserved_at_40[0x8];
8881 	u8         xrc_srqn[0x18];
8882 
8883 	u8         reserved_at_60[0x10];
8884 	u8         lwm[0x10];
8885 };
8886 
8887 struct mlx5_ifc_arm_rq_out_bits {
8888 	u8         status[0x8];
8889 	u8         reserved_at_8[0x18];
8890 
8891 	u8         syndrome[0x20];
8892 
8893 	u8         reserved_at_40[0x40];
8894 };
8895 
8896 enum {
8897 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8898 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8899 };
8900 
8901 struct mlx5_ifc_arm_rq_in_bits {
8902 	u8         opcode[0x10];
8903 	u8         uid[0x10];
8904 
8905 	u8         reserved_at_20[0x10];
8906 	u8         op_mod[0x10];
8907 
8908 	u8         reserved_at_40[0x8];
8909 	u8         srq_number[0x18];
8910 
8911 	u8         reserved_at_60[0x10];
8912 	u8         lwm[0x10];
8913 };
8914 
8915 struct mlx5_ifc_arm_dct_out_bits {
8916 	u8         status[0x8];
8917 	u8         reserved_at_8[0x18];
8918 
8919 	u8         syndrome[0x20];
8920 
8921 	u8         reserved_at_40[0x40];
8922 };
8923 
8924 struct mlx5_ifc_arm_dct_in_bits {
8925 	u8         opcode[0x10];
8926 	u8         reserved_at_10[0x10];
8927 
8928 	u8         reserved_at_20[0x10];
8929 	u8         op_mod[0x10];
8930 
8931 	u8         reserved_at_40[0x8];
8932 	u8         dct_number[0x18];
8933 
8934 	u8         reserved_at_60[0x20];
8935 };
8936 
8937 struct mlx5_ifc_alloc_xrcd_out_bits {
8938 	u8         status[0x8];
8939 	u8         reserved_at_8[0x18];
8940 
8941 	u8         syndrome[0x20];
8942 
8943 	u8         reserved_at_40[0x8];
8944 	u8         xrcd[0x18];
8945 
8946 	u8         reserved_at_60[0x20];
8947 };
8948 
8949 struct mlx5_ifc_alloc_xrcd_in_bits {
8950 	u8         opcode[0x10];
8951 	u8         uid[0x10];
8952 
8953 	u8         reserved_at_20[0x10];
8954 	u8         op_mod[0x10];
8955 
8956 	u8         reserved_at_40[0x40];
8957 };
8958 
8959 struct mlx5_ifc_alloc_uar_out_bits {
8960 	u8         status[0x8];
8961 	u8         reserved_at_8[0x18];
8962 
8963 	u8         syndrome[0x20];
8964 
8965 	u8         reserved_at_40[0x8];
8966 	u8         uar[0x18];
8967 
8968 	u8         reserved_at_60[0x20];
8969 };
8970 
8971 struct mlx5_ifc_alloc_uar_in_bits {
8972 	u8         opcode[0x10];
8973 	u8         uid[0x10];
8974 
8975 	u8         reserved_at_20[0x10];
8976 	u8         op_mod[0x10];
8977 
8978 	u8         reserved_at_40[0x40];
8979 };
8980 
8981 struct mlx5_ifc_alloc_transport_domain_out_bits {
8982 	u8         status[0x8];
8983 	u8         reserved_at_8[0x18];
8984 
8985 	u8         syndrome[0x20];
8986 
8987 	u8         reserved_at_40[0x8];
8988 	u8         transport_domain[0x18];
8989 
8990 	u8         reserved_at_60[0x20];
8991 };
8992 
8993 struct mlx5_ifc_alloc_transport_domain_in_bits {
8994 	u8         opcode[0x10];
8995 	u8         uid[0x10];
8996 
8997 	u8         reserved_at_20[0x10];
8998 	u8         op_mod[0x10];
8999 
9000 	u8         reserved_at_40[0x40];
9001 };
9002 
9003 struct mlx5_ifc_alloc_q_counter_out_bits {
9004 	u8         status[0x8];
9005 	u8         reserved_at_8[0x18];
9006 
9007 	u8         syndrome[0x20];
9008 
9009 	u8         reserved_at_40[0x18];
9010 	u8         counter_set_id[0x8];
9011 
9012 	u8         reserved_at_60[0x20];
9013 };
9014 
9015 struct mlx5_ifc_alloc_q_counter_in_bits {
9016 	u8         opcode[0x10];
9017 	u8         uid[0x10];
9018 
9019 	u8         reserved_at_20[0x10];
9020 	u8         op_mod[0x10];
9021 
9022 	u8         reserved_at_40[0x40];
9023 };
9024 
9025 struct mlx5_ifc_alloc_pd_out_bits {
9026 	u8         status[0x8];
9027 	u8         reserved_at_8[0x18];
9028 
9029 	u8         syndrome[0x20];
9030 
9031 	u8         reserved_at_40[0x8];
9032 	u8         pd[0x18];
9033 
9034 	u8         reserved_at_60[0x20];
9035 };
9036 
9037 struct mlx5_ifc_alloc_pd_in_bits {
9038 	u8         opcode[0x10];
9039 	u8         uid[0x10];
9040 
9041 	u8         reserved_at_20[0x10];
9042 	u8         op_mod[0x10];
9043 
9044 	u8         reserved_at_40[0x40];
9045 };
9046 
9047 struct mlx5_ifc_alloc_flow_counter_out_bits {
9048 	u8         status[0x8];
9049 	u8         reserved_at_8[0x18];
9050 
9051 	u8         syndrome[0x20];
9052 
9053 	u8         flow_counter_id[0x20];
9054 
9055 	u8         reserved_at_60[0x20];
9056 };
9057 
9058 struct mlx5_ifc_alloc_flow_counter_in_bits {
9059 	u8         opcode[0x10];
9060 	u8         reserved_at_10[0x10];
9061 
9062 	u8         reserved_at_20[0x10];
9063 	u8         op_mod[0x10];
9064 
9065 	u8         reserved_at_40[0x38];
9066 	u8         flow_counter_bulk[0x8];
9067 };
9068 
9069 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9070 	u8         status[0x8];
9071 	u8         reserved_at_8[0x18];
9072 
9073 	u8         syndrome[0x20];
9074 
9075 	u8         reserved_at_40[0x40];
9076 };
9077 
9078 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9079 	u8         opcode[0x10];
9080 	u8         reserved_at_10[0x10];
9081 
9082 	u8         reserved_at_20[0x10];
9083 	u8         op_mod[0x10];
9084 
9085 	u8         reserved_at_40[0x20];
9086 
9087 	u8         reserved_at_60[0x10];
9088 	u8         vxlan_udp_port[0x10];
9089 };
9090 
9091 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9092 	u8         status[0x8];
9093 	u8         reserved_at_8[0x18];
9094 
9095 	u8         syndrome[0x20];
9096 
9097 	u8         reserved_at_40[0x40];
9098 };
9099 
9100 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9101 	u8         rate_limit[0x20];
9102 
9103 	u8	   burst_upper_bound[0x20];
9104 
9105 	u8         reserved_at_40[0x10];
9106 	u8	   typical_packet_size[0x10];
9107 
9108 	u8         reserved_at_60[0x120];
9109 };
9110 
9111 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9112 	u8         opcode[0x10];
9113 	u8         uid[0x10];
9114 
9115 	u8         reserved_at_20[0x10];
9116 	u8         op_mod[0x10];
9117 
9118 	u8         reserved_at_40[0x10];
9119 	u8         rate_limit_index[0x10];
9120 
9121 	u8         reserved_at_60[0x20];
9122 
9123 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9124 };
9125 
9126 struct mlx5_ifc_access_register_out_bits {
9127 	u8         status[0x8];
9128 	u8         reserved_at_8[0x18];
9129 
9130 	u8         syndrome[0x20];
9131 
9132 	u8         reserved_at_40[0x40];
9133 
9134 	u8         register_data[][0x20];
9135 };
9136 
9137 enum {
9138 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9139 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9140 };
9141 
9142 struct mlx5_ifc_access_register_in_bits {
9143 	u8         opcode[0x10];
9144 	u8         reserved_at_10[0x10];
9145 
9146 	u8         reserved_at_20[0x10];
9147 	u8         op_mod[0x10];
9148 
9149 	u8         reserved_at_40[0x10];
9150 	u8         register_id[0x10];
9151 
9152 	u8         argument[0x20];
9153 
9154 	u8         register_data[][0x20];
9155 };
9156 
9157 struct mlx5_ifc_sltp_reg_bits {
9158 	u8         status[0x4];
9159 	u8         version[0x4];
9160 	u8         local_port[0x8];
9161 	u8         pnat[0x2];
9162 	u8         reserved_at_12[0x2];
9163 	u8         lane[0x4];
9164 	u8         reserved_at_18[0x8];
9165 
9166 	u8         reserved_at_20[0x20];
9167 
9168 	u8         reserved_at_40[0x7];
9169 	u8         polarity[0x1];
9170 	u8         ob_tap0[0x8];
9171 	u8         ob_tap1[0x8];
9172 	u8         ob_tap2[0x8];
9173 
9174 	u8         reserved_at_60[0xc];
9175 	u8         ob_preemp_mode[0x4];
9176 	u8         ob_reg[0x8];
9177 	u8         ob_bias[0x8];
9178 
9179 	u8         reserved_at_80[0x20];
9180 };
9181 
9182 struct mlx5_ifc_slrg_reg_bits {
9183 	u8         status[0x4];
9184 	u8         version[0x4];
9185 	u8         local_port[0x8];
9186 	u8         pnat[0x2];
9187 	u8         reserved_at_12[0x2];
9188 	u8         lane[0x4];
9189 	u8         reserved_at_18[0x8];
9190 
9191 	u8         time_to_link_up[0x10];
9192 	u8         reserved_at_30[0xc];
9193 	u8         grade_lane_speed[0x4];
9194 
9195 	u8         grade_version[0x8];
9196 	u8         grade[0x18];
9197 
9198 	u8         reserved_at_60[0x4];
9199 	u8         height_grade_type[0x4];
9200 	u8         height_grade[0x18];
9201 
9202 	u8         height_dz[0x10];
9203 	u8         height_dv[0x10];
9204 
9205 	u8         reserved_at_a0[0x10];
9206 	u8         height_sigma[0x10];
9207 
9208 	u8         reserved_at_c0[0x20];
9209 
9210 	u8         reserved_at_e0[0x4];
9211 	u8         phase_grade_type[0x4];
9212 	u8         phase_grade[0x18];
9213 
9214 	u8         reserved_at_100[0x8];
9215 	u8         phase_eo_pos[0x8];
9216 	u8         reserved_at_110[0x8];
9217 	u8         phase_eo_neg[0x8];
9218 
9219 	u8         ffe_set_tested[0x10];
9220 	u8         test_errors_per_lane[0x10];
9221 };
9222 
9223 struct mlx5_ifc_pvlc_reg_bits {
9224 	u8         reserved_at_0[0x8];
9225 	u8         local_port[0x8];
9226 	u8         reserved_at_10[0x10];
9227 
9228 	u8         reserved_at_20[0x1c];
9229 	u8         vl_hw_cap[0x4];
9230 
9231 	u8         reserved_at_40[0x1c];
9232 	u8         vl_admin[0x4];
9233 
9234 	u8         reserved_at_60[0x1c];
9235 	u8         vl_operational[0x4];
9236 };
9237 
9238 struct mlx5_ifc_pude_reg_bits {
9239 	u8         swid[0x8];
9240 	u8         local_port[0x8];
9241 	u8         reserved_at_10[0x4];
9242 	u8         admin_status[0x4];
9243 	u8         reserved_at_18[0x4];
9244 	u8         oper_status[0x4];
9245 
9246 	u8         reserved_at_20[0x60];
9247 };
9248 
9249 struct mlx5_ifc_ptys_reg_bits {
9250 	u8         reserved_at_0[0x1];
9251 	u8         an_disable_admin[0x1];
9252 	u8         an_disable_cap[0x1];
9253 	u8         reserved_at_3[0x5];
9254 	u8         local_port[0x8];
9255 	u8         reserved_at_10[0xd];
9256 	u8         proto_mask[0x3];
9257 
9258 	u8         an_status[0x4];
9259 	u8         reserved_at_24[0xc];
9260 	u8         data_rate_oper[0x10];
9261 
9262 	u8         ext_eth_proto_capability[0x20];
9263 
9264 	u8         eth_proto_capability[0x20];
9265 
9266 	u8         ib_link_width_capability[0x10];
9267 	u8         ib_proto_capability[0x10];
9268 
9269 	u8         ext_eth_proto_admin[0x20];
9270 
9271 	u8         eth_proto_admin[0x20];
9272 
9273 	u8         ib_link_width_admin[0x10];
9274 	u8         ib_proto_admin[0x10];
9275 
9276 	u8         ext_eth_proto_oper[0x20];
9277 
9278 	u8         eth_proto_oper[0x20];
9279 
9280 	u8         ib_link_width_oper[0x10];
9281 	u8         ib_proto_oper[0x10];
9282 
9283 	u8         reserved_at_160[0x1c];
9284 	u8         connector_type[0x4];
9285 
9286 	u8         eth_proto_lp_advertise[0x20];
9287 
9288 	u8         reserved_at_1a0[0x60];
9289 };
9290 
9291 struct mlx5_ifc_mlcr_reg_bits {
9292 	u8         reserved_at_0[0x8];
9293 	u8         local_port[0x8];
9294 	u8         reserved_at_10[0x20];
9295 
9296 	u8         beacon_duration[0x10];
9297 	u8         reserved_at_40[0x10];
9298 
9299 	u8         beacon_remain[0x10];
9300 };
9301 
9302 struct mlx5_ifc_ptas_reg_bits {
9303 	u8         reserved_at_0[0x20];
9304 
9305 	u8         algorithm_options[0x10];
9306 	u8         reserved_at_30[0x4];
9307 	u8         repetitions_mode[0x4];
9308 	u8         num_of_repetitions[0x8];
9309 
9310 	u8         grade_version[0x8];
9311 	u8         height_grade_type[0x4];
9312 	u8         phase_grade_type[0x4];
9313 	u8         height_grade_weight[0x8];
9314 	u8         phase_grade_weight[0x8];
9315 
9316 	u8         gisim_measure_bits[0x10];
9317 	u8         adaptive_tap_measure_bits[0x10];
9318 
9319 	u8         ber_bath_high_error_threshold[0x10];
9320 	u8         ber_bath_mid_error_threshold[0x10];
9321 
9322 	u8         ber_bath_low_error_threshold[0x10];
9323 	u8         one_ratio_high_threshold[0x10];
9324 
9325 	u8         one_ratio_high_mid_threshold[0x10];
9326 	u8         one_ratio_low_mid_threshold[0x10];
9327 
9328 	u8         one_ratio_low_threshold[0x10];
9329 	u8         ndeo_error_threshold[0x10];
9330 
9331 	u8         mixer_offset_step_size[0x10];
9332 	u8         reserved_at_110[0x8];
9333 	u8         mix90_phase_for_voltage_bath[0x8];
9334 
9335 	u8         mixer_offset_start[0x10];
9336 	u8         mixer_offset_end[0x10];
9337 
9338 	u8         reserved_at_140[0x15];
9339 	u8         ber_test_time[0xb];
9340 };
9341 
9342 struct mlx5_ifc_pspa_reg_bits {
9343 	u8         swid[0x8];
9344 	u8         local_port[0x8];
9345 	u8         sub_port[0x8];
9346 	u8         reserved_at_18[0x8];
9347 
9348 	u8         reserved_at_20[0x20];
9349 };
9350 
9351 struct mlx5_ifc_pqdr_reg_bits {
9352 	u8         reserved_at_0[0x8];
9353 	u8         local_port[0x8];
9354 	u8         reserved_at_10[0x5];
9355 	u8         prio[0x3];
9356 	u8         reserved_at_18[0x6];
9357 	u8         mode[0x2];
9358 
9359 	u8         reserved_at_20[0x20];
9360 
9361 	u8         reserved_at_40[0x10];
9362 	u8         min_threshold[0x10];
9363 
9364 	u8         reserved_at_60[0x10];
9365 	u8         max_threshold[0x10];
9366 
9367 	u8         reserved_at_80[0x10];
9368 	u8         mark_probability_denominator[0x10];
9369 
9370 	u8         reserved_at_a0[0x60];
9371 };
9372 
9373 struct mlx5_ifc_ppsc_reg_bits {
9374 	u8         reserved_at_0[0x8];
9375 	u8         local_port[0x8];
9376 	u8         reserved_at_10[0x10];
9377 
9378 	u8         reserved_at_20[0x60];
9379 
9380 	u8         reserved_at_80[0x1c];
9381 	u8         wrps_admin[0x4];
9382 
9383 	u8         reserved_at_a0[0x1c];
9384 	u8         wrps_status[0x4];
9385 
9386 	u8         reserved_at_c0[0x8];
9387 	u8         up_threshold[0x8];
9388 	u8         reserved_at_d0[0x8];
9389 	u8         down_threshold[0x8];
9390 
9391 	u8         reserved_at_e0[0x20];
9392 
9393 	u8         reserved_at_100[0x1c];
9394 	u8         srps_admin[0x4];
9395 
9396 	u8         reserved_at_120[0x1c];
9397 	u8         srps_status[0x4];
9398 
9399 	u8         reserved_at_140[0x40];
9400 };
9401 
9402 struct mlx5_ifc_pplr_reg_bits {
9403 	u8         reserved_at_0[0x8];
9404 	u8         local_port[0x8];
9405 	u8         reserved_at_10[0x10];
9406 
9407 	u8         reserved_at_20[0x8];
9408 	u8         lb_cap[0x8];
9409 	u8         reserved_at_30[0x8];
9410 	u8         lb_en[0x8];
9411 };
9412 
9413 struct mlx5_ifc_pplm_reg_bits {
9414 	u8         reserved_at_0[0x8];
9415 	u8	   local_port[0x8];
9416 	u8	   reserved_at_10[0x10];
9417 
9418 	u8	   reserved_at_20[0x20];
9419 
9420 	u8	   port_profile_mode[0x8];
9421 	u8	   static_port_profile[0x8];
9422 	u8	   active_port_profile[0x8];
9423 	u8	   reserved_at_58[0x8];
9424 
9425 	u8	   retransmission_active[0x8];
9426 	u8	   fec_mode_active[0x18];
9427 
9428 	u8	   rs_fec_correction_bypass_cap[0x4];
9429 	u8	   reserved_at_84[0x8];
9430 	u8	   fec_override_cap_56g[0x4];
9431 	u8	   fec_override_cap_100g[0x4];
9432 	u8	   fec_override_cap_50g[0x4];
9433 	u8	   fec_override_cap_25g[0x4];
9434 	u8	   fec_override_cap_10g_40g[0x4];
9435 
9436 	u8	   rs_fec_correction_bypass_admin[0x4];
9437 	u8	   reserved_at_a4[0x8];
9438 	u8	   fec_override_admin_56g[0x4];
9439 	u8	   fec_override_admin_100g[0x4];
9440 	u8	   fec_override_admin_50g[0x4];
9441 	u8	   fec_override_admin_25g[0x4];
9442 	u8	   fec_override_admin_10g_40g[0x4];
9443 
9444 	u8         fec_override_cap_400g_8x[0x10];
9445 	u8         fec_override_cap_200g_4x[0x10];
9446 
9447 	u8         fec_override_cap_100g_2x[0x10];
9448 	u8         fec_override_cap_50g_1x[0x10];
9449 
9450 	u8         fec_override_admin_400g_8x[0x10];
9451 	u8         fec_override_admin_200g_4x[0x10];
9452 
9453 	u8         fec_override_admin_100g_2x[0x10];
9454 	u8         fec_override_admin_50g_1x[0x10];
9455 
9456 	u8         reserved_at_140[0x140];
9457 };
9458 
9459 struct mlx5_ifc_ppcnt_reg_bits {
9460 	u8         swid[0x8];
9461 	u8         local_port[0x8];
9462 	u8         pnat[0x2];
9463 	u8         reserved_at_12[0x8];
9464 	u8         grp[0x6];
9465 
9466 	u8         clr[0x1];
9467 	u8         reserved_at_21[0x1c];
9468 	u8         prio_tc[0x3];
9469 
9470 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9471 };
9472 
9473 struct mlx5_ifc_mpein_reg_bits {
9474 	u8         reserved_at_0[0x2];
9475 	u8         depth[0x6];
9476 	u8         pcie_index[0x8];
9477 	u8         node[0x8];
9478 	u8         reserved_at_18[0x8];
9479 
9480 	u8         capability_mask[0x20];
9481 
9482 	u8         reserved_at_40[0x8];
9483 	u8         link_width_enabled[0x8];
9484 	u8         link_speed_enabled[0x10];
9485 
9486 	u8         lane0_physical_position[0x8];
9487 	u8         link_width_active[0x8];
9488 	u8         link_speed_active[0x10];
9489 
9490 	u8         num_of_pfs[0x10];
9491 	u8         num_of_vfs[0x10];
9492 
9493 	u8         bdf0[0x10];
9494 	u8         reserved_at_b0[0x10];
9495 
9496 	u8         max_read_request_size[0x4];
9497 	u8         max_payload_size[0x4];
9498 	u8         reserved_at_c8[0x5];
9499 	u8         pwr_status[0x3];
9500 	u8         port_type[0x4];
9501 	u8         reserved_at_d4[0xb];
9502 	u8         lane_reversal[0x1];
9503 
9504 	u8         reserved_at_e0[0x14];
9505 	u8         pci_power[0xc];
9506 
9507 	u8         reserved_at_100[0x20];
9508 
9509 	u8         device_status[0x10];
9510 	u8         port_state[0x8];
9511 	u8         reserved_at_138[0x8];
9512 
9513 	u8         reserved_at_140[0x10];
9514 	u8         receiver_detect_result[0x10];
9515 
9516 	u8         reserved_at_160[0x20];
9517 };
9518 
9519 struct mlx5_ifc_mpcnt_reg_bits {
9520 	u8         reserved_at_0[0x8];
9521 	u8         pcie_index[0x8];
9522 	u8         reserved_at_10[0xa];
9523 	u8         grp[0x6];
9524 
9525 	u8         clr[0x1];
9526 	u8         reserved_at_21[0x1f];
9527 
9528 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9529 };
9530 
9531 struct mlx5_ifc_ppad_reg_bits {
9532 	u8         reserved_at_0[0x3];
9533 	u8         single_mac[0x1];
9534 	u8         reserved_at_4[0x4];
9535 	u8         local_port[0x8];
9536 	u8         mac_47_32[0x10];
9537 
9538 	u8         mac_31_0[0x20];
9539 
9540 	u8         reserved_at_40[0x40];
9541 };
9542 
9543 struct mlx5_ifc_pmtu_reg_bits {
9544 	u8         reserved_at_0[0x8];
9545 	u8         local_port[0x8];
9546 	u8         reserved_at_10[0x10];
9547 
9548 	u8         max_mtu[0x10];
9549 	u8         reserved_at_30[0x10];
9550 
9551 	u8         admin_mtu[0x10];
9552 	u8         reserved_at_50[0x10];
9553 
9554 	u8         oper_mtu[0x10];
9555 	u8         reserved_at_70[0x10];
9556 };
9557 
9558 struct mlx5_ifc_pmpr_reg_bits {
9559 	u8         reserved_at_0[0x8];
9560 	u8         module[0x8];
9561 	u8         reserved_at_10[0x10];
9562 
9563 	u8         reserved_at_20[0x18];
9564 	u8         attenuation_5g[0x8];
9565 
9566 	u8         reserved_at_40[0x18];
9567 	u8         attenuation_7g[0x8];
9568 
9569 	u8         reserved_at_60[0x18];
9570 	u8         attenuation_12g[0x8];
9571 };
9572 
9573 struct mlx5_ifc_pmpe_reg_bits {
9574 	u8         reserved_at_0[0x8];
9575 	u8         module[0x8];
9576 	u8         reserved_at_10[0xc];
9577 	u8         module_status[0x4];
9578 
9579 	u8         reserved_at_20[0x60];
9580 };
9581 
9582 struct mlx5_ifc_pmpc_reg_bits {
9583 	u8         module_state_updated[32][0x8];
9584 };
9585 
9586 struct mlx5_ifc_pmlpn_reg_bits {
9587 	u8         reserved_at_0[0x4];
9588 	u8         mlpn_status[0x4];
9589 	u8         local_port[0x8];
9590 	u8         reserved_at_10[0x10];
9591 
9592 	u8         e[0x1];
9593 	u8         reserved_at_21[0x1f];
9594 };
9595 
9596 struct mlx5_ifc_pmlp_reg_bits {
9597 	u8         rxtx[0x1];
9598 	u8         reserved_at_1[0x7];
9599 	u8         local_port[0x8];
9600 	u8         reserved_at_10[0x8];
9601 	u8         width[0x8];
9602 
9603 	u8         lane0_module_mapping[0x20];
9604 
9605 	u8         lane1_module_mapping[0x20];
9606 
9607 	u8         lane2_module_mapping[0x20];
9608 
9609 	u8         lane3_module_mapping[0x20];
9610 
9611 	u8         reserved_at_a0[0x160];
9612 };
9613 
9614 struct mlx5_ifc_pmaos_reg_bits {
9615 	u8         reserved_at_0[0x8];
9616 	u8         module[0x8];
9617 	u8         reserved_at_10[0x4];
9618 	u8         admin_status[0x4];
9619 	u8         reserved_at_18[0x4];
9620 	u8         oper_status[0x4];
9621 
9622 	u8         ase[0x1];
9623 	u8         ee[0x1];
9624 	u8         reserved_at_22[0x1c];
9625 	u8         e[0x2];
9626 
9627 	u8         reserved_at_40[0x40];
9628 };
9629 
9630 struct mlx5_ifc_plpc_reg_bits {
9631 	u8         reserved_at_0[0x4];
9632 	u8         profile_id[0xc];
9633 	u8         reserved_at_10[0x4];
9634 	u8         proto_mask[0x4];
9635 	u8         reserved_at_18[0x8];
9636 
9637 	u8         reserved_at_20[0x10];
9638 	u8         lane_speed[0x10];
9639 
9640 	u8         reserved_at_40[0x17];
9641 	u8         lpbf[0x1];
9642 	u8         fec_mode_policy[0x8];
9643 
9644 	u8         retransmission_capability[0x8];
9645 	u8         fec_mode_capability[0x18];
9646 
9647 	u8         retransmission_support_admin[0x8];
9648 	u8         fec_mode_support_admin[0x18];
9649 
9650 	u8         retransmission_request_admin[0x8];
9651 	u8         fec_mode_request_admin[0x18];
9652 
9653 	u8         reserved_at_c0[0x80];
9654 };
9655 
9656 struct mlx5_ifc_plib_reg_bits {
9657 	u8         reserved_at_0[0x8];
9658 	u8         local_port[0x8];
9659 	u8         reserved_at_10[0x8];
9660 	u8         ib_port[0x8];
9661 
9662 	u8         reserved_at_20[0x60];
9663 };
9664 
9665 struct mlx5_ifc_plbf_reg_bits {
9666 	u8         reserved_at_0[0x8];
9667 	u8         local_port[0x8];
9668 	u8         reserved_at_10[0xd];
9669 	u8         lbf_mode[0x3];
9670 
9671 	u8         reserved_at_20[0x20];
9672 };
9673 
9674 struct mlx5_ifc_pipg_reg_bits {
9675 	u8         reserved_at_0[0x8];
9676 	u8         local_port[0x8];
9677 	u8         reserved_at_10[0x10];
9678 
9679 	u8         dic[0x1];
9680 	u8         reserved_at_21[0x19];
9681 	u8         ipg[0x4];
9682 	u8         reserved_at_3e[0x2];
9683 };
9684 
9685 struct mlx5_ifc_pifr_reg_bits {
9686 	u8         reserved_at_0[0x8];
9687 	u8         local_port[0x8];
9688 	u8         reserved_at_10[0x10];
9689 
9690 	u8         reserved_at_20[0xe0];
9691 
9692 	u8         port_filter[8][0x20];
9693 
9694 	u8         port_filter_update_en[8][0x20];
9695 };
9696 
9697 struct mlx5_ifc_pfcc_reg_bits {
9698 	u8         reserved_at_0[0x8];
9699 	u8         local_port[0x8];
9700 	u8         reserved_at_10[0xb];
9701 	u8         ppan_mask_n[0x1];
9702 	u8         minor_stall_mask[0x1];
9703 	u8         critical_stall_mask[0x1];
9704 	u8         reserved_at_1e[0x2];
9705 
9706 	u8         ppan[0x4];
9707 	u8         reserved_at_24[0x4];
9708 	u8         prio_mask_tx[0x8];
9709 	u8         reserved_at_30[0x8];
9710 	u8         prio_mask_rx[0x8];
9711 
9712 	u8         pptx[0x1];
9713 	u8         aptx[0x1];
9714 	u8         pptx_mask_n[0x1];
9715 	u8         reserved_at_43[0x5];
9716 	u8         pfctx[0x8];
9717 	u8         reserved_at_50[0x10];
9718 
9719 	u8         pprx[0x1];
9720 	u8         aprx[0x1];
9721 	u8         pprx_mask_n[0x1];
9722 	u8         reserved_at_63[0x5];
9723 	u8         pfcrx[0x8];
9724 	u8         reserved_at_70[0x10];
9725 
9726 	u8         device_stall_minor_watermark[0x10];
9727 	u8         device_stall_critical_watermark[0x10];
9728 
9729 	u8         reserved_at_a0[0x60];
9730 };
9731 
9732 struct mlx5_ifc_pelc_reg_bits {
9733 	u8         op[0x4];
9734 	u8         reserved_at_4[0x4];
9735 	u8         local_port[0x8];
9736 	u8         reserved_at_10[0x10];
9737 
9738 	u8         op_admin[0x8];
9739 	u8         op_capability[0x8];
9740 	u8         op_request[0x8];
9741 	u8         op_active[0x8];
9742 
9743 	u8         admin[0x40];
9744 
9745 	u8         capability[0x40];
9746 
9747 	u8         request[0x40];
9748 
9749 	u8         active[0x40];
9750 
9751 	u8         reserved_at_140[0x80];
9752 };
9753 
9754 struct mlx5_ifc_peir_reg_bits {
9755 	u8         reserved_at_0[0x8];
9756 	u8         local_port[0x8];
9757 	u8         reserved_at_10[0x10];
9758 
9759 	u8         reserved_at_20[0xc];
9760 	u8         error_count[0x4];
9761 	u8         reserved_at_30[0x10];
9762 
9763 	u8         reserved_at_40[0xc];
9764 	u8         lane[0x4];
9765 	u8         reserved_at_50[0x8];
9766 	u8         error_type[0x8];
9767 };
9768 
9769 struct mlx5_ifc_mpegc_reg_bits {
9770 	u8         reserved_at_0[0x30];
9771 	u8         field_select[0x10];
9772 
9773 	u8         tx_overflow_sense[0x1];
9774 	u8         mark_cqe[0x1];
9775 	u8         mark_cnp[0x1];
9776 	u8         reserved_at_43[0x1b];
9777 	u8         tx_lossy_overflow_oper[0x2];
9778 
9779 	u8         reserved_at_60[0x100];
9780 };
9781 
9782 enum {
9783 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
9784 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
9785 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
9786 };
9787 
9788 struct mlx5_ifc_mtutc_reg_bits {
9789 	u8         reserved_at_0[0x1c];
9790 	u8         operation[0x4];
9791 
9792 	u8         freq_adjustment[0x20];
9793 
9794 	u8         reserved_at_40[0x40];
9795 
9796 	u8         utc_sec[0x20];
9797 
9798 	u8         reserved_at_a0[0x2];
9799 	u8         utc_nsec[0x1e];
9800 
9801 	u8         time_adjustment[0x20];
9802 };
9803 
9804 struct mlx5_ifc_pcam_enhanced_features_bits {
9805 	u8         reserved_at_0[0x68];
9806 	u8         fec_50G_per_lane_in_pplm[0x1];
9807 	u8         reserved_at_69[0x4];
9808 	u8         rx_icrc_encapsulated_counter[0x1];
9809 	u8	   reserved_at_6e[0x4];
9810 	u8         ptys_extended_ethernet[0x1];
9811 	u8	   reserved_at_73[0x3];
9812 	u8         pfcc_mask[0x1];
9813 	u8         reserved_at_77[0x3];
9814 	u8         per_lane_error_counters[0x1];
9815 	u8         rx_buffer_fullness_counters[0x1];
9816 	u8         ptys_connector_type[0x1];
9817 	u8         reserved_at_7d[0x1];
9818 	u8         ppcnt_discard_group[0x1];
9819 	u8         ppcnt_statistical_group[0x1];
9820 };
9821 
9822 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
9823 	u8         port_access_reg_cap_mask_127_to_96[0x20];
9824 	u8         port_access_reg_cap_mask_95_to_64[0x20];
9825 
9826 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
9827 	u8         pplm[0x1];
9828 	u8         port_access_reg_cap_mask_34_to_32[0x3];
9829 
9830 	u8         port_access_reg_cap_mask_31_to_13[0x13];
9831 	u8         pbmc[0x1];
9832 	u8         pptb[0x1];
9833 	u8         port_access_reg_cap_mask_10_to_09[0x2];
9834 	u8         ppcnt[0x1];
9835 	u8         port_access_reg_cap_mask_07_to_00[0x8];
9836 };
9837 
9838 struct mlx5_ifc_pcam_reg_bits {
9839 	u8         reserved_at_0[0x8];
9840 	u8         feature_group[0x8];
9841 	u8         reserved_at_10[0x8];
9842 	u8         access_reg_group[0x8];
9843 
9844 	u8         reserved_at_20[0x20];
9845 
9846 	union {
9847 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
9848 		u8         reserved_at_0[0x80];
9849 	} port_access_reg_cap_mask;
9850 
9851 	u8         reserved_at_c0[0x80];
9852 
9853 	union {
9854 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
9855 		u8         reserved_at_0[0x80];
9856 	} feature_cap_mask;
9857 
9858 	u8         reserved_at_1c0[0xc0];
9859 };
9860 
9861 struct mlx5_ifc_mcam_enhanced_features_bits {
9862 	u8         reserved_at_0[0x5d];
9863 	u8         mcia_32dwords[0x1];
9864 	u8         out_pulse_duration_ns[0x1];
9865 	u8         npps_period[0x1];
9866 	u8         reserved_at_60[0xa];
9867 	u8         reset_state[0x1];
9868 	u8         ptpcyc2realtime_modify[0x1];
9869 	u8         reserved_at_6c[0x2];
9870 	u8         pci_status_and_power[0x1];
9871 	u8         reserved_at_6f[0x5];
9872 	u8         mark_tx_action_cnp[0x1];
9873 	u8         mark_tx_action_cqe[0x1];
9874 	u8         dynamic_tx_overflow[0x1];
9875 	u8         reserved_at_77[0x4];
9876 	u8         pcie_outbound_stalled[0x1];
9877 	u8         tx_overflow_buffer_pkt[0x1];
9878 	u8         mtpps_enh_out_per_adj[0x1];
9879 	u8         mtpps_fs[0x1];
9880 	u8         pcie_performance_group[0x1];
9881 };
9882 
9883 struct mlx5_ifc_mcam_access_reg_bits {
9884 	u8         reserved_at_0[0x1c];
9885 	u8         mcda[0x1];
9886 	u8         mcc[0x1];
9887 	u8         mcqi[0x1];
9888 	u8         mcqs[0x1];
9889 
9890 	u8         regs_95_to_87[0x9];
9891 	u8         mpegc[0x1];
9892 	u8         mtutc[0x1];
9893 	u8         regs_84_to_68[0x11];
9894 	u8         tracer_registers[0x4];
9895 
9896 	u8         regs_63_to_46[0x12];
9897 	u8         mrtc[0x1];
9898 	u8         regs_44_to_32[0xd];
9899 
9900 	u8         regs_31_to_0[0x20];
9901 };
9902 
9903 struct mlx5_ifc_mcam_access_reg_bits1 {
9904 	u8         regs_127_to_96[0x20];
9905 
9906 	u8         regs_95_to_64[0x20];
9907 
9908 	u8         regs_63_to_32[0x20];
9909 
9910 	u8         regs_31_to_0[0x20];
9911 };
9912 
9913 struct mlx5_ifc_mcam_access_reg_bits2 {
9914 	u8         regs_127_to_99[0x1d];
9915 	u8         mirc[0x1];
9916 	u8         regs_97_to_96[0x2];
9917 
9918 	u8         regs_95_to_64[0x20];
9919 
9920 	u8         regs_63_to_32[0x20];
9921 
9922 	u8         regs_31_to_0[0x20];
9923 };
9924 
9925 struct mlx5_ifc_mcam_reg_bits {
9926 	u8         reserved_at_0[0x8];
9927 	u8         feature_group[0x8];
9928 	u8         reserved_at_10[0x8];
9929 	u8         access_reg_group[0x8];
9930 
9931 	u8         reserved_at_20[0x20];
9932 
9933 	union {
9934 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
9935 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9936 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9937 		u8         reserved_at_0[0x80];
9938 	} mng_access_reg_cap_mask;
9939 
9940 	u8         reserved_at_c0[0x80];
9941 
9942 	union {
9943 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9944 		u8         reserved_at_0[0x80];
9945 	} mng_feature_cap_mask;
9946 
9947 	u8         reserved_at_1c0[0x80];
9948 };
9949 
9950 struct mlx5_ifc_qcam_access_reg_cap_mask {
9951 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
9952 	u8         qpdpm[0x1];
9953 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
9954 	u8         qdpm[0x1];
9955 	u8         qpts[0x1];
9956 	u8         qcap[0x1];
9957 	u8         qcam_access_reg_cap_mask_0[0x1];
9958 };
9959 
9960 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9961 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
9962 	u8         qpts_trust_both[0x1];
9963 };
9964 
9965 struct mlx5_ifc_qcam_reg_bits {
9966 	u8         reserved_at_0[0x8];
9967 	u8         feature_group[0x8];
9968 	u8         reserved_at_10[0x8];
9969 	u8         access_reg_group[0x8];
9970 	u8         reserved_at_20[0x20];
9971 
9972 	union {
9973 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9974 		u8  reserved_at_0[0x80];
9975 	} qos_access_reg_cap_mask;
9976 
9977 	u8         reserved_at_c0[0x80];
9978 
9979 	union {
9980 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9981 		u8  reserved_at_0[0x80];
9982 	} qos_feature_cap_mask;
9983 
9984 	u8         reserved_at_1c0[0x80];
9985 };
9986 
9987 struct mlx5_ifc_core_dump_reg_bits {
9988 	u8         reserved_at_0[0x18];
9989 	u8         core_dump_type[0x8];
9990 
9991 	u8         reserved_at_20[0x30];
9992 	u8         vhca_id[0x10];
9993 
9994 	u8         reserved_at_60[0x8];
9995 	u8         qpn[0x18];
9996 	u8         reserved_at_80[0x180];
9997 };
9998 
9999 struct mlx5_ifc_pcap_reg_bits {
10000 	u8         reserved_at_0[0x8];
10001 	u8         local_port[0x8];
10002 	u8         reserved_at_10[0x10];
10003 
10004 	u8         port_capability_mask[4][0x20];
10005 };
10006 
10007 struct mlx5_ifc_paos_reg_bits {
10008 	u8         swid[0x8];
10009 	u8         local_port[0x8];
10010 	u8         reserved_at_10[0x4];
10011 	u8         admin_status[0x4];
10012 	u8         reserved_at_18[0x4];
10013 	u8         oper_status[0x4];
10014 
10015 	u8         ase[0x1];
10016 	u8         ee[0x1];
10017 	u8         reserved_at_22[0x1c];
10018 	u8         e[0x2];
10019 
10020 	u8         reserved_at_40[0x40];
10021 };
10022 
10023 struct mlx5_ifc_pamp_reg_bits {
10024 	u8         reserved_at_0[0x8];
10025 	u8         opamp_group[0x8];
10026 	u8         reserved_at_10[0xc];
10027 	u8         opamp_group_type[0x4];
10028 
10029 	u8         start_index[0x10];
10030 	u8         reserved_at_30[0x4];
10031 	u8         num_of_indices[0xc];
10032 
10033 	u8         index_data[18][0x10];
10034 };
10035 
10036 struct mlx5_ifc_pcmr_reg_bits {
10037 	u8         reserved_at_0[0x8];
10038 	u8         local_port[0x8];
10039 	u8         reserved_at_10[0x10];
10040 
10041 	u8         entropy_force_cap[0x1];
10042 	u8         entropy_calc_cap[0x1];
10043 	u8         entropy_gre_calc_cap[0x1];
10044 	u8         reserved_at_23[0xf];
10045 	u8         rx_ts_over_crc_cap[0x1];
10046 	u8         reserved_at_33[0xb];
10047 	u8         fcs_cap[0x1];
10048 	u8         reserved_at_3f[0x1];
10049 
10050 	u8         entropy_force[0x1];
10051 	u8         entropy_calc[0x1];
10052 	u8         entropy_gre_calc[0x1];
10053 	u8         reserved_at_43[0xf];
10054 	u8         rx_ts_over_crc[0x1];
10055 	u8         reserved_at_53[0xb];
10056 	u8         fcs_chk[0x1];
10057 	u8         reserved_at_5f[0x1];
10058 };
10059 
10060 struct mlx5_ifc_lane_2_module_mapping_bits {
10061 	u8         reserved_at_0[0x4];
10062 	u8         rx_lane[0x4];
10063 	u8         reserved_at_8[0x4];
10064 	u8         tx_lane[0x4];
10065 	u8         reserved_at_10[0x8];
10066 	u8         module[0x8];
10067 };
10068 
10069 struct mlx5_ifc_bufferx_reg_bits {
10070 	u8         reserved_at_0[0x6];
10071 	u8         lossy[0x1];
10072 	u8         epsb[0x1];
10073 	u8         reserved_at_8[0x8];
10074 	u8         size[0x10];
10075 
10076 	u8         xoff_threshold[0x10];
10077 	u8         xon_threshold[0x10];
10078 };
10079 
10080 struct mlx5_ifc_set_node_in_bits {
10081 	u8         node_description[64][0x8];
10082 };
10083 
10084 struct mlx5_ifc_register_power_settings_bits {
10085 	u8         reserved_at_0[0x18];
10086 	u8         power_settings_level[0x8];
10087 
10088 	u8         reserved_at_20[0x60];
10089 };
10090 
10091 struct mlx5_ifc_register_host_endianness_bits {
10092 	u8         he[0x1];
10093 	u8         reserved_at_1[0x1f];
10094 
10095 	u8         reserved_at_20[0x60];
10096 };
10097 
10098 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10099 	u8         reserved_at_0[0x20];
10100 
10101 	u8         mkey[0x20];
10102 
10103 	u8         addressh_63_32[0x20];
10104 
10105 	u8         addressl_31_0[0x20];
10106 };
10107 
10108 struct mlx5_ifc_ud_adrs_vector_bits {
10109 	u8         dc_key[0x40];
10110 
10111 	u8         ext[0x1];
10112 	u8         reserved_at_41[0x7];
10113 	u8         destination_qp_dct[0x18];
10114 
10115 	u8         static_rate[0x4];
10116 	u8         sl_eth_prio[0x4];
10117 	u8         fl[0x1];
10118 	u8         mlid[0x7];
10119 	u8         rlid_udp_sport[0x10];
10120 
10121 	u8         reserved_at_80[0x20];
10122 
10123 	u8         rmac_47_16[0x20];
10124 
10125 	u8         rmac_15_0[0x10];
10126 	u8         tclass[0x8];
10127 	u8         hop_limit[0x8];
10128 
10129 	u8         reserved_at_e0[0x1];
10130 	u8         grh[0x1];
10131 	u8         reserved_at_e2[0x2];
10132 	u8         src_addr_index[0x8];
10133 	u8         flow_label[0x14];
10134 
10135 	u8         rgid_rip[16][0x8];
10136 };
10137 
10138 struct mlx5_ifc_pages_req_event_bits {
10139 	u8         reserved_at_0[0x10];
10140 	u8         function_id[0x10];
10141 
10142 	u8         num_pages[0x20];
10143 
10144 	u8         reserved_at_40[0xa0];
10145 };
10146 
10147 struct mlx5_ifc_eqe_bits {
10148 	u8         reserved_at_0[0x8];
10149 	u8         event_type[0x8];
10150 	u8         reserved_at_10[0x8];
10151 	u8         event_sub_type[0x8];
10152 
10153 	u8         reserved_at_20[0xe0];
10154 
10155 	union mlx5_ifc_event_auto_bits event_data;
10156 
10157 	u8         reserved_at_1e0[0x10];
10158 	u8         signature[0x8];
10159 	u8         reserved_at_1f8[0x7];
10160 	u8         owner[0x1];
10161 };
10162 
10163 enum {
10164 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10165 };
10166 
10167 struct mlx5_ifc_cmd_queue_entry_bits {
10168 	u8         type[0x8];
10169 	u8         reserved_at_8[0x18];
10170 
10171 	u8         input_length[0x20];
10172 
10173 	u8         input_mailbox_pointer_63_32[0x20];
10174 
10175 	u8         input_mailbox_pointer_31_9[0x17];
10176 	u8         reserved_at_77[0x9];
10177 
10178 	u8         command_input_inline_data[16][0x8];
10179 
10180 	u8         command_output_inline_data[16][0x8];
10181 
10182 	u8         output_mailbox_pointer_63_32[0x20];
10183 
10184 	u8         output_mailbox_pointer_31_9[0x17];
10185 	u8         reserved_at_1b7[0x9];
10186 
10187 	u8         output_length[0x20];
10188 
10189 	u8         token[0x8];
10190 	u8         signature[0x8];
10191 	u8         reserved_at_1f0[0x8];
10192 	u8         status[0x7];
10193 	u8         ownership[0x1];
10194 };
10195 
10196 struct mlx5_ifc_cmd_out_bits {
10197 	u8         status[0x8];
10198 	u8         reserved_at_8[0x18];
10199 
10200 	u8         syndrome[0x20];
10201 
10202 	u8         command_output[0x20];
10203 };
10204 
10205 struct mlx5_ifc_cmd_in_bits {
10206 	u8         opcode[0x10];
10207 	u8         reserved_at_10[0x10];
10208 
10209 	u8         reserved_at_20[0x10];
10210 	u8         op_mod[0x10];
10211 
10212 	u8         command[][0x20];
10213 };
10214 
10215 struct mlx5_ifc_cmd_if_box_bits {
10216 	u8         mailbox_data[512][0x8];
10217 
10218 	u8         reserved_at_1000[0x180];
10219 
10220 	u8         next_pointer_63_32[0x20];
10221 
10222 	u8         next_pointer_31_10[0x16];
10223 	u8         reserved_at_11b6[0xa];
10224 
10225 	u8         block_number[0x20];
10226 
10227 	u8         reserved_at_11e0[0x8];
10228 	u8         token[0x8];
10229 	u8         ctrl_signature[0x8];
10230 	u8         signature[0x8];
10231 };
10232 
10233 struct mlx5_ifc_mtt_bits {
10234 	u8         ptag_63_32[0x20];
10235 
10236 	u8         ptag_31_8[0x18];
10237 	u8         reserved_at_38[0x6];
10238 	u8         wr_en[0x1];
10239 	u8         rd_en[0x1];
10240 };
10241 
10242 struct mlx5_ifc_query_wol_rol_out_bits {
10243 	u8         status[0x8];
10244 	u8         reserved_at_8[0x18];
10245 
10246 	u8         syndrome[0x20];
10247 
10248 	u8         reserved_at_40[0x10];
10249 	u8         rol_mode[0x8];
10250 	u8         wol_mode[0x8];
10251 
10252 	u8         reserved_at_60[0x20];
10253 };
10254 
10255 struct mlx5_ifc_query_wol_rol_in_bits {
10256 	u8         opcode[0x10];
10257 	u8         reserved_at_10[0x10];
10258 
10259 	u8         reserved_at_20[0x10];
10260 	u8         op_mod[0x10];
10261 
10262 	u8         reserved_at_40[0x40];
10263 };
10264 
10265 struct mlx5_ifc_set_wol_rol_out_bits {
10266 	u8         status[0x8];
10267 	u8         reserved_at_8[0x18];
10268 
10269 	u8         syndrome[0x20];
10270 
10271 	u8         reserved_at_40[0x40];
10272 };
10273 
10274 struct mlx5_ifc_set_wol_rol_in_bits {
10275 	u8         opcode[0x10];
10276 	u8         reserved_at_10[0x10];
10277 
10278 	u8         reserved_at_20[0x10];
10279 	u8         op_mod[0x10];
10280 
10281 	u8         rol_mode_valid[0x1];
10282 	u8         wol_mode_valid[0x1];
10283 	u8         reserved_at_42[0xe];
10284 	u8         rol_mode[0x8];
10285 	u8         wol_mode[0x8];
10286 
10287 	u8         reserved_at_60[0x20];
10288 };
10289 
10290 enum {
10291 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10292 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10293 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10294 };
10295 
10296 enum {
10297 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10298 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10299 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10300 };
10301 
10302 enum {
10303 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10304 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10305 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10306 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10307 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10308 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10309 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10310 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10311 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10312 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10313 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10314 };
10315 
10316 struct mlx5_ifc_initial_seg_bits {
10317 	u8         fw_rev_minor[0x10];
10318 	u8         fw_rev_major[0x10];
10319 
10320 	u8         cmd_interface_rev[0x10];
10321 	u8         fw_rev_subminor[0x10];
10322 
10323 	u8         reserved_at_40[0x40];
10324 
10325 	u8         cmdq_phy_addr_63_32[0x20];
10326 
10327 	u8         cmdq_phy_addr_31_12[0x14];
10328 	u8         reserved_at_b4[0x2];
10329 	u8         nic_interface[0x2];
10330 	u8         log_cmdq_size[0x4];
10331 	u8         log_cmdq_stride[0x4];
10332 
10333 	u8         command_doorbell_vector[0x20];
10334 
10335 	u8         reserved_at_e0[0xf00];
10336 
10337 	u8         initializing[0x1];
10338 	u8         reserved_at_fe1[0x4];
10339 	u8         nic_interface_supported[0x3];
10340 	u8         embedded_cpu[0x1];
10341 	u8         reserved_at_fe9[0x17];
10342 
10343 	struct mlx5_ifc_health_buffer_bits health_buffer;
10344 
10345 	u8         no_dram_nic_offset[0x20];
10346 
10347 	u8         reserved_at_1220[0x6e40];
10348 
10349 	u8         reserved_at_8060[0x1f];
10350 	u8         clear_int[0x1];
10351 
10352 	u8         health_syndrome[0x8];
10353 	u8         health_counter[0x18];
10354 
10355 	u8         reserved_at_80a0[0x17fc0];
10356 };
10357 
10358 struct mlx5_ifc_mtpps_reg_bits {
10359 	u8         reserved_at_0[0xc];
10360 	u8         cap_number_of_pps_pins[0x4];
10361 	u8         reserved_at_10[0x4];
10362 	u8         cap_max_num_of_pps_in_pins[0x4];
10363 	u8         reserved_at_18[0x4];
10364 	u8         cap_max_num_of_pps_out_pins[0x4];
10365 
10366 	u8         reserved_at_20[0x13];
10367 	u8         cap_log_min_npps_period[0x5];
10368 	u8         reserved_at_38[0x3];
10369 	u8         cap_log_min_out_pulse_duration_ns[0x5];
10370 
10371 	u8         reserved_at_40[0x4];
10372 	u8         cap_pin_3_mode[0x4];
10373 	u8         reserved_at_48[0x4];
10374 	u8         cap_pin_2_mode[0x4];
10375 	u8         reserved_at_50[0x4];
10376 	u8         cap_pin_1_mode[0x4];
10377 	u8         reserved_at_58[0x4];
10378 	u8         cap_pin_0_mode[0x4];
10379 
10380 	u8         reserved_at_60[0x4];
10381 	u8         cap_pin_7_mode[0x4];
10382 	u8         reserved_at_68[0x4];
10383 	u8         cap_pin_6_mode[0x4];
10384 	u8         reserved_at_70[0x4];
10385 	u8         cap_pin_5_mode[0x4];
10386 	u8         reserved_at_78[0x4];
10387 	u8         cap_pin_4_mode[0x4];
10388 
10389 	u8         field_select[0x20];
10390 	u8         reserved_at_a0[0x20];
10391 
10392 	u8         npps_period[0x40];
10393 
10394 	u8         enable[0x1];
10395 	u8         reserved_at_101[0xb];
10396 	u8         pattern[0x4];
10397 	u8         reserved_at_110[0x4];
10398 	u8         pin_mode[0x4];
10399 	u8         pin[0x8];
10400 
10401 	u8         reserved_at_120[0x2];
10402 	u8         out_pulse_duration_ns[0x1e];
10403 
10404 	u8         time_stamp[0x40];
10405 
10406 	u8         out_pulse_duration[0x10];
10407 	u8         out_periodic_adjustment[0x10];
10408 	u8         enhanced_out_periodic_adjustment[0x20];
10409 
10410 	u8         reserved_at_1c0[0x20];
10411 };
10412 
10413 struct mlx5_ifc_mtppse_reg_bits {
10414 	u8         reserved_at_0[0x18];
10415 	u8         pin[0x8];
10416 	u8         event_arm[0x1];
10417 	u8         reserved_at_21[0x1b];
10418 	u8         event_generation_mode[0x4];
10419 	u8         reserved_at_40[0x40];
10420 };
10421 
10422 struct mlx5_ifc_mcqs_reg_bits {
10423 	u8         last_index_flag[0x1];
10424 	u8         reserved_at_1[0x7];
10425 	u8         fw_device[0x8];
10426 	u8         component_index[0x10];
10427 
10428 	u8         reserved_at_20[0x10];
10429 	u8         identifier[0x10];
10430 
10431 	u8         reserved_at_40[0x17];
10432 	u8         component_status[0x5];
10433 	u8         component_update_state[0x4];
10434 
10435 	u8         last_update_state_changer_type[0x4];
10436 	u8         last_update_state_changer_host_id[0x4];
10437 	u8         reserved_at_68[0x18];
10438 };
10439 
10440 struct mlx5_ifc_mcqi_cap_bits {
10441 	u8         supported_info_bitmask[0x20];
10442 
10443 	u8         component_size[0x20];
10444 
10445 	u8         max_component_size[0x20];
10446 
10447 	u8         log_mcda_word_size[0x4];
10448 	u8         reserved_at_64[0xc];
10449 	u8         mcda_max_write_size[0x10];
10450 
10451 	u8         rd_en[0x1];
10452 	u8         reserved_at_81[0x1];
10453 	u8         match_chip_id[0x1];
10454 	u8         match_psid[0x1];
10455 	u8         check_user_timestamp[0x1];
10456 	u8         match_base_guid_mac[0x1];
10457 	u8         reserved_at_86[0x1a];
10458 };
10459 
10460 struct mlx5_ifc_mcqi_version_bits {
10461 	u8         reserved_at_0[0x2];
10462 	u8         build_time_valid[0x1];
10463 	u8         user_defined_time_valid[0x1];
10464 	u8         reserved_at_4[0x14];
10465 	u8         version_string_length[0x8];
10466 
10467 	u8         version[0x20];
10468 
10469 	u8         build_time[0x40];
10470 
10471 	u8         user_defined_time[0x40];
10472 
10473 	u8         build_tool_version[0x20];
10474 
10475 	u8         reserved_at_e0[0x20];
10476 
10477 	u8         version_string[92][0x8];
10478 };
10479 
10480 struct mlx5_ifc_mcqi_activation_method_bits {
10481 	u8         pending_server_ac_power_cycle[0x1];
10482 	u8         pending_server_dc_power_cycle[0x1];
10483 	u8         pending_server_reboot[0x1];
10484 	u8         pending_fw_reset[0x1];
10485 	u8         auto_activate[0x1];
10486 	u8         all_hosts_sync[0x1];
10487 	u8         device_hw_reset[0x1];
10488 	u8         reserved_at_7[0x19];
10489 };
10490 
10491 union mlx5_ifc_mcqi_reg_data_bits {
10492 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10493 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10494 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10495 };
10496 
10497 struct mlx5_ifc_mcqi_reg_bits {
10498 	u8         read_pending_component[0x1];
10499 	u8         reserved_at_1[0xf];
10500 	u8         component_index[0x10];
10501 
10502 	u8         reserved_at_20[0x20];
10503 
10504 	u8         reserved_at_40[0x1b];
10505 	u8         info_type[0x5];
10506 
10507 	u8         info_size[0x20];
10508 
10509 	u8         offset[0x20];
10510 
10511 	u8         reserved_at_a0[0x10];
10512 	u8         data_size[0x10];
10513 
10514 	union mlx5_ifc_mcqi_reg_data_bits data[];
10515 };
10516 
10517 struct mlx5_ifc_mcc_reg_bits {
10518 	u8         reserved_at_0[0x4];
10519 	u8         time_elapsed_since_last_cmd[0xc];
10520 	u8         reserved_at_10[0x8];
10521 	u8         instruction[0x8];
10522 
10523 	u8         reserved_at_20[0x10];
10524 	u8         component_index[0x10];
10525 
10526 	u8         reserved_at_40[0x8];
10527 	u8         update_handle[0x18];
10528 
10529 	u8         handle_owner_type[0x4];
10530 	u8         handle_owner_host_id[0x4];
10531 	u8         reserved_at_68[0x1];
10532 	u8         control_progress[0x7];
10533 	u8         error_code[0x8];
10534 	u8         reserved_at_78[0x4];
10535 	u8         control_state[0x4];
10536 
10537 	u8         component_size[0x20];
10538 
10539 	u8         reserved_at_a0[0x60];
10540 };
10541 
10542 struct mlx5_ifc_mcda_reg_bits {
10543 	u8         reserved_at_0[0x8];
10544 	u8         update_handle[0x18];
10545 
10546 	u8         offset[0x20];
10547 
10548 	u8         reserved_at_40[0x10];
10549 	u8         size[0x10];
10550 
10551 	u8         reserved_at_60[0x20];
10552 
10553 	u8         data[][0x20];
10554 };
10555 
10556 enum {
10557 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10558 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10559 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10560 	MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3,
10561 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10562 };
10563 
10564 enum {
10565 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10566 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10567 };
10568 
10569 enum {
10570 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10571 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10572 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10573 };
10574 
10575 struct mlx5_ifc_mfrl_reg_bits {
10576 	u8         reserved_at_0[0x20];
10577 
10578 	u8         reserved_at_20[0x2];
10579 	u8         pci_sync_for_fw_update_start[0x1];
10580 	u8         pci_sync_for_fw_update_resp[0x2];
10581 	u8         rst_type_sel[0x3];
10582 	u8         reserved_at_28[0x4];
10583 	u8         reset_state[0x4];
10584 	u8         reset_type[0x8];
10585 	u8         reset_level[0x8];
10586 };
10587 
10588 struct mlx5_ifc_mirc_reg_bits {
10589 	u8         reserved_at_0[0x18];
10590 	u8         status_code[0x8];
10591 
10592 	u8         reserved_at_20[0x20];
10593 };
10594 
10595 struct mlx5_ifc_pddr_monitor_opcode_bits {
10596 	u8         reserved_at_0[0x10];
10597 	u8         monitor_opcode[0x10];
10598 };
10599 
10600 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10601 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10602 	u8         reserved_at_0[0x20];
10603 };
10604 
10605 enum {
10606 	/* Monitor opcodes */
10607 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10608 };
10609 
10610 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10611 	u8         reserved_at_0[0x10];
10612 	u8         group_opcode[0x10];
10613 
10614 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10615 
10616 	u8         reserved_at_40[0x20];
10617 
10618 	u8         status_message[59][0x20];
10619 };
10620 
10621 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10622 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10623 	u8         reserved_at_0[0x7c0];
10624 };
10625 
10626 enum {
10627 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10628 };
10629 
10630 struct mlx5_ifc_pddr_reg_bits {
10631 	u8         reserved_at_0[0x8];
10632 	u8         local_port[0x8];
10633 	u8         pnat[0x2];
10634 	u8         reserved_at_12[0xe];
10635 
10636 	u8         reserved_at_20[0x18];
10637 	u8         page_select[0x8];
10638 
10639 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10640 };
10641 
10642 struct mlx5_ifc_mrtc_reg_bits {
10643 	u8         time_synced[0x1];
10644 	u8         reserved_at_1[0x1f];
10645 
10646 	u8         reserved_at_20[0x20];
10647 
10648 	u8         time_h[0x20];
10649 
10650 	u8         time_l[0x20];
10651 };
10652 
10653 union mlx5_ifc_ports_control_registers_document_bits {
10654 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10655 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10656 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10657 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10658 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10659 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10660 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10661 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10662 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10663 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10664 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10665 	struct mlx5_ifc_paos_reg_bits paos_reg;
10666 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10667 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10668 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
10669 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10670 	struct mlx5_ifc_peir_reg_bits peir_reg;
10671 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10672 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10673 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10674 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10675 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10676 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10677 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10678 	struct mlx5_ifc_plib_reg_bits plib_reg;
10679 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10680 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10681 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10682 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10683 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10684 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10685 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10686 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10687 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10688 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10689 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
10690 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10691 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10692 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10693 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10694 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10695 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10696 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10697 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10698 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10699 	struct mlx5_ifc_pude_reg_bits pude_reg;
10700 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10701 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10702 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10703 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
10704 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
10705 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
10706 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
10707 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
10708 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
10709 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
10710 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
10711 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
10712 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
10713 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
10714 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
10715 	u8         reserved_at_0[0x60e0];
10716 };
10717 
10718 union mlx5_ifc_debug_enhancements_document_bits {
10719 	struct mlx5_ifc_health_buffer_bits health_buffer;
10720 	u8         reserved_at_0[0x200];
10721 };
10722 
10723 union mlx5_ifc_uplink_pci_interface_document_bits {
10724 	struct mlx5_ifc_initial_seg_bits initial_seg;
10725 	u8         reserved_at_0[0x20060];
10726 };
10727 
10728 struct mlx5_ifc_set_flow_table_root_out_bits {
10729 	u8         status[0x8];
10730 	u8         reserved_at_8[0x18];
10731 
10732 	u8         syndrome[0x20];
10733 
10734 	u8         reserved_at_40[0x40];
10735 };
10736 
10737 struct mlx5_ifc_set_flow_table_root_in_bits {
10738 	u8         opcode[0x10];
10739 	u8         reserved_at_10[0x10];
10740 
10741 	u8         reserved_at_20[0x10];
10742 	u8         op_mod[0x10];
10743 
10744 	u8         other_vport[0x1];
10745 	u8         reserved_at_41[0xf];
10746 	u8         vport_number[0x10];
10747 
10748 	u8         reserved_at_60[0x20];
10749 
10750 	u8         table_type[0x8];
10751 	u8         reserved_at_88[0x7];
10752 	u8         table_of_other_vport[0x1];
10753 	u8         table_vport_number[0x10];
10754 
10755 	u8         reserved_at_a0[0x8];
10756 	u8         table_id[0x18];
10757 
10758 	u8         reserved_at_c0[0x8];
10759 	u8         underlay_qpn[0x18];
10760 	u8         table_eswitch_owner_vhca_id_valid[0x1];
10761 	u8         reserved_at_e1[0xf];
10762 	u8         table_eswitch_owner_vhca_id[0x10];
10763 	u8         reserved_at_100[0x100];
10764 };
10765 
10766 enum {
10767 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
10768 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
10769 };
10770 
10771 struct mlx5_ifc_modify_flow_table_out_bits {
10772 	u8         status[0x8];
10773 	u8         reserved_at_8[0x18];
10774 
10775 	u8         syndrome[0x20];
10776 
10777 	u8         reserved_at_40[0x40];
10778 };
10779 
10780 struct mlx5_ifc_modify_flow_table_in_bits {
10781 	u8         opcode[0x10];
10782 	u8         reserved_at_10[0x10];
10783 
10784 	u8         reserved_at_20[0x10];
10785 	u8         op_mod[0x10];
10786 
10787 	u8         other_vport[0x1];
10788 	u8         reserved_at_41[0xf];
10789 	u8         vport_number[0x10];
10790 
10791 	u8         reserved_at_60[0x10];
10792 	u8         modify_field_select[0x10];
10793 
10794 	u8         table_type[0x8];
10795 	u8         reserved_at_88[0x18];
10796 
10797 	u8         reserved_at_a0[0x8];
10798 	u8         table_id[0x18];
10799 
10800 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
10801 };
10802 
10803 struct mlx5_ifc_ets_tcn_config_reg_bits {
10804 	u8         g[0x1];
10805 	u8         b[0x1];
10806 	u8         r[0x1];
10807 	u8         reserved_at_3[0x9];
10808 	u8         group[0x4];
10809 	u8         reserved_at_10[0x9];
10810 	u8         bw_allocation[0x7];
10811 
10812 	u8         reserved_at_20[0xc];
10813 	u8         max_bw_units[0x4];
10814 	u8         reserved_at_30[0x8];
10815 	u8         max_bw_value[0x8];
10816 };
10817 
10818 struct mlx5_ifc_ets_global_config_reg_bits {
10819 	u8         reserved_at_0[0x2];
10820 	u8         r[0x1];
10821 	u8         reserved_at_3[0x1d];
10822 
10823 	u8         reserved_at_20[0xc];
10824 	u8         max_bw_units[0x4];
10825 	u8         reserved_at_30[0x8];
10826 	u8         max_bw_value[0x8];
10827 };
10828 
10829 struct mlx5_ifc_qetc_reg_bits {
10830 	u8                                         reserved_at_0[0x8];
10831 	u8                                         port_number[0x8];
10832 	u8                                         reserved_at_10[0x30];
10833 
10834 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
10835 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
10836 };
10837 
10838 struct mlx5_ifc_qpdpm_dscp_reg_bits {
10839 	u8         e[0x1];
10840 	u8         reserved_at_01[0x0b];
10841 	u8         prio[0x04];
10842 };
10843 
10844 struct mlx5_ifc_qpdpm_reg_bits {
10845 	u8                                     reserved_at_0[0x8];
10846 	u8                                     local_port[0x8];
10847 	u8                                     reserved_at_10[0x10];
10848 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
10849 };
10850 
10851 struct mlx5_ifc_qpts_reg_bits {
10852 	u8         reserved_at_0[0x8];
10853 	u8         local_port[0x8];
10854 	u8         reserved_at_10[0x2d];
10855 	u8         trust_state[0x3];
10856 };
10857 
10858 struct mlx5_ifc_pptb_reg_bits {
10859 	u8         reserved_at_0[0x2];
10860 	u8         mm[0x2];
10861 	u8         reserved_at_4[0x4];
10862 	u8         local_port[0x8];
10863 	u8         reserved_at_10[0x6];
10864 	u8         cm[0x1];
10865 	u8         um[0x1];
10866 	u8         pm[0x8];
10867 
10868 	u8         prio_x_buff[0x20];
10869 
10870 	u8         pm_msb[0x8];
10871 	u8         reserved_at_48[0x10];
10872 	u8         ctrl_buff[0x4];
10873 	u8         untagged_buff[0x4];
10874 };
10875 
10876 struct mlx5_ifc_sbcam_reg_bits {
10877 	u8         reserved_at_0[0x8];
10878 	u8         feature_group[0x8];
10879 	u8         reserved_at_10[0x8];
10880 	u8         access_reg_group[0x8];
10881 
10882 	u8         reserved_at_20[0x20];
10883 
10884 	u8         sb_access_reg_cap_mask[4][0x20];
10885 
10886 	u8         reserved_at_c0[0x80];
10887 
10888 	u8         sb_feature_cap_mask[4][0x20];
10889 
10890 	u8         reserved_at_1c0[0x40];
10891 
10892 	u8         cap_total_buffer_size[0x20];
10893 
10894 	u8         cap_cell_size[0x10];
10895 	u8         cap_max_pg_buffers[0x8];
10896 	u8         cap_num_pool_supported[0x8];
10897 
10898 	u8         reserved_at_240[0x8];
10899 	u8         cap_sbsr_stat_size[0x8];
10900 	u8         cap_max_tclass_data[0x8];
10901 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
10902 };
10903 
10904 struct mlx5_ifc_pbmc_reg_bits {
10905 	u8         reserved_at_0[0x8];
10906 	u8         local_port[0x8];
10907 	u8         reserved_at_10[0x10];
10908 
10909 	u8         xoff_timer_value[0x10];
10910 	u8         xoff_refresh[0x10];
10911 
10912 	u8         reserved_at_40[0x9];
10913 	u8         fullness_threshold[0x7];
10914 	u8         port_buffer_size[0x10];
10915 
10916 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
10917 
10918 	u8         reserved_at_2e0[0x80];
10919 };
10920 
10921 struct mlx5_ifc_qtct_reg_bits {
10922 	u8         reserved_at_0[0x8];
10923 	u8         port_number[0x8];
10924 	u8         reserved_at_10[0xd];
10925 	u8         prio[0x3];
10926 
10927 	u8         reserved_at_20[0x1d];
10928 	u8         tclass[0x3];
10929 };
10930 
10931 struct mlx5_ifc_mcia_reg_bits {
10932 	u8         l[0x1];
10933 	u8         reserved_at_1[0x7];
10934 	u8         module[0x8];
10935 	u8         reserved_at_10[0x8];
10936 	u8         status[0x8];
10937 
10938 	u8         i2c_device_address[0x8];
10939 	u8         page_number[0x8];
10940 	u8         device_address[0x10];
10941 
10942 	u8         reserved_at_40[0x10];
10943 	u8         size[0x10];
10944 
10945 	u8         reserved_at_60[0x20];
10946 
10947 	u8         dword_0[0x20];
10948 	u8         dword_1[0x20];
10949 	u8         dword_2[0x20];
10950 	u8         dword_3[0x20];
10951 	u8         dword_4[0x20];
10952 	u8         dword_5[0x20];
10953 	u8         dword_6[0x20];
10954 	u8         dword_7[0x20];
10955 	u8         dword_8[0x20];
10956 	u8         dword_9[0x20];
10957 	u8         dword_10[0x20];
10958 	u8         dword_11[0x20];
10959 };
10960 
10961 struct mlx5_ifc_dcbx_param_bits {
10962 	u8         dcbx_cee_cap[0x1];
10963 	u8         dcbx_ieee_cap[0x1];
10964 	u8         dcbx_standby_cap[0x1];
10965 	u8         reserved_at_3[0x5];
10966 	u8         port_number[0x8];
10967 	u8         reserved_at_10[0xa];
10968 	u8         max_application_table_size[6];
10969 	u8         reserved_at_20[0x15];
10970 	u8         version_oper[0x3];
10971 	u8         reserved_at_38[5];
10972 	u8         version_admin[0x3];
10973 	u8         willing_admin[0x1];
10974 	u8         reserved_at_41[0x3];
10975 	u8         pfc_cap_oper[0x4];
10976 	u8         reserved_at_48[0x4];
10977 	u8         pfc_cap_admin[0x4];
10978 	u8         reserved_at_50[0x4];
10979 	u8         num_of_tc_oper[0x4];
10980 	u8         reserved_at_58[0x4];
10981 	u8         num_of_tc_admin[0x4];
10982 	u8         remote_willing[0x1];
10983 	u8         reserved_at_61[3];
10984 	u8         remote_pfc_cap[4];
10985 	u8         reserved_at_68[0x14];
10986 	u8         remote_num_of_tc[0x4];
10987 	u8         reserved_at_80[0x18];
10988 	u8         error[0x8];
10989 	u8         reserved_at_a0[0x160];
10990 };
10991 
10992 enum {
10993 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
10994 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
10995 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
10996 };
10997 
10998 struct mlx5_ifc_lagc_bits {
10999 	u8         fdb_selection_mode[0x1];
11000 	u8         reserved_at_1[0x14];
11001 	u8         port_select_mode[0x3];
11002 	u8         reserved_at_18[0x5];
11003 	u8         lag_state[0x3];
11004 
11005 	u8         reserved_at_20[0xc];
11006 	u8         active_port[0x4];
11007 	u8         reserved_at_30[0x4];
11008 	u8         tx_remap_affinity_2[0x4];
11009 	u8         reserved_at_38[0x4];
11010 	u8         tx_remap_affinity_1[0x4];
11011 };
11012 
11013 struct mlx5_ifc_create_lag_out_bits {
11014 	u8         status[0x8];
11015 	u8         reserved_at_8[0x18];
11016 
11017 	u8         syndrome[0x20];
11018 
11019 	u8         reserved_at_40[0x40];
11020 };
11021 
11022 struct mlx5_ifc_create_lag_in_bits {
11023 	u8         opcode[0x10];
11024 	u8         reserved_at_10[0x10];
11025 
11026 	u8         reserved_at_20[0x10];
11027 	u8         op_mod[0x10];
11028 
11029 	struct mlx5_ifc_lagc_bits ctx;
11030 };
11031 
11032 struct mlx5_ifc_modify_lag_out_bits {
11033 	u8         status[0x8];
11034 	u8         reserved_at_8[0x18];
11035 
11036 	u8         syndrome[0x20];
11037 
11038 	u8         reserved_at_40[0x40];
11039 };
11040 
11041 struct mlx5_ifc_modify_lag_in_bits {
11042 	u8         opcode[0x10];
11043 	u8         reserved_at_10[0x10];
11044 
11045 	u8         reserved_at_20[0x10];
11046 	u8         op_mod[0x10];
11047 
11048 	u8         reserved_at_40[0x20];
11049 	u8         field_select[0x20];
11050 
11051 	struct mlx5_ifc_lagc_bits ctx;
11052 };
11053 
11054 struct mlx5_ifc_query_lag_out_bits {
11055 	u8         status[0x8];
11056 	u8         reserved_at_8[0x18];
11057 
11058 	u8         syndrome[0x20];
11059 
11060 	struct mlx5_ifc_lagc_bits ctx;
11061 };
11062 
11063 struct mlx5_ifc_query_lag_in_bits {
11064 	u8         opcode[0x10];
11065 	u8         reserved_at_10[0x10];
11066 
11067 	u8         reserved_at_20[0x10];
11068 	u8         op_mod[0x10];
11069 
11070 	u8         reserved_at_40[0x40];
11071 };
11072 
11073 struct mlx5_ifc_destroy_lag_out_bits {
11074 	u8         status[0x8];
11075 	u8         reserved_at_8[0x18];
11076 
11077 	u8         syndrome[0x20];
11078 
11079 	u8         reserved_at_40[0x40];
11080 };
11081 
11082 struct mlx5_ifc_destroy_lag_in_bits {
11083 	u8         opcode[0x10];
11084 	u8         reserved_at_10[0x10];
11085 
11086 	u8         reserved_at_20[0x10];
11087 	u8         op_mod[0x10];
11088 
11089 	u8         reserved_at_40[0x40];
11090 };
11091 
11092 struct mlx5_ifc_create_vport_lag_out_bits {
11093 	u8         status[0x8];
11094 	u8         reserved_at_8[0x18];
11095 
11096 	u8         syndrome[0x20];
11097 
11098 	u8         reserved_at_40[0x40];
11099 };
11100 
11101 struct mlx5_ifc_create_vport_lag_in_bits {
11102 	u8         opcode[0x10];
11103 	u8         reserved_at_10[0x10];
11104 
11105 	u8         reserved_at_20[0x10];
11106 	u8         op_mod[0x10];
11107 
11108 	u8         reserved_at_40[0x40];
11109 };
11110 
11111 struct mlx5_ifc_destroy_vport_lag_out_bits {
11112 	u8         status[0x8];
11113 	u8         reserved_at_8[0x18];
11114 
11115 	u8         syndrome[0x20];
11116 
11117 	u8         reserved_at_40[0x40];
11118 };
11119 
11120 struct mlx5_ifc_destroy_vport_lag_in_bits {
11121 	u8         opcode[0x10];
11122 	u8         reserved_at_10[0x10];
11123 
11124 	u8         reserved_at_20[0x10];
11125 	u8         op_mod[0x10];
11126 
11127 	u8         reserved_at_40[0x40];
11128 };
11129 
11130 enum {
11131 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11132 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11133 };
11134 
11135 struct mlx5_ifc_modify_memic_in_bits {
11136 	u8         opcode[0x10];
11137 	u8         uid[0x10];
11138 
11139 	u8         reserved_at_20[0x10];
11140 	u8         op_mod[0x10];
11141 
11142 	u8         reserved_at_40[0x20];
11143 
11144 	u8         reserved_at_60[0x18];
11145 	u8         memic_operation_type[0x8];
11146 
11147 	u8         memic_start_addr[0x40];
11148 
11149 	u8         reserved_at_c0[0x140];
11150 };
11151 
11152 struct mlx5_ifc_modify_memic_out_bits {
11153 	u8         status[0x8];
11154 	u8         reserved_at_8[0x18];
11155 
11156 	u8         syndrome[0x20];
11157 
11158 	u8         reserved_at_40[0x40];
11159 
11160 	u8         memic_operation_addr[0x40];
11161 
11162 	u8         reserved_at_c0[0x140];
11163 };
11164 
11165 struct mlx5_ifc_alloc_memic_in_bits {
11166 	u8         opcode[0x10];
11167 	u8         reserved_at_10[0x10];
11168 
11169 	u8         reserved_at_20[0x10];
11170 	u8         op_mod[0x10];
11171 
11172 	u8         reserved_at_30[0x20];
11173 
11174 	u8	   reserved_at_40[0x18];
11175 	u8	   log_memic_addr_alignment[0x8];
11176 
11177 	u8         range_start_addr[0x40];
11178 
11179 	u8         range_size[0x20];
11180 
11181 	u8         memic_size[0x20];
11182 };
11183 
11184 struct mlx5_ifc_alloc_memic_out_bits {
11185 	u8         status[0x8];
11186 	u8         reserved_at_8[0x18];
11187 
11188 	u8         syndrome[0x20];
11189 
11190 	u8         memic_start_addr[0x40];
11191 };
11192 
11193 struct mlx5_ifc_dealloc_memic_in_bits {
11194 	u8         opcode[0x10];
11195 	u8         reserved_at_10[0x10];
11196 
11197 	u8         reserved_at_20[0x10];
11198 	u8         op_mod[0x10];
11199 
11200 	u8         reserved_at_40[0x40];
11201 
11202 	u8         memic_start_addr[0x40];
11203 
11204 	u8         memic_size[0x20];
11205 
11206 	u8         reserved_at_e0[0x20];
11207 };
11208 
11209 struct mlx5_ifc_dealloc_memic_out_bits {
11210 	u8         status[0x8];
11211 	u8         reserved_at_8[0x18];
11212 
11213 	u8         syndrome[0x20];
11214 
11215 	u8         reserved_at_40[0x40];
11216 };
11217 
11218 struct mlx5_ifc_umem_bits {
11219 	u8         reserved_at_0[0x80];
11220 
11221 	u8         ats[0x1];
11222 	u8         reserved_at_81[0x1a];
11223 	u8         log_page_size[0x5];
11224 
11225 	u8         page_offset[0x20];
11226 
11227 	u8         num_of_mtt[0x40];
11228 
11229 	struct mlx5_ifc_mtt_bits  mtt[];
11230 };
11231 
11232 struct mlx5_ifc_uctx_bits {
11233 	u8         cap[0x20];
11234 
11235 	u8         reserved_at_20[0x160];
11236 };
11237 
11238 struct mlx5_ifc_sw_icm_bits {
11239 	u8         modify_field_select[0x40];
11240 
11241 	u8	   reserved_at_40[0x18];
11242 	u8         log_sw_icm_size[0x8];
11243 
11244 	u8         reserved_at_60[0x20];
11245 
11246 	u8         sw_icm_start_addr[0x40];
11247 
11248 	u8         reserved_at_c0[0x140];
11249 };
11250 
11251 struct mlx5_ifc_geneve_tlv_option_bits {
11252 	u8         modify_field_select[0x40];
11253 
11254 	u8         reserved_at_40[0x18];
11255 	u8         geneve_option_fte_index[0x8];
11256 
11257 	u8         option_class[0x10];
11258 	u8         option_type[0x8];
11259 	u8         reserved_at_78[0x3];
11260 	u8         option_data_length[0x5];
11261 
11262 	u8         reserved_at_80[0x180];
11263 };
11264 
11265 struct mlx5_ifc_create_umem_in_bits {
11266 	u8         opcode[0x10];
11267 	u8         uid[0x10];
11268 
11269 	u8         reserved_at_20[0x10];
11270 	u8         op_mod[0x10];
11271 
11272 	u8         reserved_at_40[0x40];
11273 
11274 	struct mlx5_ifc_umem_bits  umem;
11275 };
11276 
11277 struct mlx5_ifc_create_umem_out_bits {
11278 	u8         status[0x8];
11279 	u8         reserved_at_8[0x18];
11280 
11281 	u8         syndrome[0x20];
11282 
11283 	u8         reserved_at_40[0x8];
11284 	u8         umem_id[0x18];
11285 
11286 	u8         reserved_at_60[0x20];
11287 };
11288 
11289 struct mlx5_ifc_destroy_umem_in_bits {
11290 	u8        opcode[0x10];
11291 	u8        uid[0x10];
11292 
11293 	u8        reserved_at_20[0x10];
11294 	u8        op_mod[0x10];
11295 
11296 	u8        reserved_at_40[0x8];
11297 	u8        umem_id[0x18];
11298 
11299 	u8        reserved_at_60[0x20];
11300 };
11301 
11302 struct mlx5_ifc_destroy_umem_out_bits {
11303 	u8        status[0x8];
11304 	u8        reserved_at_8[0x18];
11305 
11306 	u8        syndrome[0x20];
11307 
11308 	u8        reserved_at_40[0x40];
11309 };
11310 
11311 struct mlx5_ifc_create_uctx_in_bits {
11312 	u8         opcode[0x10];
11313 	u8         reserved_at_10[0x10];
11314 
11315 	u8         reserved_at_20[0x10];
11316 	u8         op_mod[0x10];
11317 
11318 	u8         reserved_at_40[0x40];
11319 
11320 	struct mlx5_ifc_uctx_bits  uctx;
11321 };
11322 
11323 struct mlx5_ifc_create_uctx_out_bits {
11324 	u8         status[0x8];
11325 	u8         reserved_at_8[0x18];
11326 
11327 	u8         syndrome[0x20];
11328 
11329 	u8         reserved_at_40[0x10];
11330 	u8         uid[0x10];
11331 
11332 	u8         reserved_at_60[0x20];
11333 };
11334 
11335 struct mlx5_ifc_destroy_uctx_in_bits {
11336 	u8         opcode[0x10];
11337 	u8         reserved_at_10[0x10];
11338 
11339 	u8         reserved_at_20[0x10];
11340 	u8         op_mod[0x10];
11341 
11342 	u8         reserved_at_40[0x10];
11343 	u8         uid[0x10];
11344 
11345 	u8         reserved_at_60[0x20];
11346 };
11347 
11348 struct mlx5_ifc_destroy_uctx_out_bits {
11349 	u8         status[0x8];
11350 	u8         reserved_at_8[0x18];
11351 
11352 	u8         syndrome[0x20];
11353 
11354 	u8          reserved_at_40[0x40];
11355 };
11356 
11357 struct mlx5_ifc_create_sw_icm_in_bits {
11358 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11359 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
11360 };
11361 
11362 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11363 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11364 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11365 };
11366 
11367 struct mlx5_ifc_mtrc_string_db_param_bits {
11368 	u8         string_db_base_address[0x20];
11369 
11370 	u8         reserved_at_20[0x8];
11371 	u8         string_db_size[0x18];
11372 };
11373 
11374 struct mlx5_ifc_mtrc_cap_bits {
11375 	u8         trace_owner[0x1];
11376 	u8         trace_to_memory[0x1];
11377 	u8         reserved_at_2[0x4];
11378 	u8         trc_ver[0x2];
11379 	u8         reserved_at_8[0x14];
11380 	u8         num_string_db[0x4];
11381 
11382 	u8         first_string_trace[0x8];
11383 	u8         num_string_trace[0x8];
11384 	u8         reserved_at_30[0x28];
11385 
11386 	u8         log_max_trace_buffer_size[0x8];
11387 
11388 	u8         reserved_at_60[0x20];
11389 
11390 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11391 
11392 	u8         reserved_at_280[0x180];
11393 };
11394 
11395 struct mlx5_ifc_mtrc_conf_bits {
11396 	u8         reserved_at_0[0x1c];
11397 	u8         trace_mode[0x4];
11398 	u8         reserved_at_20[0x18];
11399 	u8         log_trace_buffer_size[0x8];
11400 	u8         trace_mkey[0x20];
11401 	u8         reserved_at_60[0x3a0];
11402 };
11403 
11404 struct mlx5_ifc_mtrc_stdb_bits {
11405 	u8         string_db_index[0x4];
11406 	u8         reserved_at_4[0x4];
11407 	u8         read_size[0x18];
11408 	u8         start_offset[0x20];
11409 	u8         string_db_data[];
11410 };
11411 
11412 struct mlx5_ifc_mtrc_ctrl_bits {
11413 	u8         trace_status[0x2];
11414 	u8         reserved_at_2[0x2];
11415 	u8         arm_event[0x1];
11416 	u8         reserved_at_5[0xb];
11417 	u8         modify_field_select[0x10];
11418 	u8         reserved_at_20[0x2b];
11419 	u8         current_timestamp52_32[0x15];
11420 	u8         current_timestamp31_0[0x20];
11421 	u8         reserved_at_80[0x180];
11422 };
11423 
11424 struct mlx5_ifc_host_params_context_bits {
11425 	u8         host_number[0x8];
11426 	u8         reserved_at_8[0x7];
11427 	u8         host_pf_disabled[0x1];
11428 	u8         host_num_of_vfs[0x10];
11429 
11430 	u8         host_total_vfs[0x10];
11431 	u8         host_pci_bus[0x10];
11432 
11433 	u8         reserved_at_40[0x10];
11434 	u8         host_pci_device[0x10];
11435 
11436 	u8         reserved_at_60[0x10];
11437 	u8         host_pci_function[0x10];
11438 
11439 	u8         reserved_at_80[0x180];
11440 };
11441 
11442 struct mlx5_ifc_query_esw_functions_in_bits {
11443 	u8         opcode[0x10];
11444 	u8         reserved_at_10[0x10];
11445 
11446 	u8         reserved_at_20[0x10];
11447 	u8         op_mod[0x10];
11448 
11449 	u8         reserved_at_40[0x40];
11450 };
11451 
11452 struct mlx5_ifc_query_esw_functions_out_bits {
11453 	u8         status[0x8];
11454 	u8         reserved_at_8[0x18];
11455 
11456 	u8         syndrome[0x20];
11457 
11458 	u8         reserved_at_40[0x40];
11459 
11460 	struct mlx5_ifc_host_params_context_bits host_params_context;
11461 
11462 	u8         reserved_at_280[0x180];
11463 	u8         host_sf_enable[][0x40];
11464 };
11465 
11466 struct mlx5_ifc_sf_partition_bits {
11467 	u8         reserved_at_0[0x10];
11468 	u8         log_num_sf[0x8];
11469 	u8         log_sf_bar_size[0x8];
11470 };
11471 
11472 struct mlx5_ifc_query_sf_partitions_out_bits {
11473 	u8         status[0x8];
11474 	u8         reserved_at_8[0x18];
11475 
11476 	u8         syndrome[0x20];
11477 
11478 	u8         reserved_at_40[0x18];
11479 	u8         num_sf_partitions[0x8];
11480 
11481 	u8         reserved_at_60[0x20];
11482 
11483 	struct mlx5_ifc_sf_partition_bits sf_partition[];
11484 };
11485 
11486 struct mlx5_ifc_query_sf_partitions_in_bits {
11487 	u8         opcode[0x10];
11488 	u8         reserved_at_10[0x10];
11489 
11490 	u8         reserved_at_20[0x10];
11491 	u8         op_mod[0x10];
11492 
11493 	u8         reserved_at_40[0x40];
11494 };
11495 
11496 struct mlx5_ifc_dealloc_sf_out_bits {
11497 	u8         status[0x8];
11498 	u8         reserved_at_8[0x18];
11499 
11500 	u8         syndrome[0x20];
11501 
11502 	u8         reserved_at_40[0x40];
11503 };
11504 
11505 struct mlx5_ifc_dealloc_sf_in_bits {
11506 	u8         opcode[0x10];
11507 	u8         reserved_at_10[0x10];
11508 
11509 	u8         reserved_at_20[0x10];
11510 	u8         op_mod[0x10];
11511 
11512 	u8         reserved_at_40[0x10];
11513 	u8         function_id[0x10];
11514 
11515 	u8         reserved_at_60[0x20];
11516 };
11517 
11518 struct mlx5_ifc_alloc_sf_out_bits {
11519 	u8         status[0x8];
11520 	u8         reserved_at_8[0x18];
11521 
11522 	u8         syndrome[0x20];
11523 
11524 	u8         reserved_at_40[0x40];
11525 };
11526 
11527 struct mlx5_ifc_alloc_sf_in_bits {
11528 	u8         opcode[0x10];
11529 	u8         reserved_at_10[0x10];
11530 
11531 	u8         reserved_at_20[0x10];
11532 	u8         op_mod[0x10];
11533 
11534 	u8         reserved_at_40[0x10];
11535 	u8         function_id[0x10];
11536 
11537 	u8         reserved_at_60[0x20];
11538 };
11539 
11540 struct mlx5_ifc_affiliated_event_header_bits {
11541 	u8         reserved_at_0[0x10];
11542 	u8         obj_type[0x10];
11543 
11544 	u8         obj_id[0x20];
11545 };
11546 
11547 enum {
11548 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11549 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11550 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11551 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11552 };
11553 
11554 enum {
11555 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11556 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11557 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11558 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11559 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11560 };
11561 
11562 enum {
11563 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11564 };
11565 
11566 struct mlx5_ifc_ipsec_obj_bits {
11567 	u8         modify_field_select[0x40];
11568 	u8         full_offload[0x1];
11569 	u8         reserved_at_41[0x1];
11570 	u8         esn_en[0x1];
11571 	u8         esn_overlap[0x1];
11572 	u8         reserved_at_44[0x2];
11573 	u8         icv_length[0x2];
11574 	u8         reserved_at_48[0x4];
11575 	u8         aso_return_reg[0x4];
11576 	u8         reserved_at_50[0x10];
11577 
11578 	u8         esn_msb[0x20];
11579 
11580 	u8         reserved_at_80[0x8];
11581 	u8         dekn[0x18];
11582 
11583 	u8         salt[0x20];
11584 
11585 	u8         implicit_iv[0x40];
11586 
11587 	u8         reserved_at_100[0x700];
11588 };
11589 
11590 struct mlx5_ifc_create_ipsec_obj_in_bits {
11591 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11592 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11593 };
11594 
11595 enum {
11596 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11597 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11598 };
11599 
11600 struct mlx5_ifc_query_ipsec_obj_out_bits {
11601 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11602 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11603 };
11604 
11605 struct mlx5_ifc_modify_ipsec_obj_in_bits {
11606 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11607 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11608 };
11609 
11610 enum {
11611 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
11612 };
11613 
11614 enum {
11615 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
11616 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
11617 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11618 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11619 };
11620 
11621 #define MLX5_MACSEC_ASO_INC_SN  0x2
11622 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
11623 
11624 struct mlx5_ifc_macsec_aso_bits {
11625 	u8    valid[0x1];
11626 	u8    reserved_at_1[0x1];
11627 	u8    mode[0x2];
11628 	u8    window_size[0x2];
11629 	u8    soft_lifetime_arm[0x1];
11630 	u8    hard_lifetime_arm[0x1];
11631 	u8    remove_flow_enable[0x1];
11632 	u8    epn_event_arm[0x1];
11633 	u8    reserved_at_a[0x16];
11634 
11635 	u8    remove_flow_packet_count[0x20];
11636 
11637 	u8    remove_flow_soft_lifetime[0x20];
11638 
11639 	u8    reserved_at_60[0x80];
11640 
11641 	u8    mode_parameter[0x20];
11642 
11643 	u8    replay_protection_window[8][0x20];
11644 };
11645 
11646 struct mlx5_ifc_macsec_offload_obj_bits {
11647 	u8    modify_field_select[0x40];
11648 
11649 	u8    confidentiality_en[0x1];
11650 	u8    reserved_at_41[0x1];
11651 	u8    epn_en[0x1];
11652 	u8    epn_overlap[0x1];
11653 	u8    reserved_at_44[0x2];
11654 	u8    confidentiality_offset[0x2];
11655 	u8    reserved_at_48[0x4];
11656 	u8    aso_return_reg[0x4];
11657 	u8    reserved_at_50[0x10];
11658 
11659 	u8    epn_msb[0x20];
11660 
11661 	u8    reserved_at_80[0x8];
11662 	u8    dekn[0x18];
11663 
11664 	u8    reserved_at_a0[0x20];
11665 
11666 	u8    sci[0x40];
11667 
11668 	u8    reserved_at_100[0x8];
11669 	u8    macsec_aso_access_pd[0x18];
11670 
11671 	u8    reserved_at_120[0x60];
11672 
11673 	u8    salt[3][0x20];
11674 
11675 	u8    reserved_at_1e0[0x20];
11676 
11677 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
11678 };
11679 
11680 struct mlx5_ifc_create_macsec_obj_in_bits {
11681 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11682 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11683 };
11684 
11685 struct mlx5_ifc_modify_macsec_obj_in_bits {
11686 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11687 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11688 };
11689 
11690 enum {
11691 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
11692 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
11693 };
11694 
11695 struct mlx5_ifc_query_macsec_obj_out_bits {
11696 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11697 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
11698 };
11699 
11700 struct mlx5_ifc_encryption_key_obj_bits {
11701 	u8         modify_field_select[0x40];
11702 
11703 	u8         reserved_at_40[0x14];
11704 	u8         key_size[0x4];
11705 	u8         reserved_at_58[0x4];
11706 	u8         key_type[0x4];
11707 
11708 	u8         reserved_at_60[0x8];
11709 	u8         pd[0x18];
11710 
11711 	u8         reserved_at_80[0x180];
11712 	u8         key[8][0x20];
11713 
11714 	u8         reserved_at_300[0x500];
11715 };
11716 
11717 struct mlx5_ifc_create_encryption_key_in_bits {
11718 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11719 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
11720 };
11721 
11722 enum {
11723 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
11724 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
11725 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
11726 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
11727 };
11728 
11729 struct mlx5_ifc_flow_meter_parameters_bits {
11730 	u8         valid[0x1];
11731 	u8         bucket_overflow[0x1];
11732 	u8         start_color[0x2];
11733 	u8         both_buckets_on_green[0x1];
11734 	u8         reserved_at_5[0x1];
11735 	u8         meter_mode[0x2];
11736 	u8         reserved_at_8[0x18];
11737 
11738 	u8         reserved_at_20[0x20];
11739 
11740 	u8         reserved_at_40[0x3];
11741 	u8         cbs_exponent[0x5];
11742 	u8         cbs_mantissa[0x8];
11743 	u8         reserved_at_50[0x3];
11744 	u8         cir_exponent[0x5];
11745 	u8         cir_mantissa[0x8];
11746 
11747 	u8         reserved_at_60[0x20];
11748 
11749 	u8         reserved_at_80[0x3];
11750 	u8         ebs_exponent[0x5];
11751 	u8         ebs_mantissa[0x8];
11752 	u8         reserved_at_90[0x3];
11753 	u8         eir_exponent[0x5];
11754 	u8         eir_mantissa[0x8];
11755 
11756 	u8         reserved_at_a0[0x60];
11757 };
11758 
11759 struct mlx5_ifc_flow_meter_aso_obj_bits {
11760 	u8         modify_field_select[0x40];
11761 
11762 	u8         reserved_at_40[0x40];
11763 
11764 	u8         reserved_at_80[0x8];
11765 	u8         meter_aso_access_pd[0x18];
11766 
11767 	u8         reserved_at_a0[0x160];
11768 
11769 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
11770 };
11771 
11772 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
11773 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
11774 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
11775 };
11776 
11777 struct mlx5_ifc_sampler_obj_bits {
11778 	u8         modify_field_select[0x40];
11779 
11780 	u8         table_type[0x8];
11781 	u8         level[0x8];
11782 	u8         reserved_at_50[0xf];
11783 	u8         ignore_flow_level[0x1];
11784 
11785 	u8         sample_ratio[0x20];
11786 
11787 	u8         reserved_at_80[0x8];
11788 	u8         sample_table_id[0x18];
11789 
11790 	u8         reserved_at_a0[0x8];
11791 	u8         default_table_id[0x18];
11792 
11793 	u8         sw_steering_icm_address_rx[0x40];
11794 	u8         sw_steering_icm_address_tx[0x40];
11795 
11796 	u8         reserved_at_140[0xa0];
11797 };
11798 
11799 struct mlx5_ifc_create_sampler_obj_in_bits {
11800 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11801 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11802 };
11803 
11804 struct mlx5_ifc_query_sampler_obj_out_bits {
11805 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
11806 	struct mlx5_ifc_sampler_obj_bits sampler_object;
11807 };
11808 
11809 enum {
11810 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
11811 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
11812 };
11813 
11814 enum {
11815 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
11816 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
11817 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4,
11818 };
11819 
11820 struct mlx5_ifc_tls_static_params_bits {
11821 	u8         const_2[0x2];
11822 	u8         tls_version[0x4];
11823 	u8         const_1[0x2];
11824 	u8         reserved_at_8[0x14];
11825 	u8         encryption_standard[0x4];
11826 
11827 	u8         reserved_at_20[0x20];
11828 
11829 	u8         initial_record_number[0x40];
11830 
11831 	u8         resync_tcp_sn[0x20];
11832 
11833 	u8         gcm_iv[0x20];
11834 
11835 	u8         implicit_iv[0x40];
11836 
11837 	u8         reserved_at_100[0x8];
11838 	u8         dek_index[0x18];
11839 
11840 	u8         reserved_at_120[0xe0];
11841 };
11842 
11843 struct mlx5_ifc_tls_progress_params_bits {
11844 	u8         next_record_tcp_sn[0x20];
11845 
11846 	u8         hw_resync_tcp_sn[0x20];
11847 
11848 	u8         record_tracker_state[0x2];
11849 	u8         auth_state[0x2];
11850 	u8         reserved_at_44[0x4];
11851 	u8         hw_offset_record_number[0x18];
11852 };
11853 
11854 enum {
11855 	MLX5_MTT_PERM_READ	= 1 << 0,
11856 	MLX5_MTT_PERM_WRITE	= 1 << 1,
11857 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
11858 };
11859 
11860 enum {
11861 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
11862 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
11863 };
11864 
11865 struct mlx5_ifc_suspend_vhca_in_bits {
11866 	u8         opcode[0x10];
11867 	u8         uid[0x10];
11868 
11869 	u8         reserved_at_20[0x10];
11870 	u8         op_mod[0x10];
11871 
11872 	u8         reserved_at_40[0x10];
11873 	u8         vhca_id[0x10];
11874 
11875 	u8         reserved_at_60[0x20];
11876 };
11877 
11878 struct mlx5_ifc_suspend_vhca_out_bits {
11879 	u8         status[0x8];
11880 	u8         reserved_at_8[0x18];
11881 
11882 	u8         syndrome[0x20];
11883 
11884 	u8         reserved_at_40[0x40];
11885 };
11886 
11887 enum {
11888 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
11889 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
11890 };
11891 
11892 struct mlx5_ifc_resume_vhca_in_bits {
11893 	u8         opcode[0x10];
11894 	u8         uid[0x10];
11895 
11896 	u8         reserved_at_20[0x10];
11897 	u8         op_mod[0x10];
11898 
11899 	u8         reserved_at_40[0x10];
11900 	u8         vhca_id[0x10];
11901 
11902 	u8         reserved_at_60[0x20];
11903 };
11904 
11905 struct mlx5_ifc_resume_vhca_out_bits {
11906 	u8         status[0x8];
11907 	u8         reserved_at_8[0x18];
11908 
11909 	u8         syndrome[0x20];
11910 
11911 	u8         reserved_at_40[0x40];
11912 };
11913 
11914 struct mlx5_ifc_query_vhca_migration_state_in_bits {
11915 	u8         opcode[0x10];
11916 	u8         uid[0x10];
11917 
11918 	u8         reserved_at_20[0x10];
11919 	u8         op_mod[0x10];
11920 
11921 	u8         reserved_at_40[0x10];
11922 	u8         vhca_id[0x10];
11923 
11924 	u8         reserved_at_60[0x20];
11925 };
11926 
11927 struct mlx5_ifc_query_vhca_migration_state_out_bits {
11928 	u8         status[0x8];
11929 	u8         reserved_at_8[0x18];
11930 
11931 	u8         syndrome[0x20];
11932 
11933 	u8         reserved_at_40[0x40];
11934 
11935 	u8         required_umem_size[0x20];
11936 
11937 	u8         reserved_at_a0[0x160];
11938 };
11939 
11940 struct mlx5_ifc_save_vhca_state_in_bits {
11941 	u8         opcode[0x10];
11942 	u8         uid[0x10];
11943 
11944 	u8         reserved_at_20[0x10];
11945 	u8         op_mod[0x10];
11946 
11947 	u8         reserved_at_40[0x10];
11948 	u8         vhca_id[0x10];
11949 
11950 	u8         reserved_at_60[0x20];
11951 
11952 	u8         va[0x40];
11953 
11954 	u8         mkey[0x20];
11955 
11956 	u8         size[0x20];
11957 };
11958 
11959 struct mlx5_ifc_save_vhca_state_out_bits {
11960 	u8         status[0x8];
11961 	u8         reserved_at_8[0x18];
11962 
11963 	u8         syndrome[0x20];
11964 
11965 	u8         actual_image_size[0x20];
11966 
11967 	u8         reserved_at_60[0x20];
11968 };
11969 
11970 struct mlx5_ifc_load_vhca_state_in_bits {
11971 	u8         opcode[0x10];
11972 	u8         uid[0x10];
11973 
11974 	u8         reserved_at_20[0x10];
11975 	u8         op_mod[0x10];
11976 
11977 	u8         reserved_at_40[0x10];
11978 	u8         vhca_id[0x10];
11979 
11980 	u8         reserved_at_60[0x20];
11981 
11982 	u8         va[0x40];
11983 
11984 	u8         mkey[0x20];
11985 
11986 	u8         size[0x20];
11987 };
11988 
11989 struct mlx5_ifc_load_vhca_state_out_bits {
11990 	u8         status[0x8];
11991 	u8         reserved_at_8[0x18];
11992 
11993 	u8         syndrome[0x20];
11994 
11995 	u8         reserved_at_40[0x40];
11996 };
11997 
11998 struct mlx5_ifc_adv_virtualization_cap_bits {
11999 	u8         reserved_at_0[0x3];
12000 	u8         pg_track_log_max_num[0x5];
12001 	u8         pg_track_max_num_range[0x8];
12002 	u8         pg_track_log_min_addr_space[0x8];
12003 	u8         pg_track_log_max_addr_space[0x8];
12004 
12005 	u8         reserved_at_20[0x3];
12006 	u8         pg_track_log_min_msg_size[0x5];
12007 	u8         reserved_at_28[0x3];
12008 	u8         pg_track_log_max_msg_size[0x5];
12009 	u8         reserved_at_30[0x3];
12010 	u8         pg_track_log_min_page_size[0x5];
12011 	u8         reserved_at_38[0x3];
12012 	u8         pg_track_log_max_page_size[0x5];
12013 
12014 	u8         reserved_at_40[0x7c0];
12015 };
12016 
12017 struct mlx5_ifc_page_track_report_entry_bits {
12018 	u8         dirty_address_high[0x20];
12019 
12020 	u8         dirty_address_low[0x20];
12021 };
12022 
12023 enum {
12024 	MLX5_PAGE_TRACK_STATE_TRACKING,
12025 	MLX5_PAGE_TRACK_STATE_REPORTING,
12026 	MLX5_PAGE_TRACK_STATE_ERROR,
12027 };
12028 
12029 struct mlx5_ifc_page_track_range_bits {
12030 	u8         start_address[0x40];
12031 
12032 	u8         length[0x40];
12033 };
12034 
12035 struct mlx5_ifc_page_track_bits {
12036 	u8         modify_field_select[0x40];
12037 
12038 	u8         reserved_at_40[0x10];
12039 	u8         vhca_id[0x10];
12040 
12041 	u8         reserved_at_60[0x20];
12042 
12043 	u8         state[0x4];
12044 	u8         track_type[0x4];
12045 	u8         log_addr_space_size[0x8];
12046 	u8         reserved_at_90[0x3];
12047 	u8         log_page_size[0x5];
12048 	u8         reserved_at_98[0x3];
12049 	u8         log_msg_size[0x5];
12050 
12051 	u8         reserved_at_a0[0x8];
12052 	u8         reporting_qpn[0x18];
12053 
12054 	u8         reserved_at_c0[0x18];
12055 	u8         num_ranges[0x8];
12056 
12057 	u8         reserved_at_e0[0x20];
12058 
12059 	u8         range_start_address[0x40];
12060 
12061 	u8         length[0x40];
12062 
12063 	struct     mlx5_ifc_page_track_range_bits track_range[0];
12064 };
12065 
12066 struct mlx5_ifc_create_page_track_obj_in_bits {
12067 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12068 	struct mlx5_ifc_page_track_bits obj_context;
12069 };
12070 
12071 struct mlx5_ifc_modify_page_track_obj_in_bits {
12072 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12073 	struct mlx5_ifc_page_track_bits obj_context;
12074 };
12075 
12076 #endif /* MLX5_IFC_H */
12077