Searched refs:link_level (Results 1 – 3 of 3) sorted by relevance
546 uint32_t link_level; in smu_v13_0_7_set_default_dpm_table() local648 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_7_set_default_dpm_table()649 if (!skutable->PcieGenSpeed[link_level] && in smu_v13_0_7_set_default_dpm_table()650 !skutable->PcieLaneCount[link_level] && in smu_v13_0_7_set_default_dpm_table()651 !skutable->LclkFreq[link_level]) in smu_v13_0_7_set_default_dpm_table()655 skutable->PcieGenSpeed[link_level]; in smu_v13_0_7_set_default_dpm_table()657 skutable->PcieLaneCount[link_level]; in smu_v13_0_7_set_default_dpm_table()659 skutable->LclkFreq[link_level]; in smu_v13_0_7_set_default_dpm_table()
493 uint32_t link_level; in smu_v13_0_0_set_default_dpm_table() local595 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_0_set_default_dpm_table()596 if (!skutable->PcieGenSpeed[link_level] && in smu_v13_0_0_set_default_dpm_table()597 !skutable->PcieLaneCount[link_level] && in smu_v13_0_0_set_default_dpm_table()598 !skutable->LclkFreq[link_level]) in smu_v13_0_0_set_default_dpm_table()602 skutable->PcieGenSpeed[link_level]; in smu_v13_0_0_set_default_dpm_table()604 skutable->PcieLaneCount[link_level]; in smu_v13_0_0_set_default_dpm_table()606 skutable->LclkFreq[link_level]; in smu_v13_0_0_set_default_dpm_table()
1739 int link_level; in nix_reset_tx_linkcfg() local1749 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? in nix_reset_tx_linkcfg()1751 if (lvl != link_level) in nix_reset_tx_linkcfg()
