| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_amdkfd_gfx_v11.c | 263 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v11() local
279 r = amdgpu_ring_alloc(kiq_ring, 7); in hiq_mqd_load_v11()
285 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v11()
286 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
296 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v11()
298 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v11()
299 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v11()
300 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v11()
301 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v11()
302 amdgpu_ring_commit(kiq_ring); in hiq_mqd_load_v11()
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| D | amdgpu_amdkfd_gfx_v10.c | 291 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load() local
307 r = amdgpu_ring_alloc(kiq_ring, 7); in kgd_hiq_mqd_load()
313 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
314 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
324 amdgpu_ring_write(kiq_ring, in kgd_hiq_mqd_load()
326 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_hiq_mqd_load()
327 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_hiq_mqd_load()
328 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_hiq_mqd_load()
329 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()
330 amdgpu_ring_commit(kiq_ring); in kgd_hiq_mqd_load()
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| D | amdgpu_amdkfd_gfx_v9.c | 303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load() local
319 r = amdgpu_ring_alloc(kiq_ring, 7); in kgd_gfx_v9_hiq_mqd_load()
325 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
326 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
336 amdgpu_ring_write(kiq_ring, in kgd_gfx_v9_hiq_mqd_load()
338 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
339 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
340 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in kgd_gfx_v9_hiq_mqd_load()
341 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
342 amdgpu_ring_commit(kiq_ring); in kgd_gfx_v9_hiq_mqd_load()
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| D | amdgpu_amdkfd_gfx_v10_3.c | 278 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3() local
294 r = amdgpu_ring_alloc(kiq_ring, 7); in hiq_mqd_load_v10_3()
300 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
301 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
311 amdgpu_ring_write(kiq_ring, in hiq_mqd_load_v10_3()
313 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); in hiq_mqd_load_v10_3()
314 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); in hiq_mqd_load_v10_3()
315 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); in hiq_mqd_load_v10_3()
316 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v10_3()
317 amdgpu_ring_commit(kiq_ring); in hiq_mqd_load_v10_3()
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| D | amdgpu_gfx.c | 464 struct amdgpu_ring *kiq_ring = &kiq->ring; in amdgpu_gfx_disable_kcq() local
471 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * in amdgpu_gfx_disable_kcq()
478 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], in amdgpu_gfx_disable_kcq()
482 r = amdgpu_ring_test_helper(kiq_ring); in amdgpu_gfx_disable_kcq()
504 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in amdgpu_gfx_enable_kcq() local
526 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, in amdgpu_gfx_enable_kcq()
527 kiq_ring->queue); in amdgpu_gfx_enable_kcq()
529 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * in amdgpu_gfx_enable_kcq()
541 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); in amdgpu_gfx_enable_kcq()
543 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); in amdgpu_gfx_enable_kcq()
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| D | amdgpu_gfx.h | 81 void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
83 void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
85 void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
89 void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
93 void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
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| D | gfx_v11_0.c | 126 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx11_kiq_set_resources() argument
128 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx11_kiq_set_resources()
129 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx11_kiq_set_resources()
131 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx11_kiq_set_resources()
132 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx11_kiq_set_resources()
133 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx11_kiq_set_resources()
134 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx11_kiq_set_resources()
135 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx11_kiq_set_resources()
136 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx11_kiq_set_resources()
139 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, in gfx11_kiq_map_queues() argument
[all …]
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| D | gfx_v9_0.c | 764 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, in gfx_v9_0_kiq_set_resources() argument
767 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v9_0_kiq_set_resources()
768 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
772 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
774 amdgpu_ring_write(kiq_ring, in gfx_v9_0_kiq_set_resources()
776 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v9_0_kiq_set_resources()
777 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v9_0_kiq_set_resources()
778 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v9_0_kiq_set_resources()
779 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v9_0_kiq_set_resources()
782 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, in gfx_v9_0_kiq_map_queues() argument
[all …]
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| D | gfx_v10_0.c | 3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) in gfx10_kiq_set_resources() argument
3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx10_kiq_set_resources()
3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | in gfx10_kiq_set_resources()
3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx10_kiq_set_resources()
3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx10_kiq_set_resources()
3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx10_kiq_set_resources()
3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx10_kiq_set_resources()
3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx10_kiq_set_resources()
3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx10_kiq_set_resources()
3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, in gfx10_kiq_map_queues() argument
[all …]
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| D | mes_v10_1.c | 884 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in mes_v10_1_kiq_enable_queue() local
890 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v10_1_kiq_enable_queue()
896 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v10_1_kiq_enable_queue()
898 r = amdgpu_ring_test_ring(kiq_ring); in mes_v10_1_kiq_enable_queue()
901 kiq_ring->sched.ready = false; in mes_v10_1_kiq_enable_queue()
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| D | gfx_v8_0.c | 4344 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in gfx_v8_0_kiq_kcq_enable() local
4363 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()
4369 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); in gfx_v8_0_kiq_kcq_enable()
4370 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ in gfx_v8_0_kiq_kcq_enable()
4371 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ in gfx_v8_0_kiq_kcq_enable()
4372 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ in gfx_v8_0_kiq_kcq_enable()
4373 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ in gfx_v8_0_kiq_kcq_enable()
4374 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ in gfx_v8_0_kiq_kcq_enable()
4375 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ in gfx_v8_0_kiq_kcq_enable()
4376 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ in gfx_v8_0_kiq_kcq_enable()
[all …]
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| D | mes_v11_0.c | 931 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in mes_v11_0_kiq_enable_queue() local
937 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); in mes_v11_0_kiq_enable_queue()
943 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); in mes_v11_0_kiq_enable_queue()
945 r = amdgpu_ring_test_ring(kiq_ring); in mes_v11_0_kiq_enable_queue()
948 kiq_ring->sched.ready = false; in mes_v11_0_kiq_enable_queue()
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