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Searched refs:ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR (Results 1 – 15 of 15) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h6025 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_0_3_offset.h7648 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_0_1_offset.h12491 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_1_0_offset.h13335 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_2_1_0_offset.h13095 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_2_0_offset.h13802 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_1_5_offset.h14411 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_2_1_offset.h13781 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_1_4_offset.h406 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_1_2_offset.h14305 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_1_6_offset.h14902 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_0_2_offset.h15380 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_2_0_0_offset.h16759 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
Ddcn_3_0_0_offset.h17101 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h17148 #define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR … macro