Searched refs:irq_handler_offset (Results 1 – 2 of 2) sorted by relevance
2611 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_pci_dma_qman() local2660 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_pci_dma_qman()2673 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2675 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_pci_dma_qman()2700 u32 irq_handler_offset; in gaudi_init_dma_core() local2715 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_dma_core()2720 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2722 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi_init_dma_core()2790 u32 dma_qm_err_cfg, irq_handler_offset; in gaudi_init_hbm_dma_qman() local2831 irq_handler_offset = hdev->asic_prop.gic_interrupts_enable ? in gaudi_init_hbm_dma_qman()[all …]
4201 u32 glbl_prot = QMAN_MAKE_TRUSTED, irq_handler_offset; in gaudi2_init_qman_common() local4206 irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base); in gaudi2_init_qman_common()4207 WREG32(reg_base + QM_GLBL_ERR_ADDR_LO_OFFSET, lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()4208 WREG32(reg_base + QM_GLBL_ERR_ADDR_HI_OFFSET, upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_qman_common()4251 u32 prot, irq_handler_offset; in gaudi2_init_dma_core() local4262 irq_handler_offset = le32_to_cpu(dyn_regs->gic_dma_core_irq_ctrl); in gaudi2_init_dma_core()4265 lower_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()4268 upper_32_bits(CFG_BASE + irq_handler_offset)); in gaudi2_init_dma_core()9913 u32 irq_handler_offset = le32_to_cpu(dyn_regs->gic_host_ints_irq); in gaudi2_enable_events_from_fw() local9916 WREG32(irq_handler_offset, in gaudi2_enable_events_from_fw()
