Searched refs:interrupt_status_offsets (Results 1 – 4 of 4) sorted by relevance
93 } interrupt_status_offsets[6] = { { variable2964 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v6_0_crtc_irq()2970 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v6_0_crtc_irq()2981 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()3085 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v6_0_hpd_irq()3086 mask = interrupt_status_offsets[hpd].hpd; in dce_v6_0_hpd_irq()
90 } interrupt_status_offsets[6] = { { variable3057 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v8_0_crtc_irq()3063 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v8_0_crtc_irq()3074 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()3178 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v8_0_hpd_irq()3179 mask = interrupt_status_offsets[hpd].hpd; in dce_v8_0_hpd_irq()
90 } interrupt_status_offsets[] = { { variable3242 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v10_0_crtc_irq()3247 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v10_0_crtc_irq()3259 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()3288 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()3289 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
92 } interrupt_status_offsets[] = { { variable3365 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); in dce_v11_0_crtc_irq()3371 if (disp_int & interrupt_status_offsets[crtc].vblank) in dce_v11_0_crtc_irq()3383 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()3412 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v11_0_hpd_irq()3413 mask = interrupt_status_offsets[hpd].hpd; in dce_v11_0_hpd_irq()
