Searched refs:input_clks (Results 1 – 2 of 2) sorted by relevance
369 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; member524 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_init()525 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_init()741 clk = sp->input_clks[pll_mux_parent_index[clk_index][i]]; in cdns_sierra_pll_mux_register()1140 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1148 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1156 sp->input_clks[PLL0_REFCLK] = clk; in cdns_sierra_phy_get_clocks()1164 sp->input_clks[PLL1_REFCLK] = clk; in cdns_sierra_phy_get_clocks()1180 sp->input_clks[PHY_CLK] = clk; in cdns_sierra_phy_clk()1182 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_clk()[all …]
371 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; member804 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()1066 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_init()1100 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; in wiz_clock_init()1115 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_init()
