| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_de.h | 14 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_read()
20 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_posting_read()
26 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) in intel_de_write()
32 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) in intel_de_rmw()
38 intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_register()
45 intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_set()
52 intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, in intel_de_wait_for_clear()
67 intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg) in intel_de_read_fw()
78 intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) in intel_de_write_fw()
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| D | intel_dkl_phy.h | 16 intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
18 intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val);
20 intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set);
22 intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln);
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| D | intel_dkl_phy.c | 14 dkl_phy_set_hip_idx(struct drm_i915_private *i915, i915_reg_t reg, int idx) in dkl_phy_set_hip_idx()
36 intel_dkl_phy_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) in intel_dkl_phy_read()
60 intel_dkl_phy_write(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 val) in intel_dkl_phy_write()
82 intel_dkl_phy_rmw(struct drm_i915_private *i915, i915_reg_t reg, int ln, u32 clear, u32 set) in intel_dkl_phy_rmw()
101 intel_dkl_phy_posting_read(struct drm_i915_private *i915, i915_reg_t reg, int ln) in intel_dkl_phy_posting_read()
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| D | intel_dp_aux.c | 39 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); in intel_dp_aux_wait_done()
196 i915_reg_t ch_ctl, ch_data[5]; in intel_dp_aux_xfer()
482 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) in g4x_aux_ctl_reg()
499 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) in g4x_aux_data_reg()
516 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) in ilk_aux_ctl_reg()
535 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) in ilk_aux_data_reg()
554 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) in skl_aux_ctl_reg()
574 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) in skl_aux_data_reg()
594 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) in tgl_aux_ctl_reg()
617 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) in tgl_aux_data_reg()
[all …]
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| D | intel_sdvo.h | 18 i915_reg_t sdvo_reg, enum pipe *pipe);
20 i915_reg_t reg, enum port port);
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| D | intel_dsb.h | 18 i915_reg_t reg, u32 val);
20 i915_reg_t reg, u32 val);
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| D | g4x_dp.h | 25 i915_reg_t dp_reg, enum port port,
28 i915_reg_t output_reg, enum port port);
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| D | intel_vga.c | 16 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915) in intel_vga_cntrl_reg()
30 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); in intel_vga_disable()
50 i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); in intel_vga_redisable_power_on()
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| D | intel_dvo_dev.h | 36 i915_reg_t dvo_reg;
37 i915_reg_t dvo_srcdim_reg;
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| D | intel_pch_display.c | 36 i915_reg_t dp_reg) in assert_pch_dp_disabled()
54 i915_reg_t hdmi_reg) in assert_pch_hdmi_disabled()
109 enum port port, i915_reg_t hdmi_reg) in ibx_sanitize_pch_hdmi_port()
128 enum port port, i915_reg_t dp_reg) in ibx_sanitize_pch_dp_port()
242 i915_reg_t reg; in ilk_enable_pch_transcoder()
308 i915_reg_t reg; in ilk_disable_pch_transcoder()
417 i915_reg_t reg = TRANS_DP_CTL(pipe); in ilk_pch_enable()
458 i915_reg_t reg; in ilk_pch_post_disable()
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| D | intel_display.h | 625 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
626 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
629 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
630 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
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| D | intel_pps.c | 354 i915_reg_t pp_ctrl;
355 i915_reg_t pp_stat;
356 i915_reg_t pp_on;
357 i915_reg_t pp_off;
358 i915_reg_t pp_div;
387 static i915_reg_t
397 static i915_reg_t
465 i915_reg_t pp_stat_reg, pp_ctrl_reg; in wait_panel_status()
581 i915_reg_t pp_stat_reg, pp_ctrl_reg; in intel_pps_vdd_on_unlocked()
659 i915_reg_t pp_stat_reg, pp_ctrl_reg; in intel_pps_vdd_off_sync_unlocked()
[all …]
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| D | intel_ddi.h | 25 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
27 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
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| D | intel_dmc.c | 281 i915_reg_t ctl_reg, i915_reg_t htp_reg) in disable_event_handler()
293 i915_reg_t ctl_reg, i915_reg_t htp_reg) in disable_flip_queue_event()
318 i915_reg_t *ctl_reg, i915_reg_t *htp_reg) in get_flip_queue_event_regs()
352 i915_reg_t ctl_reg; in disable_all_flip_queue_events()
353 i915_reg_t htp_reg; in disable_all_flip_queue_events()
1056 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; in intel_dmc_debugfs_status_show()
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| /Linux-v6.1/drivers/gpu/drm/i915/ |
| D | intel_uncore.h | 96 i915_reg_t r);
98 i915_reg_t r);
101 i915_reg_t r, bool trace);
103 i915_reg_t r, bool trace);
105 i915_reg_t r, bool trace);
107 i915_reg_t r, bool trace);
110 i915_reg_t r, u8 val, bool trace);
112 i915_reg_t r, u16 val, bool trace);
114 i915_reg_t r, u32 val, bool trace);
246 i915_reg_t reg, unsigned int op);
[all …]
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| D | i915_reg_defs.h | 103 } i915_reg_t; typedef
105 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
109 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg) in i915_mmio_reg_offset()
114 static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b) in i915_mmio_reg_equal()
119 static inline bool i915_mmio_reg_valid(i915_reg_t reg) in i915_mmio_reg_valid()
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| D | i915_irq.h | 94 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
95 i915_reg_t iir, i915_reg_t ier);
100 i915_reg_t imr, u32 imr_val,
101 i915_reg_t ier, u32 ier_val,
102 i915_reg_t iir);
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| D | intel_uncore.c | 1159 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) in gen6_reg_write_fw_domains()
1693 const i915_reg_t reg, in __unclaimed_reg_debug()
1707 const i915_reg_t reg, in __unclaimed_previous_reg_debug()
1719 const i915_reg_t reg, in unclaimed_reg_debug()
1740 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1760 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1768 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \
1833 fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \
1845 fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { in fwtable_reg_read_fw_domains()
1866 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \
[all …]
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| D | i915_ioctl.c | 23 i915_reg_t offset_ldw;
24 i915_reg_t offset_udw;
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| /Linux-v6.1/drivers/gpu/drm/i915/gt/ |
| D | intel_gt_mcr.h | 14 i915_reg_t reg,
16 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
17 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
20 i915_reg_t reg, u32 value,
23 i915_reg_t reg, u32 value);
25 i915_reg_t reg, u32 value);
28 i915_reg_t reg,
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| D | intel_gt_mcr.c | 151 i915_reg_t reg, u8 rw_flag, in rw_with_mcr_steering_fw()
201 i915_reg_t reg, u8 rw_flag, in rw_with_mcr_steering()
236 i915_reg_t reg, in intel_gt_mcr_read()
253 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value, in intel_gt_mcr_unicast_write()
268 i915_reg_t reg, u32 value) in intel_gt_mcr_multicast_write()
284 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value) in intel_gt_mcr_multicast_write_fw()
304 i915_reg_t reg, in reg_needs_read_steering()
383 i915_reg_t reg, in intel_gt_mcr_get_nonterminated_steering()
412 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg) in intel_gt_mcr_read_any_fw()
439 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg) in intel_gt_mcr_read_any()
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| D | intel_gt_pm_irq.c | 18 i915_reg_t reg; in write_pm_imr()
65 i915_reg_t reg = GRAPHICS_VER(gt->i915) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_gt_pm_reset_iir()
79 i915_reg_t reg; in write_pm_ier()
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| D | intel_rc6.h | 24 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, i915_reg_t reg);
25 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg);
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| D | intel_gt.c | 213 static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set) in rmw_set()
218 static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr) in rmw_clear()
223 static void clear_register(struct intel_uncore *uncore, i915_reg_t reg) in clear_register()
304 i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg; in gen8_check_faults()
947 i915_reg_t reg;
953 const i915_reg_t *regs, const unsigned int num) in get_reg_and_bit()
975 static const i915_reg_t gen8_regs[] = { in mmio_invalidate_full()
981 static const i915_reg_t gen12_regs[] = { in mmio_invalidate_full()
993 const i915_reg_t *regs; in mmio_invalidate_full()
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| /Linux-v6.1/drivers/gpu/drm/i915/selftests/ |
| D | mock_uncore.c | 29 nop_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { }
36 nop_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { return 0; }
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