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Searched refs:i915_ggtt_offset (Results 1 – 25 of 32) sorted by relevance

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/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_lrc.c810 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in init_wa_bb_regs()
819 i915_ggtt_offset(wa_ctx->vma) + in init_wa_bb_regs()
976 return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce); in lrc_indirect_bb()
1185 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_timestamp_wa()
1213 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_restore_scratch()
1229 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET + in gen12_emit_cmd_buf_wa()
1406 return i915_ggtt_offset(ce->state) | desc; in lrc_descriptor()
1419 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma); in lrc_update_regs()
1462 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) { in lrc_check_regs()
1466 i915_ggtt_offset(ring->vma)); in lrc_check_regs()
[all …]
Dselftest_lrc.c81 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
445 *cs++ = i915_ggtt_offset(scratch) + RING_START_IDX * sizeof(u32); in __live_lrc_state()
448 expected[RING_START_IDX] = i915_ggtt_offset(ce->ring->vma); in __live_lrc_state()
452 *cs++ = i915_ggtt_offset(scratch) + RING_TAIL_IDX * sizeof(u32); in __live_lrc_state()
569 i915_ggtt_offset(ce->engine->status_page.vma) + in __gpr_read()
600 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in __gpr_read()
746 i915_ggtt_offset(ce->engine->status_page.vma) + in create_timestamp()
1129 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in record_registers()
1262 *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) + in poison_registers()
1609 *cs++ = i915_ggtt_offset(ce->state) + in emit_indirect_ctx_bb_canary()
Dintel_timeline.c209 i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_pin()
317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno()
354 *hwsp = i915_ggtt_offset(tl->hwsp_ggtt) + in intel_timeline_read_hwsp()
Dintel_context_sseu.c27 offset = i915_ggtt_offset(ce->state) + in gen8_emit_rpcs_config()
Dselftest_mocs.c237 offset = i915_ggtt_offset(vma); in check_mocs_engine()
242 offset -= i915_ggtt_offset(vma); in check_mocs_engine()
Dintel_gt.h72 return i915_ggtt_offset(gt->scratch) + field; in intel_gt_scratch_offset()
Dintel_ring_submission.c137 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
221 ENGINE_WRITE_FW(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
269 i915_ggtt_offset(ring->vma)); in xcs_resume()
756 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
763 *cs++ = i915_ggtt_offset(ce->state) | flags; in mi_set_context()
Dintel_renderstate.c89 so->batch_offset = i915_ggtt_offset(so->vma); in render_state_setup()
Dselftest_timeline.c850 w->addr = i915_ggtt_offset(vma); in setup_watcher()
885 w->addr = i915_ggtt_offset(w->vma); in create_watcher()
899 GEM_BUG_ON(w->addr - i915_ggtt_offset(w->vma) > w->vma->size); in check_watcher()
912 end = (w->addr - i915_ggtt_offset(w->vma)) / sizeof(*w->map); in check_watcher()
Dgen8_engine_cs.c336 return (i915_ggtt_offset(engine->status_page.vma) + in preempt_address()
654 return i915_ggtt_offset(rq->context->state) + in ccs_semaphore_offset()
Dselftest_execlists.c837 *cs++ = i915_ggtt_offset(vma) + 4 * idx; in emit_semaphore_chain()
842 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in emit_semaphore_chain()
911 *cs++ = i915_ggtt_offset(vma) + 4 * (idx - 1); in release_queue()
1056 i915_ggtt_offset(ce->engine->status_page.vma) + in create_rewinder()
1618 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1629 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
1668 *cs++ = i915_ggtt_offset(vma); in live_busywait_preempt()
3237 *cs++ = i915_ggtt_offset(global); in preempt_user()
4260 *cs++ = i915_ggtt_offset(scratch) + n * sizeof(u32); in preserved_virtual_engine()
Dselftest_engine_pm.c77 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
Dintel_context.c263 i915_ggtt_offset(ce->ring->vma), in __intel_context_do_pin_ww()
Dintel_engine_cs.c1779 i915_ggtt_offset(rq->ring->vma), in print_ring()
2060 i915_ggtt_offset(rq->ring->vma)); in engine_dump_request()
/Linux-v6.1/drivers/gpu/drm/i915/display/
Dintel_dsb.c257 i915_ggtt_offset(dsb->vma)); in intel_dsb_commit()
271 i915_ggtt_offset(dsb->vma), tail); in intel_dsb_commit()
273 i915_ggtt_offset(dsb->vma) + tail); in intel_dsb_commit()
Dintel_overlay.c848 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
865 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
867 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1366 overlay->flip_addr = i915_ggtt_offset(vma); in get_registers()
Dintel_fbdev.c314 i915_ggtt_offset(vma)); in intelfb_create()
Dintel_display_types.h2062 return i915_ggtt_offset(plane_state->ggtt_vma); in intel_plane_ggtt_offset()
/Linux-v6.1/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_coherency.c226 *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
227 *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); in gpu_set()
232 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
236 *cs++ = i915_ggtt_offset(vma) + offset; in gpu_set()
/Linux-v6.1/drivers/gpu/drm/i915/selftests/
Di915_perf.c239 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_delay()
346 i915_ggtt_offset(stream->noa_wait), 0, in live_noa_gpr()
372 *cs++ = i915_ggtt_offset(rq->engine->status_page.vma) + in live_noa_gpr()
/Linux-v6.1/drivers/gpu/drm/i915/
Di915_perf.c464 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in oa_buffer_check_unlocked()
654 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_append_oa_reports()
948 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_append_oa_reports()
1260 stream->specific_ctx_id = i915_ggtt_offset(ce->state); in oa_get_render_ctx_id()
1411 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen7_init_oa_buffer()
1457 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen8_init_oa_buffer()
1511 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma); in gen12_init_oa_buffer()
1755 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4; in alloc_noa_wait()
1792 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4; in alloc_noa_wait()
1915 *cs++ = i915_ggtt_offset(stream->noa_wait); in alloc_oa_config_buffer()
[all …]
Di915_vma.h127 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
/Linux-v6.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.h343 u32 offset = i915_ggtt_offset(vma); in intel_guc_ggtt_offset()
Dintel_guc_submission.c2524 desc->process_desc = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69()
2526 desc->wq_addr = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v69()
2597 wq_desc_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70()
2599 wq_base_offset = i915_ggtt_offset(ce->state) + in prepare_context_registration_info_v70()
2698 if (i915_ggtt_offset(ce->state) != in __guc_context_pin()
3945 i915_ggtt_offset(engine->status_page.vma)); in setup_hwsp()
4775 return i915_ggtt_offset(ce->state) + in get_children_go_addr()
4785 return i915_ggtt_offset(ce->state) + in get_children_join_addr()
/Linux-v6.1/drivers/gpu/drm/i915/gvt/
Dscheduler.c569 bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma); in prepare_shadow_batch_buffer()
642 wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma); in prepare_shadow_wa_ctx()

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