Searched refs:glitch (Results 1 – 11 of 11) sorted by relevance
150 struct catpt_notify_glitch glitch; in catpt_dsp_notify_stream() local168 memcpy_fromio(&glitch, catpt_inbox_addr(cdev), sizeof(glitch)); in catpt_dsp_notify_stream()169 trace_catpt_ipc_payload((u8 *)&glitch, sizeof(glitch)); in catpt_dsp_notify_stream()172 glitch.type, glitch.presentation_pos, in catpt_dsp_notify_stream()173 glitch.write_pos); in catpt_dsp_notify_stream()
378 bool glitch) in __nmk_gpio_set_mode_safe() argument383 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()395 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()1530 bool glitch; in nmk_pmx_set() local1562 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); in nmk_pmx_set()1564 if (glitch) { in nmk_pmx_set()1604 (g->altsetting & NMK_GPIO_ALT_C), glitch); in nmk_pmx_set()1624 if (glitch) { in nmk_pmx_set()
38 Definition: List of pinctrl settings to apply to keep HSIC pins in a glitch
743 * VPU_0 and VPU_1 muxed to a single clock by a glitch745 * Same for VAPB but with a final gate after the glitch free mux.
812 * VPU_0 and VPU_1 muxed to a single clock by a glitch814 * Same for VAPB but with a final gate after the glitch free mux.
1240 * VPU_0 and VPU_1 muxed to a single clock by a glitch1242 * Same for VAPB but with a final gate after the glitch free mux.
1637 * VPU_0 and VPU_1 muxed to a single clock by a glitch1639 * Same for VAPB but with a final gate after the glitch free mux.
56 input de-glitch/debounce logic, sometimes with software controls.
40 input de-glitch/debounce logic, sometimes with software controls.286 setup of an output GPIO's value. This allows a glitch-free migration from a676 initializing the value as low. To ensure glitch free
77 initializing the value as low. To ensure glitch free
107 do not suffer from almost any glitch due to the background workload.
