Searched refs:dummy_pstate_table (Results 1 – 3 of 3) sorted by relevance
457 …if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i]… in dcn30_fpu_calculate_wm_and_dlg()460 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[… in dcn30_fpu_calculate_wm_and_dlg()638 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()704 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600; in dcn3_fpu_build_wm_range_table()705 base->bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 38; in dcn3_fpu_build_wm_range_table()706 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000; in dcn3_fpu_build_wm_range_table()707 base->bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn3_fpu_build_wm_range_table()708 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000; in dcn3_fpu_build_wm_range_table()709 base->bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn3_fpu_build_wm_range_table()710 base->bw_params->dummy_pstate_table[3].dram_speed_mts = 16000; in dcn3_fpu_build_wm_range_table()[all …]
223 …clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()224 clk_mgr->base.bw_params->dummy_pstate_table[0].dummy_pstate_latency_us = 50; in dcn32_build_wm_range_table_fpu()225 …clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()226 clk_mgr->base.bw_params->dummy_pstate_table[1].dummy_pstate_latency_us = 9; in dcn32_build_wm_range_table_fpu()227 …clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()228 clk_mgr->base.bw_params->dummy_pstate_table[2].dummy_pstate_latency_us = 8; in dcn32_build_wm_range_table_fpu()229 …clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()230 clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pstate_latency_us = 5; in dcn32_build_wm_range_table_fpu()235 …tries[WM_D].dml_input.pstate_latency_us = clk_mgr->base.bw_params->dummy_pstate_table[3].dummy_pst… in dcn32_build_wm_range_table_fpu()266 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()[all …]
235 struct dummy_pstate_entry dummy_pstate_table[4]; member
