Searched refs:dfixed_const (Results 1 – 15 of 15) sorted by relevance
81 tmp.full = dfixed_const(100); in rs690_pm_info()82 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); in rs690_pm_info()85 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); in rs690_pm_info()87 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); in rs690_pm_info()90 rdev->pm.igp_system_mclk.full = dfixed_const(400); in rs690_pm_info()91 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); in rs690_pm_info()92 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); in rs690_pm_info()95 tmp.full = dfixed_const(100); in rs690_pm_info()96 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); in rs690_pm_info()99 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); in rs690_pm_info()[all …]
949 a.full = dfixed_const(100); in rv515_crtc_bandwidth_compute()950 sclk.full = dfixed_const(selected_sclk); in rv515_crtc_bandwidth_compute()953 if (crtc->vsc.full > dfixed_const(2)) in rv515_crtc_bandwidth_compute()954 wm->num_line_pair.full = dfixed_const(2); in rv515_crtc_bandwidth_compute()956 wm->num_line_pair.full = dfixed_const(1); in rv515_crtc_bandwidth_compute()958 b.full = dfixed_const(mode->crtc_hdisplay); in rv515_crtc_bandwidth_compute()959 c.full = dfixed_const(256); in rv515_crtc_bandwidth_compute()963 if (a.full < dfixed_const(4)) { in rv515_crtc_bandwidth_compute()975 a.full = dfixed_const(mode->clock); in rv515_crtc_bandwidth_compute()976 b.full = dfixed_const(1000); in rv515_crtc_bandwidth_compute()[all …]
1956 a.full = dfixed_const(1000); in evergreen_dram_bandwidth()1957 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth()1959 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth()1960 a.full = dfixed_const(10); in evergreen_dram_bandwidth()1961 dram_efficiency.full = dfixed_const(7); in evergreen_dram_bandwidth()1976 a.full = dfixed_const(1000); in evergreen_dram_bandwidth_for_display()1977 yclk.full = dfixed_const(wm->yclk); in evergreen_dram_bandwidth_for_display()1979 dram_channels.full = dfixed_const(wm->dram_channels * 4); in evergreen_dram_bandwidth_for_display()1980 a.full = dfixed_const(10); in evergreen_dram_bandwidth_for_display()1981 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in evergreen_dram_bandwidth_for_display()[all …]
2075 a.full = dfixed_const(1000); in dce6_dram_bandwidth()2076 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth()2078 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth()2079 a.full = dfixed_const(10); in dce6_dram_bandwidth()2080 dram_efficiency.full = dfixed_const(7); in dce6_dram_bandwidth()2095 a.full = dfixed_const(1000); in dce6_dram_bandwidth_for_display()2096 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth_for_display()2098 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth_for_display()2099 a.full = dfixed_const(10); in dce6_dram_bandwidth_for_display()2100 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce6_dram_bandwidth_for_display()[all …]
3262 temp_ff.full = dfixed_const(temp); in r100_bandwidth_update()3269 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3270 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ in r100_bandwidth_update()3272 temp_ff.full = dfixed_const(pixel_bytes1); in r100_bandwidth_update()3276 temp_ff.full = dfixed_const(1000); in r100_bandwidth_update()3277 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ in r100_bandwidth_update()3279 temp_ff.full = dfixed_const(pixel_bytes2); in r100_bandwidth_update()3325 trcd_ff.full = dfixed_const(mem_trcd); in r100_bandwidth_update()3326 trp_ff.full = dfixed_const(mem_trp); in r100_bandwidth_update()3327 tras_ff.full = dfixed_const(mem_tras); in r100_bandwidth_update()[all …]
8930 a.full = dfixed_const(1000); in dce8_dram_bandwidth()8931 yclk.full = dfixed_const(wm->yclk); in dce8_dram_bandwidth()8933 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce8_dram_bandwidth()8934 a.full = dfixed_const(10); in dce8_dram_bandwidth()8935 dram_efficiency.full = dfixed_const(7); in dce8_dram_bandwidth()8959 a.full = dfixed_const(1000); in dce8_dram_bandwidth_for_display()8960 yclk.full = dfixed_const(wm->yclk); in dce8_dram_bandwidth_for_display()8962 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce8_dram_bandwidth_for_display()8963 a.full = dfixed_const(10); in dce8_dram_bandwidth_for_display()8964 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce8_dram_bandwidth_for_display()[all …]
1763 a.full = dfixed_const(src_v); in radeon_crtc_scaling_mode_fixup()1764 b.full = dfixed_const(dst_v); in radeon_crtc_scaling_mode_fixup()1766 a.full = dfixed_const(src_h); in radeon_crtc_scaling_mode_fixup()1767 b.full = dfixed_const(dst_h); in radeon_crtc_scaling_mode_fixup()1770 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()1771 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
731 a.full = dfixed_const(100); in radeon_update_bandwidth_info()732 rdev->pm.sclk.full = dfixed_const(sclk); in radeon_update_bandwidth_info()734 rdev->pm.mclk.full = dfixed_const(mclk); in radeon_update_bandwidth_info()738 a.full = dfixed_const(16); in radeon_update_bandwidth_info()
35 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ macro40 #define dfixed_init(A) { .full = dfixed_const((A)) }49 return dfixed_const(non_frac); in dfixed_floor()56 if (A.full > dfixed_const(non_frac)) in dfixed_ceil()57 return dfixed_const(non_frac + 1); in dfixed_ceil()59 return dfixed_const(non_frac); in dfixed_ceil()
526 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth()527 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth()529 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth()530 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth()531 dram_efficiency.full = dfixed_const(7); in dce_v6_0_dram_bandwidth()555 a.full = dfixed_const(1000); in dce_v6_0_dram_bandwidth_for_display()556 yclk.full = dfixed_const(wm->yclk); in dce_v6_0_dram_bandwidth_for_display()558 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v6_0_dram_bandwidth_for_display()559 a.full = dfixed_const(10); in dce_v6_0_dram_bandwidth_for_display()560 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v6_0_dram_bandwidth_for_display()[all …]
663 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth()664 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth()666 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth()667 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth()668 dram_efficiency.full = dfixed_const(7); in dce_v8_0_dram_bandwidth()692 a.full = dfixed_const(1000); in dce_v8_0_dram_bandwidth_for_display()693 yclk.full = dfixed_const(wm->yclk); in dce_v8_0_dram_bandwidth_for_display()695 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v8_0_dram_bandwidth_for_display()696 a.full = dfixed_const(10); in dce_v8_0_dram_bandwidth_for_display()697 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v8_0_dram_bandwidth_for_display()[all …]
728 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth()729 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth()731 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth()732 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth()733 dram_efficiency.full = dfixed_const(7); in dce_v10_0_dram_bandwidth()757 a.full = dfixed_const(1000); in dce_v10_0_dram_bandwidth_for_display()758 yclk.full = dfixed_const(wm->yclk); in dce_v10_0_dram_bandwidth_for_display()760 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v10_0_dram_bandwidth_for_display()761 a.full = dfixed_const(10); in dce_v10_0_dram_bandwidth_for_display()762 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v10_0_dram_bandwidth_for_display()[all …]
754 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth()755 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth()757 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth()758 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth()759 dram_efficiency.full = dfixed_const(7); in dce_v11_0_dram_bandwidth()783 a.full = dfixed_const(1000); in dce_v11_0_dram_bandwidth_for_display()784 yclk.full = dfixed_const(wm->yclk); in dce_v11_0_dram_bandwidth_for_display()786 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce_v11_0_dram_bandwidth_for_display()787 a.full = dfixed_const(10); in dce_v11_0_dram_bandwidth_for_display()788 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ in dce_v11_0_dram_bandwidth_for_display()[all …]
1378 a.full = dfixed_const(src_v); in amdgpu_display_crtc_scaling_mode_fixup()1379 b.full = dfixed_const(dst_v); in amdgpu_display_crtc_scaling_mode_fixup()1381 a.full = dfixed_const(src_h); in amdgpu_display_crtc_scaling_mode_fixup()1382 b.full = dfixed_const(dst_h); in amdgpu_display_crtc_scaling_mode_fixup()1385 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()1386 amdgpu_crtc->hsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
151 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()152 inf.full -= dfixed_const(1); in compute_dda_inc()155 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); in compute_dda_inc()
