Searched refs:dcn3_0_soc (Results 1 – 3 of 3) sorted by relevance
125 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { variable541 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn30_fpu_update_dram_channel_width_bytes()549 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()551 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_update_max_clk()553 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_update_max_clk()555 dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_fpu_update_max_clk()566 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()567 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()568 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans * in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()569 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()[all …]
39 extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc;
1513 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc; in init_soc_bounding_box()1528 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc); in init_soc_bounding_box()2117 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn30_update_bw_bounding_box()2208 dcn3_0_soc.num_states = num_states; in dcn30_update_bw_bounding_box()2433 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); in dcn30_resource_construct()
