Searched refs:dclr0 (Results 1 – 2 of 2) sorted by relevance
1313 if (pvt->dclr0 & BIT(bit)) in determine_edac_cap()1474 debug_dump_dramcfg_low(pvt, pvt->dclr0, 0); in __dump_misc_regs()1685 pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; in determine_memory_type()1692 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; in determine_memory_type()1713 else if (pvt->dclr0 & BIT(16)) in determine_memory_type()1732 pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3; in determine_memory_type()1742 flag = pvt->dclr0 & WIDTH_128; in k8_early_channel_count()1745 flag = pvt->dclr0 & REVE_WIDTH_128; in k8_early_channel_count()1960 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()2017 if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128)) in f1x_early_channel_count()[all …]
370 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ member
