Searched refs:dcefclk (Results 1 – 7 of 7) sorted by relevance
344 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()361 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()382 &smu->smu_table.boot_values.dcefclk); in smu_v12_0_get_vbios_bootup_values()
638 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()652 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()667 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()698 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; in smu_v13_0_get_vbios_bootup_values()925 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v13_0_init_max_sustainable_clocks()
583 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()600 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()621 &smu->smu_table.boot_values.dcefclk); in smu_v11_0_get_vbios_bootup_values()864 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1071 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1089 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1107 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1125 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1062 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1080 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1098 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1116 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
290 uint32_t dcefclk; member
1331 smu->smu_table.boot_values.dcefclk / 100); in smu_smc_hw_setup()
