| /Linux-v6.1/drivers/memory/ |
| D | ti-aemif.c | 123 unsigned long clk_rate; member
179 unsigned long clk_rate = aemif->clk_rate; in aemif_config_abus() local
185 ta = aemif_calc_rate(pdev, data->ta, clk_rate, TA_MAX); in aemif_config_abus()
186 rhold = aemif_calc_rate(pdev, data->rhold, clk_rate, RHOLD_MAX); in aemif_config_abus()
187 rstrobe = aemif_calc_rate(pdev, data->rstrobe, clk_rate, RSTROBE_MAX); in aemif_config_abus()
188 rsetup = aemif_calc_rate(pdev, data->rsetup, clk_rate, RSETUP_MAX); in aemif_config_abus()
189 whold = aemif_calc_rate(pdev, data->whold, clk_rate, WHOLD_MAX); in aemif_config_abus()
190 wstrobe = aemif_calc_rate(pdev, data->wstrobe, clk_rate, WSTROBE_MAX); in aemif_config_abus()
191 wsetup = aemif_calc_rate(pdev, data->wsetup, clk_rate, WSETUP_MAX); in aemif_config_abus()
217 static inline int aemif_cycles_to_nsec(int val, unsigned long clk_rate) in aemif_cycles_to_nsec() argument
[all …]
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| /Linux-v6.1/drivers/clocksource/ |
| D | timer-oxnas-rps.c | 130 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clockevent_init() local
135 rps->timer_period = DIV_ROUND_UP(clk_rate, HZ); in oxnas_rps_clockevent_init()
136 timer_rate = clk_rate; in oxnas_rps_clockevent_init()
140 timer_rate = clk_rate / 16; in oxnas_rps_clockevent_init()
145 timer_rate = clk_rate / 256; in oxnas_rps_clockevent_init()
167 clk_rate, in oxnas_rps_clockevent_init()
185 ulong clk_rate = clk_get_rate(rps->clk); in oxnas_rps_clocksource_init() local
189 clk_rate = clk_rate / 16; in oxnas_rps_clocksource_init()
197 TIMER_BITS, clk_rate); in oxnas_rps_clocksource_init()
200 clk_rate, 250, TIMER_BITS, in oxnas_rps_clocksource_init()
[all …]
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| D | timer-microchip-pit64b.c | 231 static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, in mchp_pit64b_pres_compute() argument
237 tmp = clk_rate / (*pres + 1); in mchp_pit64b_pres_compute()
340 u32 clk_rate) in mchp_pit64b_init_clksrc() argument
366 ret = clocksource_register_hz(&cs->clksrc, clk_rate); in mchp_pit64b_init_clksrc()
377 sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); in mchp_pit64b_init_clksrc()
383 u32 clk_rate, u32 irq) in mchp_pit64b_init_clkevt() argument
392 mchp_pit64b_ce_cycles = DIV_ROUND_CLOSEST(clk_rate, HZ); in mchp_pit64b_init_clkevt()
416 clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ULONG_MAX); in mchp_pit64b_init_clkevt()
425 unsigned long clk_rate; in mchp_pit64b_dt_init_timer() local
456 clk_rate = clk_get_rate(timer.gclk); in mchp_pit64b_dt_init_timer()
[all …]
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| D | timer-vf-pit.c | 153 unsigned long clk_rate; in pit_timer_init() local
182 clk_rate = clk_get_rate(pit_clk); in pit_timer_init()
183 cycle_per_jiffy = clk_rate / (HZ); in pit_timer_init()
188 ret = pit_clocksource_init(clk_rate); in pit_timer_init()
192 return pit_clockevent_init(clk_rate, irq); in pit_timer_init()
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| /Linux-v6.1/drivers/ufs/host/ |
| D | ufs-mediatek-trace.h | 32 TP_PROTO(const char *name, bool scale_up, unsigned long clk_rate),
33 TP_ARGS(name, scale_up, clk_rate),
38 __field(unsigned long, clk_rate)
44 __entry->clk_rate = clk_rate;
50 __entry->clk_rate)
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| /Linux-v6.1/drivers/char/hw_random/ |
| D | ks-sa-rng.c | 93 static unsigned int cycles_to_ns(unsigned long clk_rate, unsigned int cycles) in cycles_to_ns() argument
96 cycles, clk_rate); in cycles_to_ns()
99 static unsigned int startup_delay_ns(unsigned long clk_rate) in startup_delay_ns() argument
102 return cycles_to_ns(clk_rate, BIT(24)); in startup_delay_ns()
103 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_STARTUP_CYCLES); in startup_delay_ns()
106 static unsigned int refill_delay_ns(unsigned long clk_rate) in refill_delay_ns() argument
109 return cycles_to_ns(clk_rate, BIT(24)); in refill_delay_ns()
110 return cycles_to_ns(clk_rate, 256 * TRNG_DEF_MAX_REFILL_CYCLES); in refill_delay_ns()
118 unsigned long clk_rate = clk_get_rate(ks_sa_rng->clk); in ks_sa_rng_init() local
147 ks_sa_rng->refill_delay_ns = refill_delay_ns(clk_rate); in ks_sa_rng_init()
[all …]
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| /Linux-v6.1/drivers/watchdog/ |
| D | loongson1_wdt.c | 23 unsigned long clk_rate; member
45 counts = drvdata->clk_rate * min(timeout, max_hw_heartbeat); in ls1x_wdt_set_timeout()
92 unsigned long clk_rate; in ls1x_wdt_probe() local
117 clk_rate = clk_get_rate(drvdata->clk); in ls1x_wdt_probe()
118 if (!clk_rate) in ls1x_wdt_probe()
120 drvdata->clk_rate = clk_rate; in ls1x_wdt_probe()
127 ls1x_wdt->max_hw_heartbeat_ms = U32_MAX / clk_rate * 1000; in ls1x_wdt_probe()
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| D | imgpdc_wdt.c | 116 unsigned long clk_rate = clk_get_rate(wdt->wdt_clk); in __pdc_wdt_set_timeout() local
120 val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1; in __pdc_wdt_set_timeout()
188 unsigned long clk_rate; in pdc_wdt_probe() local
232 clk_rate = clk_get_rate(pdc_wdt->wdt_clk); in pdc_wdt_probe()
233 if (clk_rate == 0) { in pdc_wdt_probe()
238 if (order_base_2(clk_rate) > PDC_WDT_CONFIG_DELAY_MASK + 1) { in pdc_wdt_probe()
243 if (order_base_2(clk_rate) == 0) in pdc_wdt_probe()
252 do_div(div, clk_rate); in pdc_wdt_probe()
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| D | renesas_wdt.c | 37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
52 unsigned long clk_rate; member
80 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate); in rwdt_wait_cycles()
143 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); in rwdt_restart()
155 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate)); in rwdt_restart()
237 priv->clk_rate = clk_get_rate(priv->clk); in rwdt_probe()
242 if (!priv->clk_rate) { in rwdt_probe()
248 clks_per_sec = priv->clk_rate / clk_divs[i]; in rwdt_probe()
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| D | apple_wdt.c | 59 unsigned long clk_rate; member
100 writel_relaxed(wdt->clk_rate * s, wdt->regs + APPLE_WDT_WD1_BITE_TIME); in apple_wdt_set_timeout()
115 return (reset_time - cur_time) / wdt->clk_rate; in apple_wdt_get_timeleft()
188 wdt->clk_rate = clk_get_rate(clk); in apple_wdt_probe()
189 if (!wdt->clk_rate) in apple_wdt_probe()
194 wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate; in apple_wdt_probe()
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| D | lantiq_wdt.c | 64 unsigned long clk_rate; member
103 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_start()
131 timeout = wdt->timeout * priv->clk_rate; in ltq_wdt_ping()
147 return do_div(timeout, priv->clk_rate); in ltq_wdt_get_timeleft()
219 priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER; in ltq_wdt_probe()
220 if (!priv->clk_rate) { in ltq_wdt_probe()
230 wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate; in ltq_wdt_probe()
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| D | orion_wdt.c | 76 unsigned long clk_rate; member
95 dev->clk_rate = clk_get_rate(dev->clk); in orion_wdt_clock_init()
118 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada370_wdt_clock_init()
138 dev->clk_rate = clk_get_rate(dev->clk); in armada375_wdt_clock_init()
157 dev->clk_rate = clk_get_rate(dev->clk) / WDT_A370_RATIO; in armada375_wdt_clock_init()
181 dev->clk_rate = clk_get_rate(dev->clk); in armadaxp_wdt_clock_init()
189 writel(dev->clk_rate * wdt_dev->timeout, in orion_wdt_ping()
192 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in orion_wdt_ping()
204 writel(dev->clk_rate * wdt_dev->timeout, in armada375_start()
207 writel(dev->clk_rate * (wdt_dev->timeout - wdt_dev->pretimeout), in armada375_start()
[all …]
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| D | lpc18xx_wdt.c | 55 unsigned long clk_rate; member
107 val = DIV_ROUND_UP(lpc18xx_wdt->wdt_dev.timeout * lpc18xx_wdt->clk_rate, in __lpc18xx_wdt_set_timeout()
129 return (val * LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_get_timeleft()
252 lpc18xx_wdt->clk_rate = clk_get_rate(lpc18xx_wdt->wdt_clk); in lpc18xx_wdt_probe()
253 if (lpc18xx_wdt->clk_rate == 0) { in lpc18xx_wdt_probe()
262 LPC18XX_WDT_CLK_DIV, lpc18xx_wdt->clk_rate); in lpc18xx_wdt_probe()
265 LPC18XX_WDT_CLK_DIV) / lpc18xx_wdt->clk_rate; in lpc18xx_wdt_probe()
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| /Linux-v6.1/drivers/mfd/ |
| D | intel-lpss-acpi.c | 32 .clk_rate = 120000000,
46 .clk_rate = 120000000,
62 .clk_rate = 120000000,
77 .clk_rate = 100000000,
93 .clk_rate = 133000000,
109 .clk_rate = 133000000,
123 .clk_rate = 120000000,
128 .clk_rate = 216000000,
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| /Linux-v6.1/drivers/pwm/ |
| D | pwm-omap-dmtimer.c | 85 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) in pwm_omap_dmtimer_get_clock_cycles() argument
87 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); in pwm_omap_dmtimer_get_clock_cycles()
158 unsigned long clk_rate; in pwm_omap_dmtimer_config() local
174 clk_rate = clk_get_rate(fclk); in pwm_omap_dmtimer_config()
175 if (!clk_rate) { in pwm_omap_dmtimer_config()
180 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate); in pwm_omap_dmtimer_config()
198 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); in pwm_omap_dmtimer_config()
199 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); in pwm_omap_dmtimer_config()
204 period_ns, clk_rate); in pwm_omap_dmtimer_config()
211 duty_ns, clk_rate); in pwm_omap_dmtimer_config()
[all …]
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| D | pwm-sunplus.c | 60 u64 clk_rate; in sunplus_pwm_apply() local
77 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_apply()
84 if (clk_rate > (u64)SP7021_PWM_FREQ_SCALER * NSEC_PER_SEC) in sunplus_pwm_apply()
91 dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER in sunplus_pwm_apply()
116 duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate, in sunplus_pwm_apply()
132 u64 clk_rate; in sunplus_pwm_get_state() local
137 clk_rate = clk_get_rate(priv->clk); in sunplus_pwm_get_state()
146 * NSEC_PER_SEC, clk_rate); in sunplus_pwm_get_state()
151 clk_rate); in sunplus_pwm_get_state()
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| D | pwm-keembay.c | 97 unsigned long clk_rate; in keembay_pwm_get_state() local
100 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_get_state()
113 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); in keembay_pwm_get_state()
114 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); in keembay_pwm_get_state()
124 unsigned long clk_rate; in keembay_pwm_apply() local
152 clk_rate = clk_get_rate(priv->clk); in keembay_pwm_apply()
153 div = clk_rate * state->duty_cycle; in keembay_pwm_apply()
159 div = clk_rate * state->period; in keembay_pwm_apply()
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| D | pwm-sun4i.c | 116 u64 clk_rate, tmp; in sun4i_pwm_get_state() local
120 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_get_state()
131 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
161 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
164 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
172 u64 clk_rate, div = 0; in sun4i_pwm_calculate() local
175 clk_rate = clk_get_rate(sun4i_pwm->clk); in sun4i_pwm_calculate()
179 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
181 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); in sun4i_pwm_calculate()
[all …]
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| D | pwm-lpss.c | 37 .clk_rate = 25000000,
45 .clk_rate = 19200000,
54 .clk_rate = 19200000,
63 .clk_rate = 19200000,
128 unsigned long c = lpwm->info->clk_rate, base_unit_range; in pwm_lpss_prepare()
224 freq = base_unit * lpwm->info->clk_rate; in pwm_lpss_get_state()
265 c = lpwm->info->clk_rate; in pwm_lpss_probe()
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| D | pwm-rockchip.c | 66 unsigned long clk_rate; in rockchip_pwm_get_state() local
79 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
83 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
87 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in rockchip_pwm_get_state()
106 u64 clk_rate, div; in rockchip_pwm_config() local
109 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_config()
116 div = clk_rate * state->period; in rockchip_pwm_config()
120 div = clk_rate * state->duty_cycle; in rockchip_pwm_config()
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| /Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_core_perf.c | 289 u64 clk_rate = kms->perf.perf_tune.min_core_clk; in _dpu_core_perf_get_core_clk_rate() local
296 clk_rate = max(dpu_cstate->new_perf.core_clk_rate, in _dpu_core_perf_get_core_clk_rate()
297 clk_rate); in _dpu_core_perf_get_core_clk_rate()
298 clk_rate = clk_round_rate(kms->perf.core_clk, in _dpu_core_perf_get_core_clk_rate()
299 clk_rate); in _dpu_core_perf_get_core_clk_rate()
304 clk_rate = kms->perf.fix_core_clk_rate; in _dpu_core_perf_get_core_clk_rate()
306 DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); in _dpu_core_perf_get_core_clk_rate()
308 return clk_rate; in _dpu_core_perf_get_core_clk_rate()
316 u64 clk_rate = 0; in dpu_core_perf_crtc_update() local
393 clk_rate = _dpu_core_perf_get_core_clk_rate(kms); in dpu_core_perf_crtc_update()
[all …]
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| /Linux-v6.1/arch/m68k/include/asm/ |
| D | mcfclk.h | 32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ argument
35 .rate = clk_rate, \
42 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ argument
44 .rate = clk_rate, \
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| /Linux-v6.1/drivers/nvmem/ |
| D | vf610-ocotp.c | 116 u32 clk_rate; in vf610_ocotp_calculate_timing() local
120 clk_rate = clk_get_rate(ocotp_dev->clk); in vf610_ocotp_calculate_timing()
123 relax = clk_rate / (1000000000 / DEF_RELAX) - 1; in vf610_ocotp_calculate_timing()
124 strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
125 strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1; in vf610_ocotp_calculate_timing()
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| /Linux-v6.1/drivers/media/rc/ |
| D | meson-ir-tx.c | 76 unsigned long clk_rate; member
81 unsigned int cnt = DIV_ROUND_CLOSEST(ir->clk_rate, ir->carrier); in meson_irtx_set_mod()
86 ir->carrier, NSEC_PER_SEC / ir->clk_rate * cnt, in meson_irtx_set_mod()
296 ir->clk_rate = clk_get_rate(clock) / 3; in meson_irtx_mod_clock_probe()
298 if (ir->clk_rate < IRB_MOD_1US_CLK_RATE) { in meson_irtx_mod_clock_probe()
300 ir->clk_rate = IRB_MOD_1US_CLK_RATE; in meson_irtx_mod_clock_probe()
303 dev_info(ir->dev, "F_clk = %luHz\n", ir->clk_rate); in meson_irtx_mod_clock_probe()
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| /Linux-v6.1/drivers/phy/ralink/ |
| D | phy-mt7621-pci.c | 121 unsigned long clk_rate; in mt7621_set_phy_for_ssc() local
123 clk_rate = clk_get_rate(phy->sys_clk); in mt7621_set_phy_for_ssc()
124 if (!clk_rate) in mt7621_set_phy_for_ssc()
143 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
149 } else if (clk_rate == 25000000) { /* 25MHz Xal */ in mt7621_set_phy_for_ssc()
200 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
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