| /Linux-v6.1/drivers/clk/zynqmp/ |
| D | pll.c | 53 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_get_mode() local
60 __func__, clk_name, ret); in zynqmp_pll_get_mode()
76 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_mode() local
88 __func__, clk_name, ret); in zynqmp_pll_set_mode()
138 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_recalc_rate() local
148 __func__, clk_name, ret); in zynqmp_pll_recalc_rate()
182 const char *clk_name = clk_hw_get_name(hw); in zynqmp_pll_set_rate() local
200 clk_name); in zynqmp_pll_set_rate()
203 __func__, clk_name, ret); in zynqmp_pll_set_rate()
214 __func__, clk_name, ret); in zynqmp_pll_set_rate()
[all …]
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| D | clk-gate-zynqmp.c | 37 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_enable() local
45 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_enable()
57 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_disable() local
65 __func__, clk_name, clk_id, ret); in zynqmp_clk_gate_disable()
77 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_gate_is_enabled() local
84 __func__, clk_name, ret); in zynqmp_clk_gate_is_enabled()
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| D | clkc.c | 71 char clk_name[MAX_NAME_LEN]; member
160 static int zynqmp_get_clock_name(u32 clk_id, char *clk_name) in zynqmp_get_clock_name() argument
166 strscpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in zynqmp_get_clock_name()
585 static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name, in zynqmp_register_clk_topology() argument
605 clk_out[j] = kasprintf(GFP_KERNEL, "%s%s", clk_name, in zynqmp_register_clk_topology()
608 clk_out[j] = kasprintf(GFP_KERNEL, "%s", clk_name); in zynqmp_register_clk_topology()
620 __func__, clk_dev_id, clk_name, in zynqmp_register_clk_topology()
645 char clk_name[MAX_NAME_LEN]; in zynqmp_register_clocks() local
648 if (zynqmp_get_clock_name(i, clk_name)) in zynqmp_register_clocks()
662 clock[i].clk_name); in zynqmp_register_clocks()
[all …]
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| D | divider.c | 83 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_recalc_rate() local
93 __func__, clk_name, ret); in zynqmp_clk_divider_recalc_rate()
106 clk_name); in zynqmp_clk_divider_recalc_rate()
172 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_round_rate() local
184 __func__, clk_name, ret); in zynqmp_clk_divider_round_rate()
229 const char *clk_name = clk_hw_get_name(hw); in zynqmp_clk_divider_set_rate() local
251 __func__, clk_name, ret); in zynqmp_clk_divider_set_rate()
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| /Linux-v6.1/drivers/gpu/drm/msm/dp/ |
| D | dp_parser.c | 111 const char *clk_name) in dp_parser_check_prefix() argument
113 return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); in dp_parser_check_prefix()
120 const char *clk_name; in dp_parser_init_clk_data() local
134 "clock-names", i, &clk_name); in dp_parser_init_clk_data()
138 if (dp_parser_check_prefix("core", clk_name)) in dp_parser_init_clk_data()
141 if (dp_parser_check_prefix("ctrl", clk_name)) in dp_parser_init_clk_data()
144 if (dp_parser_check_prefix("stream", clk_name)) in dp_parser_init_clk_data()
200 const char *clk_name; in dp_parser_clock() local
220 i, &clk_name); in dp_parser_clock()
225 if (dp_parser_check_prefix("core", clk_name) && in dp_parser_clock()
[all …]
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| /Linux-v6.1/drivers/clk/sunxi/ |
| D | clk-a10-pll2.c | 41 const char *clk_name = node->name, *parent; in sun4i_pll2_setup() local
121 SUN4I_A10_PLL2_1X, &clk_name); in sun4i_pll2_setup()
122 clks[SUN4I_A10_PLL2_1X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
136 SUN4I_A10_PLL2_2X, &clk_name); in sun4i_pll2_setup()
137 clks[SUN4I_A10_PLL2_2X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
145 SUN4I_A10_PLL2_4X, &clk_name); in sun4i_pll2_setup()
146 clks[SUN4I_A10_PLL2_4X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
154 SUN4I_A10_PLL2_8X, &clk_name); in sun4i_pll2_setup()
155 clks[SUN4I_A10_PLL2_8X] = clk_register_fixed_factor(NULL, clk_name, in sun4i_pll2_setup()
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| D | clk-sun4i-pll3.c | 23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
36 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_pll3_setup()
57 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_pll3_setup()
64 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_pll3_setup()
71 clk_name); in sun4i_a10_pll3_setup()
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| D | clk-sun4i-display.c | 105 const char *clk_name = node->name; in sun4i_a10_display_init() local
115 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_display_init()
119 pr_err("%s: Could not map the clock registers\n", clk_name); in sun4i_a10_display_init()
125 pr_err("%s: Could not retrieve the parents\n", clk_name); in sun4i_a10_display_init()
157 clk = clk_register_composite(NULL, clk_name, in sun4i_a10_display_init()
165 pr_err("%s: Couldn't register the clock\n", clk_name); in sun4i_a10_display_init()
171 pr_err("%s: Couldn't register DT provider\n", clk_name); in sun4i_a10_display_init()
198 clk_name); in sun4i_a10_display_init()
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| D | clk-sunxi.c | 655 const char *clk_name = node->name; in sunxi_mux_clk_setup() local
667 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_mux_clk_setup()
673 clk = clk_register_mux(NULL, clk_name, parents, i, in sunxi_mux_clk_setup()
680 clk_name, PTR_ERR(clk)); in sunxi_mux_clk_setup()
686 __func__, clk_name); in sunxi_mux_clk_setup()
779 const char *clk_name = node->name; in sunxi_divider_clk_setup() local
791 if (of_property_read_string(node, "clock-output-names", &clk_name)) { in sunxi_divider_clk_setup()
797 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
803 __func__, clk_name, PTR_ERR(clk)); in sunxi_divider_clk_setup()
809 __func__, clk_name); in sunxi_divider_clk_setup()
[all …]
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| D | clk-a10-codec.c | 17 const char *clk_name = node->name, *parent_name; in sun4i_codec_clk_setup() local
24 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_codec_clk_setup()
27 clk = clk_register_gate(NULL, clk_name, parent_name, in sun4i_codec_clk_setup()
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| D | clk-sun4i-tcon-ch1.c | 227 const char *clk_name = node->name; in tcon_ch1_setup() local
235 of_property_read_string(node, "clock-output-names", &clk_name); in tcon_ch1_setup()
239 pr_err("%s: Could not map the clock registers\n", clk_name); in tcon_ch1_setup()
245 pr_err("%s Could not retrieve the parents\n", clk_name); in tcon_ch1_setup()
253 init.name = clk_name; in tcon_ch1_setup()
265 pr_err("%s: Couldn't register the clock\n", clk_name); in tcon_ch1_setup()
271 pr_err("%s: Couldn't register our clock provider\n", clk_name); in tcon_ch1_setup()
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| D | clk-sun6i-apb0.c | 33 const char *clk_name = np->name; in sun6i_a31_apb0_clk_probe() local
46 of_property_read_string(np, "clock-output-names", &clk_name); in sun6i_a31_apb0_clk_probe()
48 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, in sun6i_a31_apb0_clk_probe()
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| /Linux-v6.1/drivers/mailbox/ |
| D | qcom-apcs-ipc-mailbox.c | 29 char *clk_name; member
33 .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
37 .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
41 .offset = 8, .clk_name = NULL
45 .offset = 16, .clk_name = NULL
49 .offset = 12, .clk_name = NULL
53 .offset = 0x1008, .clk_name = "qcom-sdx55-acps-clk"
118 if (apcs_data->clk_name) { in qcom_apcs_ipc_probe()
120 apcs_data->clk_name, in qcom_apcs_ipc_probe()
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| /Linux-v6.1/drivers/clk/pxa/ |
| D | clk-pxa.h | 19 #define MUX_RO_RATE_RO_OPS(name, clk_name) \ argument
31 return clk_register_composite(NULL, clk_name, \
39 #define RATE_RO_OPS(name, clk_name) \ argument
46 return clk_register_composite(NULL, clk_name, \
54 #define RATE_OPS(name, clk_name) \ argument
63 return clk_register_composite(NULL, clk_name, \
71 #define MUX_OPS(name, clk_name, flags) \ argument
80 return clk_register_composite(NULL, clk_name, \
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| /Linux-v6.1/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_10nm.c | 577 char clk_name[32]; in pll_10nm_register() local
583 .name = clk_name, in pll_10nm_register()
594 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_10nm->phy->id); in pll_10nm_register()
601 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_10nm->phy->id); in pll_10nm_register()
603 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_10nm_register()
613 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_10nm->phy->id); in pll_10nm_register()
616 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_10nm_register()
625 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_10nm->phy->id); in pll_10nm_register()
628 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, in pll_10nm_register()
637 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_10nm->phy->id); in pll_10nm_register()
[all …]
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| D | dsi_phy_7nm.c | 591 char clk_name[32]; in pll_7nm_register() local
597 .name = clk_name, in pll_7nm_register()
608 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_7nm->phy->id); in pll_7nm_register()
615 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_out_div_clk", pll_7nm->phy->id); in pll_7nm_register()
617 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_7nm_register()
627 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_bit_clk", pll_7nm->phy->id); in pll_7nm_register()
630 pll_bit = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_7nm_register()
639 snprintf(clk_name, sizeof(clk_name), "dsi%d_phy_pll_out_byteclk", pll_7nm->phy->id); in pll_7nm_register()
642 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, in pll_7nm_register()
652 snprintf(clk_name, sizeof(clk_name), "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); in pll_7nm_register()
[all …]
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| D | dsi_phy_28nm.c | 522 char clk_name[32]; in pll_28nm_register() local
528 .name = clk_name, in pll_28nm_register()
542 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_28nm->phy->id); in pll_28nm_register()
548 snprintf(clk_name, sizeof(clk_name), "dsi%danalog_postdiv_clk", pll_28nm->phy->id); in pll_28nm_register()
549 analog_postdiv = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_28nm_register()
557 snprintf(clk_name, sizeof(clk_name), "dsi%dindirect_path_div2_clk", pll_28nm->phy->id); in pll_28nm_register()
559 clk_name, analog_postdiv, CLK_SET_RATE_PARENT, 1, 2); in pll_28nm_register()
563 snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_28nm->phy->id); in pll_28nm_register()
564 hw = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_28nm_register()
572 snprintf(clk_name, sizeof(clk_name), "dsi%dbyte_mux", pll_28nm->phy->id); in pll_28nm_register()
[all …]
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| /Linux-v6.1/drivers/clk/mvebu/ |
| D | clk-cpu.c | 36 const char *clk_name; member
198 char *clk_name = kzalloc(5, GFP_KERNEL); in of_cpu_clk_setup() local
201 if (WARN_ON(!clk_name)) in of_cpu_clk_setup()
208 sprintf(clk_name, "cpu%d", cpu); in of_cpu_clk_setup()
211 cpuclk[cpu].clk_name = clk_name; in of_cpu_clk_setup()
218 init.name = cpuclk[cpu].clk_name; in of_cpu_clk_setup()
237 kfree(cpuclk[ncpus].clk_name); in of_cpu_clk_setup()
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| /Linux-v6.1/drivers/clk/ |
| D | clk-nspire.c | 69 const char *clk_name = node->name; in nspire_ahbdiv_setup() local
81 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_ahbdiv_setup()
84 hw = clk_hw_register_fixed_factor(NULL, clk_name, parent_name, 0, in nspire_ahbdiv_setup()
111 const char *clk_name = node->name; in nspire_clk_setup() local
122 of_property_read_string(node, "clock-output-names", &clk_name); in nspire_clk_setup()
124 hw = clk_hw_register_fixed_rate(NULL, clk_name, NULL, 0, in nspire_clk_setup()
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| /Linux-v6.1/drivers/clk/samsung/ |
| D | clk-exynos-arm64.c | 76 if (cmu->clk_name) { in exynos_arm64_register_cmu()
80 parent_clk = clk_get(dev, cmu->clk_name); in exynos_arm64_register_cmu()
82 parent_clk = of_clk_get_by_name(np, cmu->clk_name); in exynos_arm64_register_cmu()
86 __func__, cmu->clk_name, PTR_ERR(parent_clk)); in exynos_arm64_register_cmu()
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| /Linux-v6.1/drivers/clk/keystone/ |
| D | pll.c | 254 const char *clk_name = node->name; in of_pll_div_clk_init() local
256 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_div_clk_init()
282 clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, in of_pll_div_clk_init()
287 pr_err("%s: error registering divider %s\n", __func__, clk_name); in of_pll_div_clk_init()
303 const char *clk_name = node->name; in of_pll_mux_clk_init() local
305 of_property_read_string(node, "clock-output-names", &clk_name); in of_pll_mux_clk_init()
328 clk = clk_register_mux(NULL, clk_name, (const char **)&parents, in of_pll_mux_clk_init()
334 pr_err("%s: error registering mux %s\n", __func__, clk_name); in of_pll_mux_clk_init()
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| /Linux-v6.1/tools/testing/selftests/kvm/x86_64/ |
| D | kvm_clock_test.c | 142 char *clk_name; in check_clocksource() local
159 clk_name = malloc(st.st_size); in check_clocksource()
160 TEST_ASSERT(clk_name, "failed to allocate buffer to read file\n"); in check_clocksource()
162 if (!fgets(clk_name, st.st_size, fp)) { in check_clocksource()
168 TEST_ASSERT(!strncmp(clk_name, "tsc\n", st.st_size), in check_clocksource()
169 "clocksource not supported: %s", clk_name); in check_clocksource()
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| /Linux-v6.1/drivers/media/platform/mediatek/vcodec/ |
| D | mtk_vcodec_enc_pm.c | 45 "clock-names", i, &clk_info->clk_name); in mtk_vcodec_init_enc_clk()
51 clk_info->clk_name); in mtk_vcodec_init_enc_clk()
54 clk_info->clk_name); in mtk_vcodec_init_enc_clk()
71 enc_clk->clk_info[i].clk_name, ret); in mtk_vcodec_enc_clock_on()
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| /Linux-v6.1/drivers/clk/ti/ |
| D | fixed-factor.c | 31 const char *clk_name = ti_dt_clk_name(node); in of_ti_fixed_factor_clk_setup() local
51 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags, in of_ti_fixed_factor_clk_setup()
57 ti_clk_add_alias(NULL, clk, clk_name); in of_ti_fixed_factor_clk_setup()
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| D | clockdomain.c | 102 const char *clk_name; in omap2_init_clk_clkdm() local
107 clk_name = __clk_get_name(hw->clk); in omap2_init_clk_clkdm()
112 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
116 clk_name, clk->clkdm_name); in omap2_init_clk_clkdm()
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