Searched refs:clk_dif_sr (Results 1 – 1 of 1) sorted by relevance
67 u8 clk_dif_sr; member164 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); in rs9_get_output_config()165 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); in rs9_get_output_config()177 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); in rs9_get_output_config()178 rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx); in rs9_get_output_config()180 rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx); in rs9_get_output_config()181 rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx); in rs9_get_output_config()252 if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)) in rs9_update_config()256 rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i)); in rs9_update_config()
