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Searched refs:caches (Results 1 – 25 of 145) sorted by relevance

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/Linux-v6.1/kernel/bpf/
Dmemalloc.c410 ma->caches = pcc; in bpf_mem_alloc_init()
438 free_percpu(ma->caches); in free_mem_alloc_no_barrier()
440 ma->caches = NULL; in free_mem_alloc_no_barrier()
483 copy->caches = ma->caches; in destroy_mem_alloc()
484 ma->caches = NULL; in destroy_mem_alloc()
517 if (ma->caches) { in bpf_mem_alloc_destroy()
520 cc = per_cpu_ptr(ma->caches, cpu); in bpf_mem_alloc_destroy()
617 ret = unit_alloc(this_cpu_ptr(ma->caches)->cache + idx); in bpf_mem_alloc()
632 unit_free(this_cpu_ptr(ma->caches)->cache + idx, ptr); in bpf_mem_free()
/Linux-v6.1/tools/cgroup/
Dmemcg_slabinfo.py184 caches = {}
203 caches[addr] = cache
215 for addr in caches:
217 cache_show(caches[addr], cfg, stats[addr])
/Linux-v6.1/Documentation/block/
Dwriteback_cache_control.rst9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
/Linux-v6.1/arch/arm/boot/compressed/
Dhead-xscale.S28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
/Linux-v6.1/arch/arm/mm/
Dproc-arm720.S46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
Dproc-sa110.S49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
Dproc-fa526.S39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm926.S53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mov r0, #4 @ disable write-back on caches explicitly
Dproc-sa1100.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm920.S61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-mohawk.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
359 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
Dproc-arm740.S40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
Dproc-arm925.S84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
436 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mov r0, #4 @ disable write-back on caches explicitly
Dproc-arm1020e.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
415 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1022.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1026.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm922.S63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
380 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-xsc3.S92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
430 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
450 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
Dproc-arm1020.S69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
/Linux-v6.1/include/linux/
Dbpf_mem_alloc.h12 struct bpf_mem_caches __percpu *caches; member
/Linux-v6.1/arch/openrisc/
DKconfig80 bool "Have write through data caches"
83 Select this if your implementation features write through data caches.
85 caches at relevant times. Most OpenRISC implementations support write-
86 through data caches.
/Linux-v6.1/drivers/acpi/numa/
Dhmat.c66 struct list_head caches; member
141 INIT_LIST_HEAD(&target->caches); in alloc_memory_target()
414 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
697 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
798 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
/Linux-v6.1/Documentation/filesystems/nfs/
Drpc-cache.rst13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
/Linux-v6.1/Documentation/mm/
Dslub.rst9 slab caches. SLUB always includes full debugging but it is off by default.
58 O Switch debugging off for caches that would have
84 a result of storing the metadata (for example, caches with PAGE_SIZE object
87 switch off debugging for such caches by default, use::
97 You can also enable options (e.g. sanity checks and poisoning) for all caches
391 For more information about current state of SLUB caches with the user tracking
393 /sys/kernel/debug/slab/<cache>/ (created only for caches with enabled user
/Linux-v6.1/tools/testing/selftests/zram/
DREADME9 use as swap disks, various caches under /var and maybe many more :)

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