| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_fpu_populate_dml_writeback_from_context()
371 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
372 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
383 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
385 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
386 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
390 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_fpu_calculate_wm_and_dlg()
391 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
395 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 259 const struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
265 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
269 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
319 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
321 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
323 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
325 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
355 double vco_speed = context->bw_ctx.dml.soc.dispclk_dppclk_vco_speed_mhz; in dcn32_predict_pipe_split()
364 dml32_CalculateODMMode(context->bw_ctx.dml.ip.maximum_pixels_per_line_per_dsc_unit, in dcn32_predict_pipe_split()
369 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 929 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_fpu_set_wb_arb_params()
930 …rams->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_c… in dcn20_fpu_set_wb_arb_params()
990 if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0 || optimized_min_dst_y_next_start_us > 5000) in decide_zstate_support()
1013 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1014 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1015 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1016 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1018 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1019 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1021 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 457 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
458 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
470 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
473 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
487 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
491 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 351 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
352 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
353 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
359 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
360 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
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| D | dc.c | 1869 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_commit_state_no_check()
1871 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_state_no_check()
2013 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_post_update_surfaces_to_stream()
2015 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_post_update_surfaces_to_stream()
2044 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
2607 …if (!dc->clk_mgr->funcs->are_clock_states_equal(&dc->clk_mgr->clks, &dc->current_state->bw_ctx.bw.… in dc_check_update_surfaces_for_stream()
2610 …} else if (memcmp(&dc->current_state->bw_ctx.bw.dcn.clk, &dc->clk_mgr->clks, offsetof(struct dc_cl… in dc_check_update_surfaces_for_stream()
3905 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_updates_for_stream()
3999 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib)); in dc_set_power_state()
4006 dc->current_state->bw_ctx.dml = *dml; in dc_set_power_state()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 901 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
909 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
910 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
924 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce112_validate_bandwidth()
925 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce112_validate_bandwidth()
926 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
927 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce112_validate_bandwidth()
930 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce112_validate_bandwidth()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 979 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
989 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
990 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1004 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1005 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1006 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1009 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1010 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce110_validate_bandwidth()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 436 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg_fp()
437 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
441 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_calculate_wm_and_dlg_fp()
442 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
446 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_calculate_wm_and_dlg_fp()
447 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
452 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_calculate_wm_and_dlg_fp()
453 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg_fp()
459 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg_fp()
460 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg_fp()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
629 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 350 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
359 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
364 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
366 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
379 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1391 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params()
1409 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; in dcn30_set_mcif_arb_params()
1652 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1658 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1659 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1660 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1669 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1677 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn30_internal_validate_bw()
1679 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1681 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 841 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
843 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
845 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
853 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
855 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
856 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
865 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
895 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
919 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
923 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 475 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
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| D | dcn10_hw_sequencer.c | 463 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
464 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_log_hw_state()
465 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
466 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
467 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()
468 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
469 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
1460 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dcn10_init_hw()
1461 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz; in dcn10_init_hw()
2711 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1623 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; in dcn20_set_mcif_arb_params()
1836 struct vba_vars_st *v = &context->bw_ctx.dml.vba; in dcn20_validate_apply_pipe_split_flags()
1891 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1896 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2043 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn20_fast_validate_bw()
2045 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2063 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
2082 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) in dcn20_fast_validate_bw()
2092 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn20_fast_validate_bw()
2096 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn20_fast_validate_bw()
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| D | dcn20_hwseq.c | 1926 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth()
1939 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth()
1946 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
1952 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth()
1956 if (context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes) in dcn20_prepare_bandwidth()
1957 compbuf_size_kb = context->bw_ctx.dml.ip.min_comp_buffer_size_kbytes; in dcn20_prepare_bandwidth()
1959 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; in dcn20_prepare_bandwidth()
1977 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth()
1984 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
1990 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn20_optimize_bandwidth()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| D | dce60_clk_mgr.c | 126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 850 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
851 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce100_validate_bandwidth()
853 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
854 context->bw_ctx.bw.dce.yclk_khz = 0; in dce100_validate_bandwidth()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn315/ |
| D | dcn315_resource.c | 1643 …const int max_usable_det = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes - DCN3_15_MI… in dcn315_populate_dml_pipes_from_context()
1694 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1696 if (context->bw_ctx.dml.ip.det_buffer_size_kbytes > DCN3_15_MAX_DET_SIZE) in dcn315_populate_dml_pipes_from_context()
1697 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_15_MAX_DET_SIZE; in dcn315_populate_dml_pipes_from_context()
1698 ASSERT(context->bw_ctx.dml.ip.det_buffer_size_kbytes >= DCN3_15_DEFAULT_DET_SIZE); in dcn315_populate_dml_pipes_from_context()
1704 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn315_populate_dml_pipes_from_context()
1708 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn315_populate_dml_pipes_from_context()
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