/Linux-v6.1/drivers/gpu/drm/ast/ |
D | ast_dp.c | 29 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid() 36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4, in ast_astdp_read_edid() 95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid() 101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid() 165 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_dp_launch() 184 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); in ast_dp_power_on_off() 195 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); in ast_dp_set_on_off() 277 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0, ASTDP_AND_CLEAR_MASK, in ast_dp_set_mode() 279 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); in ast_dp_set_mode() 280 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx); in ast_dp_set_mode()
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D | ast_mode.c | 276 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]); in ast_set_std_reg() 283 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_std_reg() 320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_crtc_reg() 325 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); in ast_set_crtc_reg() 330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); in ast_set_crtc_reg() 335 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); in ast_set_crtc_reg() 342 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); in ast_set_crtc_reg() 347 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); in ast_set_crtc_reg() 352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); in ast_set_crtc_reg() 354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); in ast_set_crtc_reg() [all …]
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D | ast_dp501.c | 36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack() 44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack() 81 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40); in set_cmd_trigger() 86 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00); in clear_cmd_trigger() 113 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_cmd() 135 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_data() 169 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00); 403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); in ast_init_dvo() 432 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x00); in ast_init_analog()
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D | ast_i2c.c | 38 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7); in ast_i2c_setsda() 54 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7); in ast_i2c_setscl()
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D | ast_post.c | 93 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg() 102 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg() 103 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg() 110 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg() 395 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
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D | ast_drv.h | 287 void ast_set_index_reg_mask(struct ast_private *ast,
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D | ast_main.c | 40 void ast_set_index_reg_mask(struct ast_private *ast, in ast_set_index_reg_mask() function
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