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/Linux-v6.1/arch/arm/boot/dts/
Dimx7ulp.dtsi154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
261 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
262 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
[all …]
Dexynos4412-odroid-common.dtsi126 assigned-clocks = <&clock CLK_FOUT_EPLL>;
127 assigned-clock-rates = <45158401>;
131 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
137 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
140 assigned-clock-rates = <0>, <0>,
208 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
210 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
211 assigned-clock-rates = <0>, <176000000>;
216 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
218 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
[all …]
Dimx7d-pico.dtsi105 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
107 assigned-clock-parents = <&clks IMX7D_CKIL>;
108 assigned-clock-rates = <0>, <32768>;
121 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
123 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
124 assigned-clock-rates = <0>, <100000000>;
278 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
280 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
281 assigned-clock-rates = <0>, <24576000>;
313 assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
[all …]
Dimx7d-cl-som-imx7.dts47 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
49 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
50 assigned-clock-rates = <0>, <100000000>;
75 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
77 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
78 assigned-clock-rates = <0>, <100000000>;
197 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
198 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
212 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
213 assigned-clock-rates = <400000000>;
Dimx7d-zii-rpu2.dts189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
[all …]
Dimx7d-sdb.dts217 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
219 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
220 assigned-clock-rates = <0>, <100000000>;
244 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
246 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
247 assigned-clock-rates = <0>, <100000000>;
388 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
391 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
392 assigned-clock-rates = <0>, <884736000>, <12288000>;
424 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
[all …]
Dimx7d-remarkable2.dts61 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
63 assigned-clock-parents = <&clks IMX7D_CKIL>;
64 assigned-clock-rates = <0>, <32768>;
94 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
95 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
102 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
103 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
140 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
141 assigned-clock-rates = <400000000>;
Dsama7g5.dtsi323 assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
324 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
325 assigned-clock-rates = <40000000>;
339 assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
340 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
341 assigned-clock-rates = <40000000>;
355 assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
356 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>;
357 assigned-clock-rates = <40000000>;
371 assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
[all …]
Dimx7s-warp.dts84 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
85 assigned-clock-rates = <884736000>;
268 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
270 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
271 assigned-clock-rates = <0>, <36864000>;
278 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
279 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
286 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
287 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
295 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
[all …]
Dimx7d-nitrogen7.dts114 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
116 assigned-clock-parents = <&clks IMX7D_CKIL>;
117 assigned-clock-rates = <0>, <32768>;
131 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
133 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
134 assigned-clock-rates = <0>, <100000000>;
322 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
323 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
330 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
331 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dbrcm,cygnus-audio.txt13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
Dmt2701-afe-pcm.txt47 - assigned-clocks: list of input clocks and dividers for the audio system.
49 - assigned-clocks-parents: parent of input clocks of assigned clocks.
50 - assigned-clock-rates: list of clock frequencies of assigned clocks.
138 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
142 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
144 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dimx8ulp.dtsi191 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
192 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
226 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
227 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
228 assigned-clock-rates = <48000000>;
239 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
240 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
241 assigned-clock-rates = <48000000>;
272 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
273 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
[all …]
Dimx8mq-mnt-reform2.dts105 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
106 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
107 assigned-clock-rates = <25000000>;
175 assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
176 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
177 /delete-property/assigned-clock-rates;
236 assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
237 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
238 assigned-clock-rates = <25000000>;
275 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
[all …]
Dimx8mn-evk.dtsi214 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
215 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
216 assigned-clock-rates = <24576000>;
223 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
224 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
225 assigned-clock-rates = <24576000>;
237 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
238 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
239 assigned-clock-rates = <24576000>;
252 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
[all …]
Dimx8mm-tqma8mqml-mba8mx.dts85 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
87 assigned-clock-rates = <10000000>, <250000000>;
88 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
94 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
95 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
109 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
110 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
114 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
115 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
Dimx8mm-beacon-baseboard.dtsi151 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
152 assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
153 assigned-clock-rates = <24000000>;
247 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
249 assigned-clock-rates = <10000000>, <250000000>;
250 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
259 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
260 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
261 assigned-clock-rates = <24576000>;
279 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
[all …]
Dimx8mq-evk.dts407 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
408 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
409 assigned-clock-rates = <0>, <24576000>;
417 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
418 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
419 assigned-clock-rates = <24576000>;
430 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
431 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
432 assigned-clock-rates = <24576000>;
437 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
[all …]
Dimx8mq.dtsi554 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
558 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
561 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
652 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
660 assigned-clock-rates = <0>, <0>,
667 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
750 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
754 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
758 assigned-clock-rates = <600000000>,
1046 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
[all …]
Dimx8mm-emcon.dtsi530 assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
531 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
532 assigned-clock-rates = <12000000>;
539 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
540 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
541 assigned-clock-rates = <24576000>;
556 assigned-clocks = <&clk IMX8MM_CLK_UART1>;
557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
564 assigned-clocks = <&clk IMX8MM_CLK_UART2>;
565 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
[all …]
/Linux-v6.1/arch/mips/boot/dts/img/
Dpistachio.dtsi51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
[all …]
/Linux-v6.1/drivers/s390/char/
Dsclp_cmd.c242 u16 assigned; member
265 for (i = 0; i < sccb->assigned; i++) { in sclp_attach_storage()
424 static void __init insert_increment(u16 rn, int standby, int assigned) in insert_increment() argument
438 if (assigned && incr->rn > rn) in insert_increment()
440 if (!assigned && incr->rn - last_rn > 1) in insert_increment()
445 if (!assigned) in insert_increment()
457 int i, id, assigned, rc; in sclp_detect_standby_memory() local
467 assigned = 0; in sclp_detect_standby_memory()
477 for (i = 0; i < sccb->assigned; i++) { in sclp_detect_standby_memory()
480 assigned++; in sclp_detect_standby_memory()
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-am65-iot2050-common-pg2.dtsi32 assigned-clocks = <&k3_clks 67 0>;
36 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
37 assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
41 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
Dk3-j721e-common-proc-board.dts625 assigned-clocks = <&k3_clks 157 371>;
626 assigned-clock-parents = <&k3_clks 157 400>;
627 assigned-clock-rates = <24576000>; /* for 48KHz */
679 assigned-clocks = <&k3_clks 152 1>,
683 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
783 assigned-clocks = <&wiz0_pll1_refclk>;
784 assigned-clock-parents = <&cmn_refclk1>;
788 assigned-clocks = <&wiz0_refclk_dig>;
789 assigned-clock-parents = <&cmn_refclk1>;
793 assigned-clocks = <&wiz1_pll1_refclk>;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-typec.txt11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;

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