1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13 #include <linux/acpi.h>
14 #include <linux/bitfield.h>
15 #include <linux/bits.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/limits.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/rtc.h>
25 #include <linux/suspend.h>
26 #include <linux/seq_file.h>
27 #include <linux/uaccess.h>
28
29 /* SMU communication registers */
30 #define AMD_PMC_REGISTER_MESSAGE 0x538
31 #define AMD_PMC_REGISTER_RESPONSE 0x980
32 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC
33
34 /* PMC Scratch Registers */
35 #define AMD_PMC_SCRATCH_REG_CZN 0x94
36 #define AMD_PMC_SCRATCH_REG_YC 0xD14
37
38 /* STB Registers */
39 #define AMD_PMC_STB_INDEX_ADDRESS 0xF8
40 #define AMD_PMC_STB_INDEX_DATA 0xFC
41 #define AMD_PMC_STB_PMI_0 0x03E30600
42 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
43 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
44 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
45
46 /* STB S2D(Spill to DRAM) has different message port offset */
47 #define STB_SPILL_TO_DRAM 0xBE
48 #define AMD_S2D_REGISTER_MESSAGE 0xA20
49 #define AMD_S2D_REGISTER_RESPONSE 0xA80
50 #define AMD_S2D_REGISTER_ARGUMENT 0xA88
51
52 /* STB Spill to DRAM Parameters */
53 #define S2D_TELEMETRY_BYTES_MAX 0x100000
54 #define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
55
56 /* Base address of SMU for mapping physical address to virtual address */
57 #define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
58 #define AMD_PMC_SMU_INDEX_DATA 0xBC
59 #define AMD_PMC_MAPPING_SIZE 0x01000
60 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000
61 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8
62 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC
63 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
64 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
65
66 /* SMU Response Codes */
67 #define AMD_PMC_RESULT_OK 0x01
68 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
69 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
70 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
71 #define AMD_PMC_RESULT_FAILED 0xFF
72
73 /* FCH SSC Registers */
74 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
75 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
76 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
77 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
78 #define FCH_SSC_MAPPING_SIZE 0x800
79 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100
80 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000
81
82 /* SMU Message Definations */
83 #define SMU_MSG_GETSMUVERSION 0x02
84 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
85 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
86 #define SMU_MSG_LOG_START 0x06
87 #define SMU_MSG_LOG_RESET 0x07
88 #define SMU_MSG_LOG_DUMP_DATA 0x08
89 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
90 /* List of supported CPU ids */
91 #define AMD_CPU_ID_RV 0x15D0
92 #define AMD_CPU_ID_RN 0x1630
93 #define AMD_CPU_ID_PCO AMD_CPU_ID_RV
94 #define AMD_CPU_ID_CZN AMD_CPU_ID_RN
95 #define AMD_CPU_ID_YC 0x14B5
96 #define AMD_CPU_ID_CB 0x14D8
97 #define AMD_CPU_ID_PS 0x14E8
98
99 #define PMC_MSG_DELAY_MIN_US 50
100 #define RESPONSE_REGISTER_LOOP_MAX 20000
101
102 #define SOC_SUBSYSTEM_IP_MAX 12
103 #define DELAY_MIN_US 2000
104 #define DELAY_MAX_US 3000
105 #define FIFO_SIZE 4096
106 enum amd_pmc_def {
107 MSG_TEST = 0x01,
108 MSG_OS_HINT_PCO,
109 MSG_OS_HINT_RN,
110 };
111
112 enum s2d_arg {
113 S2D_TELEMETRY_SIZE = 0x01,
114 S2D_PHYS_ADDR_LOW,
115 S2D_PHYS_ADDR_HIGH,
116 };
117
118 struct amd_pmc_bit_map {
119 const char *name;
120 u32 bit_mask;
121 };
122
123 static const struct amd_pmc_bit_map soc15_ip_blk[] = {
124 {"DISPLAY", BIT(0)},
125 {"CPU", BIT(1)},
126 {"GFX", BIT(2)},
127 {"VDD", BIT(3)},
128 {"ACP", BIT(4)},
129 {"VCN", BIT(5)},
130 {"ISP", BIT(6)},
131 {"NBIO", BIT(7)},
132 {"DF", BIT(8)},
133 {"USB0", BIT(9)},
134 {"USB1", BIT(10)},
135 {"LAPIC", BIT(11)},
136 {}
137 };
138
139 struct amd_pmc_dev {
140 void __iomem *regbase;
141 void __iomem *smu_virt_addr;
142 void __iomem *stb_virt_addr;
143 void __iomem *fch_virt_addr;
144 bool msg_port;
145 u32 base_addr;
146 u32 cpu_id;
147 u32 active_ips;
148 /* SMU version information */
149 u8 smu_program;
150 u8 major;
151 u8 minor;
152 u8 rev;
153 struct device *dev;
154 struct pci_dev *rdev;
155 struct mutex lock; /* generic mutex lock */
156 struct dentry *dbgfs_dir;
157 };
158
159 static bool enable_stb;
160 module_param(enable_stb, bool, 0644);
161 MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
162
163 static struct amd_pmc_dev pmc;
164 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
165 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
166 #ifdef CONFIG_SUSPEND
167 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
168 #endif
169
amd_pmc_reg_read(struct amd_pmc_dev * dev,int reg_offset)170 static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
171 {
172 return ioread32(dev->regbase + reg_offset);
173 }
174
amd_pmc_reg_write(struct amd_pmc_dev * dev,int reg_offset,u32 val)175 static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
176 {
177 iowrite32(val, dev->regbase + reg_offset);
178 }
179
180 struct smu_metrics {
181 u32 table_version;
182 u32 hint_count;
183 u32 s0i3_last_entry_status;
184 u32 timein_s0i2;
185 u64 timeentering_s0i3_lastcapture;
186 u64 timeentering_s0i3_totaltime;
187 u64 timeto_resume_to_os_lastcapture;
188 u64 timeto_resume_to_os_totaltime;
189 u64 timein_s0i3_lastcapture;
190 u64 timein_s0i3_totaltime;
191 u64 timein_swdrips_lastcapture;
192 u64 timein_swdrips_totaltime;
193 u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
194 u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
195 } __packed;
196
amd_pmc_stb_debugfs_open(struct inode * inode,struct file * filp)197 static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
198 {
199 struct amd_pmc_dev *dev = filp->f_inode->i_private;
200 u32 size = FIFO_SIZE * sizeof(u32);
201 u32 *buf;
202 int rc;
203
204 buf = kzalloc(size, GFP_KERNEL);
205 if (!buf)
206 return -ENOMEM;
207
208 rc = amd_pmc_read_stb(dev, buf);
209 if (rc) {
210 kfree(buf);
211 return rc;
212 }
213
214 filp->private_data = buf;
215 return rc;
216 }
217
amd_pmc_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)218 static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
219 loff_t *pos)
220 {
221 if (!filp->private_data)
222 return -EINVAL;
223
224 return simple_read_from_buffer(buf, size, pos, filp->private_data,
225 FIFO_SIZE * sizeof(u32));
226 }
227
amd_pmc_stb_debugfs_release(struct inode * inode,struct file * filp)228 static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
229 {
230 kfree(filp->private_data);
231 return 0;
232 }
233
234 static const struct file_operations amd_pmc_stb_debugfs_fops = {
235 .owner = THIS_MODULE,
236 .open = amd_pmc_stb_debugfs_open,
237 .read = amd_pmc_stb_debugfs_read,
238 .release = amd_pmc_stb_debugfs_release,
239 };
240
amd_pmc_stb_debugfs_open_v2(struct inode * inode,struct file * filp)241 static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
242 {
243 struct amd_pmc_dev *dev = filp->f_inode->i_private;
244 u32 *buf;
245
246 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
247 if (!buf)
248 return -ENOMEM;
249
250 memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
251 filp->private_data = buf;
252
253 return 0;
254 }
255
amd_pmc_stb_debugfs_read_v2(struct file * filp,char __user * buf,size_t size,loff_t * pos)256 static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
257 loff_t *pos)
258 {
259 if (!filp->private_data)
260 return -EINVAL;
261
262 return simple_read_from_buffer(buf, size, pos, filp->private_data,
263 S2D_TELEMETRY_BYTES_MAX);
264 }
265
amd_pmc_stb_debugfs_release_v2(struct inode * inode,struct file * filp)266 static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
267 {
268 kfree(filp->private_data);
269 return 0;
270 }
271
272 static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
273 .owner = THIS_MODULE,
274 .open = amd_pmc_stb_debugfs_open_v2,
275 .read = amd_pmc_stb_debugfs_read_v2,
276 .release = amd_pmc_stb_debugfs_release_v2,
277 };
278
amd_pmc_setup_smu_logging(struct amd_pmc_dev * dev)279 static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
280 {
281 if (dev->cpu_id == AMD_CPU_ID_PCO) {
282 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
283 return -EINVAL;
284 }
285
286 /* Get Active devices list from SMU */
287 if (!dev->active_ips)
288 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
289
290 /* Get dram address */
291 if (!dev->smu_virt_addr) {
292 u32 phys_addr_low, phys_addr_hi;
293 u64 smu_phys_addr;
294
295 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
296 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
297 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
298
299 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
300 sizeof(struct smu_metrics));
301 if (!dev->smu_virt_addr)
302 return -ENOMEM;
303 }
304
305 /* Start the logging */
306 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
307 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
308
309 return 0;
310 }
311
amd_pmc_idlemask_read(struct amd_pmc_dev * pdev,struct device * dev,struct seq_file * s)312 static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
313 struct seq_file *s)
314 {
315 u32 val;
316
317 switch (pdev->cpu_id) {
318 case AMD_CPU_ID_CZN:
319 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
320 break;
321 case AMD_CPU_ID_YC:
322 case AMD_CPU_ID_CB:
323 case AMD_CPU_ID_PS:
324 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
325 break;
326 default:
327 return -EINVAL;
328 }
329
330 if (dev)
331 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
332
333 if (s)
334 seq_printf(s, "SMU idlemask : 0x%x\n", val);
335
336 return 0;
337 }
338
get_metrics_table(struct amd_pmc_dev * pdev,struct smu_metrics * table)339 static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
340 {
341 if (!pdev->smu_virt_addr) {
342 int ret = amd_pmc_setup_smu_logging(pdev);
343
344 if (ret)
345 return ret;
346 }
347
348 if (pdev->cpu_id == AMD_CPU_ID_PCO)
349 return -ENODEV;
350 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
351 return 0;
352 }
353
354 #ifdef CONFIG_SUSPEND
amd_pmc_validate_deepest(struct amd_pmc_dev * pdev)355 static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
356 {
357 struct smu_metrics table;
358
359 if (get_metrics_table(pdev, &table))
360 return;
361
362 if (!table.s0i3_last_entry_status)
363 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
364 else
365 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
366 table.timein_s0i3_lastcapture);
367 }
368 #endif
369
amd_pmc_get_smu_version(struct amd_pmc_dev * dev)370 static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
371 {
372 int rc;
373 u32 val;
374
375 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
376 if (rc)
377 return rc;
378
379 dev->smu_program = (val >> 24) & GENMASK(7, 0);
380 dev->major = (val >> 16) & GENMASK(7, 0);
381 dev->minor = (val >> 8) & GENMASK(7, 0);
382 dev->rev = (val >> 0) & GENMASK(7, 0);
383
384 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
385 dev->smu_program, dev->major, dev->minor, dev->rev);
386
387 return 0;
388 }
389
smu_fw_version_show(struct device * d,struct device_attribute * attr,char * buf)390 static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
391 char *buf)
392 {
393 struct amd_pmc_dev *dev = dev_get_drvdata(d);
394
395 if (!dev->major) {
396 int rc = amd_pmc_get_smu_version(dev);
397
398 if (rc)
399 return rc;
400 }
401 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
402 }
403
smu_program_show(struct device * d,struct device_attribute * attr,char * buf)404 static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
405 char *buf)
406 {
407 struct amd_pmc_dev *dev = dev_get_drvdata(d);
408
409 if (!dev->major) {
410 int rc = amd_pmc_get_smu_version(dev);
411
412 if (rc)
413 return rc;
414 }
415 return sysfs_emit(buf, "%u\n", dev->smu_program);
416 }
417
418 static DEVICE_ATTR_RO(smu_fw_version);
419 static DEVICE_ATTR_RO(smu_program);
420
421 static struct attribute *pmc_attrs[] = {
422 &dev_attr_smu_fw_version.attr,
423 &dev_attr_smu_program.attr,
424 NULL,
425 };
426 ATTRIBUTE_GROUPS(pmc);
427
smu_fw_info_show(struct seq_file * s,void * unused)428 static int smu_fw_info_show(struct seq_file *s, void *unused)
429 {
430 struct amd_pmc_dev *dev = s->private;
431 struct smu_metrics table;
432 int idx;
433
434 if (get_metrics_table(dev, &table))
435 return -EINVAL;
436
437 seq_puts(s, "\n=== SMU Statistics ===\n");
438 seq_printf(s, "Table Version: %d\n", table.table_version);
439 seq_printf(s, "Hint Count: %d\n", table.hint_count);
440 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
441 "Unknown/Fail");
442 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
443 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
444 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
445 table.timeto_resume_to_os_lastcapture);
446
447 seq_puts(s, "\n=== Active time (in us) ===\n");
448 for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
449 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
450 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
451 table.timecondition_notmet_lastcapture[idx]);
452 }
453
454 return 0;
455 }
456 DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
457
s0ix_stats_show(struct seq_file * s,void * unused)458 static int s0ix_stats_show(struct seq_file *s, void *unused)
459 {
460 struct amd_pmc_dev *dev = s->private;
461 u64 entry_time, exit_time, residency;
462
463 /* Use FCH registers to get the S0ix stats */
464 if (!dev->fch_virt_addr) {
465 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
466 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
467 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
468
469 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
470 if (!dev->fch_virt_addr)
471 return -ENOMEM;
472 }
473
474 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
475 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
476
477 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
478 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
479
480 /* It's in 48MHz. We need to convert it */
481 residency = exit_time - entry_time;
482 do_div(residency, 48);
483
484 seq_puts(s, "=== S0ix statistics ===\n");
485 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
486 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
487 seq_printf(s, "Residency Time: %lld\n", residency);
488
489 return 0;
490 }
491 DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
492
amd_pmc_idlemask_show(struct seq_file * s,void * unused)493 static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
494 {
495 struct amd_pmc_dev *dev = s->private;
496 int rc;
497
498 /* we haven't yet read SMU version */
499 if (!dev->major) {
500 rc = amd_pmc_get_smu_version(dev);
501 if (rc)
502 return rc;
503 }
504
505 if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
506 rc = amd_pmc_idlemask_read(dev, NULL, s);
507 if (rc)
508 return rc;
509 } else {
510 seq_puts(s, "Unsupported SMU version for Idlemask\n");
511 }
512
513 return 0;
514 }
515 DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
516
amd_pmc_dbgfs_unregister(struct amd_pmc_dev * dev)517 static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
518 {
519 debugfs_remove_recursive(dev->dbgfs_dir);
520 }
521
amd_pmc_dbgfs_register(struct amd_pmc_dev * dev)522 static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
523 {
524 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
525 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
526 &smu_fw_info_fops);
527 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
528 &s0ix_stats_fops);
529 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
530 &amd_pmc_idlemask_fops);
531 /* Enable STB only when the module_param is set */
532 if (enable_stb) {
533 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
534 dev->cpu_id == AMD_CPU_ID_PS)
535 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
536 &amd_pmc_stb_debugfs_fops_v2);
537 else
538 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
539 &amd_pmc_stb_debugfs_fops);
540 }
541 }
542
amd_pmc_dump_registers(struct amd_pmc_dev * dev)543 static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
544 {
545 u32 value, message, argument, response;
546
547 if (dev->msg_port) {
548 message = AMD_S2D_REGISTER_MESSAGE;
549 argument = AMD_S2D_REGISTER_ARGUMENT;
550 response = AMD_S2D_REGISTER_RESPONSE;
551 } else {
552 message = AMD_PMC_REGISTER_MESSAGE;
553 argument = AMD_PMC_REGISTER_ARGUMENT;
554 response = AMD_PMC_REGISTER_RESPONSE;
555 }
556
557 value = amd_pmc_reg_read(dev, response);
558 dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
559
560 value = amd_pmc_reg_read(dev, argument);
561 dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
562
563 value = amd_pmc_reg_read(dev, message);
564 dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
565 }
566
amd_pmc_send_cmd(struct amd_pmc_dev * dev,u32 arg,u32 * data,u8 msg,bool ret)567 static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
568 {
569 int rc;
570 u32 val, message, argument, response;
571
572 mutex_lock(&dev->lock);
573
574 if (dev->msg_port) {
575 message = AMD_S2D_REGISTER_MESSAGE;
576 argument = AMD_S2D_REGISTER_ARGUMENT;
577 response = AMD_S2D_REGISTER_RESPONSE;
578 } else {
579 message = AMD_PMC_REGISTER_MESSAGE;
580 argument = AMD_PMC_REGISTER_ARGUMENT;
581 response = AMD_PMC_REGISTER_RESPONSE;
582 }
583
584 /* Wait until we get a valid response */
585 rc = readx_poll_timeout(ioread32, dev->regbase + response,
586 val, val != 0, PMC_MSG_DELAY_MIN_US,
587 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
588 if (rc) {
589 dev_err(dev->dev, "failed to talk to SMU\n");
590 goto out_unlock;
591 }
592
593 /* Write zero to response register */
594 amd_pmc_reg_write(dev, response, 0);
595
596 /* Write argument into response register */
597 amd_pmc_reg_write(dev, argument, arg);
598
599 /* Write message ID to message ID register */
600 amd_pmc_reg_write(dev, message, msg);
601
602 /* Wait until we get a valid response */
603 rc = readx_poll_timeout(ioread32, dev->regbase + response,
604 val, val != 0, PMC_MSG_DELAY_MIN_US,
605 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
606 if (rc) {
607 dev_err(dev->dev, "SMU response timed out\n");
608 goto out_unlock;
609 }
610
611 switch (val) {
612 case AMD_PMC_RESULT_OK:
613 if (ret) {
614 /* PMFW may take longer time to return back the data */
615 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
616 *data = amd_pmc_reg_read(dev, argument);
617 }
618 break;
619 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
620 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
621 rc = -EBUSY;
622 goto out_unlock;
623 case AMD_PMC_RESULT_CMD_UNKNOWN:
624 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
625 rc = -EINVAL;
626 goto out_unlock;
627 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
628 case AMD_PMC_RESULT_FAILED:
629 default:
630 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
631 rc = -EIO;
632 goto out_unlock;
633 }
634
635 out_unlock:
636 mutex_unlock(&dev->lock);
637 amd_pmc_dump_registers(dev);
638 return rc;
639 }
640
641 #ifdef CONFIG_SUSPEND
amd_pmc_get_os_hint(struct amd_pmc_dev * dev)642 static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
643 {
644 switch (dev->cpu_id) {
645 case AMD_CPU_ID_PCO:
646 return MSG_OS_HINT_PCO;
647 case AMD_CPU_ID_RN:
648 case AMD_CPU_ID_YC:
649 case AMD_CPU_ID_CB:
650 case AMD_CPU_ID_PS:
651 return MSG_OS_HINT_RN;
652 }
653 return -EINVAL;
654 }
655
amd_pmc_verify_czn_rtc(struct amd_pmc_dev * pdev,u32 * arg)656 static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
657 {
658 struct rtc_device *rtc_device;
659 time64_t then, now, duration;
660 struct rtc_wkalrm alarm;
661 struct rtc_time tm;
662 int rc;
663
664 /* we haven't yet read SMU version */
665 if (!pdev->major) {
666 rc = amd_pmc_get_smu_version(pdev);
667 if (rc)
668 return rc;
669 }
670
671 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
672 return 0;
673
674 rtc_device = rtc_class_open("rtc0");
675 if (!rtc_device)
676 return 0;
677 rc = rtc_read_alarm(rtc_device, &alarm);
678 if (rc)
679 return rc;
680 if (!alarm.enabled) {
681 dev_dbg(pdev->dev, "alarm not enabled\n");
682 return 0;
683 }
684 rc = rtc_read_time(rtc_device, &tm);
685 if (rc)
686 return rc;
687 then = rtc_tm_to_time64(&alarm.time);
688 now = rtc_tm_to_time64(&tm);
689 duration = then-now;
690
691 /* in the past */
692 if (then < now)
693 return 0;
694
695 /* will be stored in upper 16 bits of s0i3 hint argument,
696 * so timer wakeup from s0i3 is limited to ~18 hours or less
697 */
698 if (duration <= 4 || duration > U16_MAX)
699 return -EINVAL;
700
701 *arg |= (duration << 16);
702 rc = rtc_alarm_irq_enable(rtc_device, 0);
703 dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
704
705 return rc;
706 }
707
amd_pmc_s2idle_prepare(void)708 static void amd_pmc_s2idle_prepare(void)
709 {
710 struct amd_pmc_dev *pdev = &pmc;
711 int rc;
712 u8 msg;
713 u32 arg = 1;
714
715 /* Reset and Start SMU logging - to monitor the s0i3 stats */
716 amd_pmc_setup_smu_logging(pdev);
717
718 /* Activate CZN specific RTC functionality */
719 if (pdev->cpu_id == AMD_CPU_ID_CZN) {
720 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
721 if (rc) {
722 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
723 return;
724 }
725 }
726
727 msg = amd_pmc_get_os_hint(pdev);
728 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
729 if (rc) {
730 dev_err(pdev->dev, "suspend failed: %d\n", rc);
731 return;
732 }
733
734 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
735 if (rc)
736 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
737 }
738
amd_pmc_s2idle_check(void)739 static void amd_pmc_s2idle_check(void)
740 {
741 struct amd_pmc_dev *pdev = &pmc;
742 struct smu_metrics table;
743 int rc;
744
745 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
746 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
747 table.s0i3_last_entry_status)
748 usleep_range(10000, 20000);
749
750 /* Dump the IdleMask before we add to the STB */
751 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
752
753 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
754 if (rc)
755 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
756 }
757
amd_pmc_s2idle_restore(void)758 static void amd_pmc_s2idle_restore(void)
759 {
760 struct amd_pmc_dev *pdev = &pmc;
761 int rc;
762 u8 msg;
763
764 msg = amd_pmc_get_os_hint(pdev);
765 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
766 if (rc)
767 dev_err(pdev->dev, "resume failed: %d\n", rc);
768
769 /* Let SMU know that we are looking for stats */
770 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
771
772 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
773 if (rc)
774 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
775
776 /* Notify on failed entry */
777 amd_pmc_validate_deepest(pdev);
778 }
779
780 static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
781 .prepare = amd_pmc_s2idle_prepare,
782 .check = amd_pmc_s2idle_check,
783 .restore = amd_pmc_s2idle_restore,
784 };
785 #endif
786
787 static const struct pci_device_id pmc_pci_ids[] = {
788 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
789 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
791 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
792 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
793 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
794 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
795 { }
796 };
797
amd_pmc_s2d_init(struct amd_pmc_dev * dev)798 static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
799 {
800 u32 phys_addr_low, phys_addr_hi;
801 u64 stb_phys_addr;
802 u32 size = 0;
803
804 /* Spill to DRAM feature uses separate SMU message port */
805 dev->msg_port = 1;
806
807 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
808 if (size != S2D_TELEMETRY_BYTES_MAX)
809 return -EIO;
810
811 /* Get STB DRAM address */
812 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
813 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
814
815 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
816
817 /* Clear msg_port for other SMU operation */
818 dev->msg_port = 0;
819
820 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
821 if (!dev->stb_virt_addr)
822 return -ENOMEM;
823
824 return 0;
825 }
826
827 #ifdef CONFIG_SUSPEND
amd_pmc_write_stb(struct amd_pmc_dev * dev,u32 data)828 static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
829 {
830 int err;
831
832 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
833 if (err) {
834 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
835 AMD_PMC_STB_INDEX_ADDRESS);
836 return pcibios_err_to_errno(err);
837 }
838
839 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
840 if (err) {
841 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
842 AMD_PMC_STB_INDEX_DATA);
843 return pcibios_err_to_errno(err);
844 }
845
846 return 0;
847 }
848 #endif
849
amd_pmc_read_stb(struct amd_pmc_dev * dev,u32 * buf)850 static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
851 {
852 int i, err;
853
854 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
855 if (err) {
856 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
857 AMD_PMC_STB_INDEX_ADDRESS);
858 return pcibios_err_to_errno(err);
859 }
860
861 for (i = 0; i < FIFO_SIZE; i++) {
862 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
863 if (err) {
864 dev_err(dev->dev, "error reading data from stb: 0x%X\n",
865 AMD_PMC_STB_INDEX_DATA);
866 return pcibios_err_to_errno(err);
867 }
868 }
869
870 return 0;
871 }
872
amd_pmc_probe(struct platform_device * pdev)873 static int amd_pmc_probe(struct platform_device *pdev)
874 {
875 struct amd_pmc_dev *dev = &pmc;
876 struct pci_dev *rdev;
877 u32 base_addr_lo, base_addr_hi;
878 u64 base_addr;
879 int err;
880 u32 val;
881
882 dev->dev = &pdev->dev;
883
884 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
885 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
886 err = -ENODEV;
887 goto err_pci_dev_put;
888 }
889
890 dev->cpu_id = rdev->device;
891 dev->rdev = rdev;
892 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
893 if (err) {
894 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
895 err = pcibios_err_to_errno(err);
896 goto err_pci_dev_put;
897 }
898
899 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
900 if (err) {
901 err = pcibios_err_to_errno(err);
902 goto err_pci_dev_put;
903 }
904
905 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
906
907 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
908 if (err) {
909 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
910 err = pcibios_err_to_errno(err);
911 goto err_pci_dev_put;
912 }
913
914 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
915 if (err) {
916 err = pcibios_err_to_errno(err);
917 goto err_pci_dev_put;
918 }
919
920 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
921 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
922
923 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
924 AMD_PMC_MAPPING_SIZE);
925 if (!dev->regbase) {
926 err = -ENOMEM;
927 goto err_pci_dev_put;
928 }
929
930 mutex_init(&dev->lock);
931
932 if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
933 err = amd_pmc_s2d_init(dev);
934 if (err)
935 return err;
936 }
937
938 platform_set_drvdata(pdev, dev);
939 #ifdef CONFIG_SUSPEND
940 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
941 if (err)
942 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
943 #endif
944
945 amd_pmc_dbgfs_register(dev);
946 return 0;
947
948 err_pci_dev_put:
949 pci_dev_put(rdev);
950 return err;
951 }
952
amd_pmc_remove(struct platform_device * pdev)953 static int amd_pmc_remove(struct platform_device *pdev)
954 {
955 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
956
957 #ifdef CONFIG_SUSPEND
958 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
959 #endif
960 amd_pmc_dbgfs_unregister(dev);
961 pci_dev_put(dev->rdev);
962 mutex_destroy(&dev->lock);
963 return 0;
964 }
965
966 static const struct acpi_device_id amd_pmc_acpi_ids[] = {
967 {"AMDI0005", 0},
968 {"AMDI0006", 0},
969 {"AMDI0007", 0},
970 {"AMDI0008", 0},
971 {"AMDI0009", 0},
972 {"AMD0004", 0},
973 {"AMD0005", 0},
974 { }
975 };
976 MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
977
978 static struct platform_driver amd_pmc_driver = {
979 .driver = {
980 .name = "amd_pmc",
981 .acpi_match_table = amd_pmc_acpi_ids,
982 .dev_groups = pmc_groups,
983 },
984 .probe = amd_pmc_probe,
985 .remove = amd_pmc_remove,
986 };
987 module_platform_driver(amd_pmc_driver);
988
989 MODULE_LICENSE("GPL v2");
990 MODULE_DESCRIPTION("AMD PMC Driver");
991
