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Searched refs:_MASKED_BIT_DISABLE (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/i915/gvt/
Dreg.h99 ((_val) & _MASKED_BIT_DISABLE(_b))
Dhandlers.c2107 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)) in ring_reset_ctl_write()
/Linux-v6.1/drivers/gpu/drm/i915/pxp/
Dintel_pxp.c71 _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES)); in kcr_pxp_disable()
/Linux-v6.1/drivers/gpu/drm/i915/gt/
Dintel_ring_submission.c247 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in xcs_resume()
782 *cs++ = _MASKED_BIT_DISABLE( in mi_set_context()
1036 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); in gen6_bsd_submit_request()
Dintel_rc6.c722 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); in vlv_residency_raw()
Dintel_lrc.c789 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); in init_common_regs()
793 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | in init_common_regs()
Dintel_reset.c590 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET)); in gen8_engine_reset_cancel()
Dintel_engine_cs.c1450 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in intel_engine_cancel_stop_cs()
Dintel_workarounds.c213 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
Dintel_execlists_submission.c2935 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in enable_execlists()
/Linux-v6.1/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c759 intel_uncore_write_fw(uncore, DMA_CTRL, _MASKED_BIT_DISABLE(dma_flags)); in uc_fw_xfer()
Dintel_guc_submission.c3954 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING)); in start_engine()
/Linux-v6.1/drivers/gpu/drm/i915/
Dintel_pm.c365 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); in _intel_set_memory_cxsr()
376 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); in _intel_set_memory_cxsr()
4782 _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); in gen3_init_clock_gating()
4800 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); in i85x_init_clock_gating()
Dintel_uncore.c124 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)
Di915_irq.c2957 …intel_uncore_write(&dev_priv->uncore, SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE)… in i915gm_disable_vblank()
Di915_reg.h185 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) macro