1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/module.h>
118 #include <linux/device.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/ethtool.h>
123
124 #include "xgbe.h"
125 #include "xgbe-common.h"
126
127 #define XGBE_PHY_PORT_SPEED_100 BIT(1)
128 #define XGBE_PHY_PORT_SPEED_1000 BIT(2)
129 #define XGBE_PHY_PORT_SPEED_2500 BIT(3)
130 #define XGBE_PHY_PORT_SPEED_10000 BIT(4)
131
132 #define XGBE_MUTEX_RELEASE 0x80000000
133
134 #define XGBE_SFP_DIRECT 7
135
136 /* I2C target addresses */
137 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
138 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
139 #define XGBE_SFP_PHY_ADDRESS 0x56
140 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
141
142 /* SFP sideband signal indicators */
143 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
144 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
145 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
146 #define XGBE_GPIO_NO_RX_LOS BIT(3)
147
148 /* Rate-change complete wait/retry count */
149 #define XGBE_RATECHANGE_COUNT 500
150
151 /* CDR delay values for KR support (in usec) */
152 #define XGBE_CDR_DELAY_INIT 10000
153 #define XGBE_CDR_DELAY_INC 10000
154 #define XGBE_CDR_DELAY_MAX 100000
155
156 /* RRC frequency during link status check */
157 #define XGBE_RRC_FREQUENCY 10
158
159 enum xgbe_port_mode {
160 XGBE_PORT_MODE_RSVD = 0,
161 XGBE_PORT_MODE_BACKPLANE,
162 XGBE_PORT_MODE_BACKPLANE_2500,
163 XGBE_PORT_MODE_1000BASE_T,
164 XGBE_PORT_MODE_1000BASE_X,
165 XGBE_PORT_MODE_NBASE_T,
166 XGBE_PORT_MODE_10GBASE_T,
167 XGBE_PORT_MODE_10GBASE_R,
168 XGBE_PORT_MODE_SFP,
169 XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
170 XGBE_PORT_MODE_MAX,
171 };
172
173 enum xgbe_conn_type {
174 XGBE_CONN_TYPE_NONE = 0,
175 XGBE_CONN_TYPE_SFP,
176 XGBE_CONN_TYPE_MDIO,
177 XGBE_CONN_TYPE_RSVD1,
178 XGBE_CONN_TYPE_BACKPLANE,
179 XGBE_CONN_TYPE_MAX,
180 };
181
182 /* SFP/SFP+ related definitions */
183 enum xgbe_sfp_comm {
184 XGBE_SFP_COMM_DIRECT = 0,
185 XGBE_SFP_COMM_PCA9545,
186 };
187
188 enum xgbe_sfp_cable {
189 XGBE_SFP_CABLE_UNKNOWN = 0,
190 XGBE_SFP_CABLE_ACTIVE,
191 XGBE_SFP_CABLE_PASSIVE,
192 };
193
194 enum xgbe_sfp_base {
195 XGBE_SFP_BASE_UNKNOWN = 0,
196 XGBE_SFP_BASE_1000_T,
197 XGBE_SFP_BASE_1000_SX,
198 XGBE_SFP_BASE_1000_LX,
199 XGBE_SFP_BASE_1000_CX,
200 XGBE_SFP_BASE_10000_SR,
201 XGBE_SFP_BASE_10000_LR,
202 XGBE_SFP_BASE_10000_LRM,
203 XGBE_SFP_BASE_10000_ER,
204 XGBE_SFP_BASE_10000_CR,
205 };
206
207 enum xgbe_sfp_speed {
208 XGBE_SFP_SPEED_UNKNOWN = 0,
209 XGBE_SFP_SPEED_100_1000,
210 XGBE_SFP_SPEED_1000,
211 XGBE_SFP_SPEED_10000,
212 };
213
214 /* SFP Serial ID Base ID values relative to an offset of 0 */
215 #define XGBE_SFP_BASE_ID 0
216 #define XGBE_SFP_ID_SFP 0x03
217
218 #define XGBE_SFP_BASE_EXT_ID 1
219 #define XGBE_SFP_EXT_ID_SFP 0x04
220
221 #define XGBE_SFP_BASE_10GBE_CC 3
222 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
223 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
224 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
225 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
226
227 #define XGBE_SFP_BASE_1GBE_CC 6
228 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
229 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
230 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
231 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
232
233 #define XGBE_SFP_BASE_CABLE 8
234 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
235 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
236
237 #define XGBE_SFP_BASE_BR 12
238 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
239 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
240 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
241 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
242 #define XGBE_MOLEX_SFP_BASE_BR_10GBE_MAX 0x78
243
244 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
245
246 #define XGBE_SFP_BASE_VENDOR_NAME 20
247 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
248 #define XGBE_SFP_BASE_VENDOR_PN 40
249 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
250 #define XGBE_SFP_BASE_VENDOR_REV 56
251 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
252
253 #define XGBE_SFP_BASE_CC 63
254
255 /* SFP Serial ID Extended ID values relative to an offset of 64 */
256 #define XGBE_SFP_BASE_VENDOR_SN 4
257 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
258
259 #define XGBE_SFP_EXTD_OPT1 1
260 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
261 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
262
263 #define XGBE_SFP_EXTD_DIAG 28
264 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
265
266 #define XGBE_SFP_EXTD_SFF_8472 30
267
268 #define XGBE_SFP_EXTD_CC 31
269
270 struct xgbe_sfp_eeprom {
271 u8 base[64];
272 u8 extd[32];
273 u8 vendor[32];
274 };
275
276 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
277 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
278 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
279
280 #define XGBE_SFP_EEPROM_BASE_LEN 256
281 #define XGBE_SFP_EEPROM_DIAG_LEN 256
282 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
283 XGBE_SFP_EEPROM_DIAG_LEN)
284
285 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
286 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
287
288 #define XGBE_MOLEX_VENDOR "Molex Inc. "
289
290 struct xgbe_sfp_ascii {
291 union {
292 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
293 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
294 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
295 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
296 } u;
297 };
298
299 /* MDIO PHY reset types */
300 enum xgbe_mdio_reset {
301 XGBE_MDIO_RESET_NONE = 0,
302 XGBE_MDIO_RESET_I2C_GPIO,
303 XGBE_MDIO_RESET_INT_GPIO,
304 XGBE_MDIO_RESET_MAX,
305 };
306
307 /* Re-driver related definitions */
308 enum xgbe_phy_redrv_if {
309 XGBE_PHY_REDRV_IF_MDIO = 0,
310 XGBE_PHY_REDRV_IF_I2C,
311 XGBE_PHY_REDRV_IF_MAX,
312 };
313
314 enum xgbe_phy_redrv_model {
315 XGBE_PHY_REDRV_MODEL_4223 = 0,
316 XGBE_PHY_REDRV_MODEL_4227,
317 XGBE_PHY_REDRV_MODEL_MAX,
318 };
319
320 enum xgbe_phy_redrv_mode {
321 XGBE_PHY_REDRV_MODE_CX = 5,
322 XGBE_PHY_REDRV_MODE_SR = 9,
323 };
324
325 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
326
327 /* PHY related configuration information */
328 struct xgbe_phy_data {
329 enum xgbe_port_mode port_mode;
330
331 unsigned int port_id;
332
333 unsigned int port_speeds;
334
335 enum xgbe_conn_type conn_type;
336
337 enum xgbe_mode cur_mode;
338 enum xgbe_mode start_mode;
339
340 unsigned int rrc_count;
341
342 unsigned int mdio_addr;
343
344 /* SFP Support */
345 enum xgbe_sfp_comm sfp_comm;
346 unsigned int sfp_mux_address;
347 unsigned int sfp_mux_channel;
348
349 unsigned int sfp_gpio_address;
350 unsigned int sfp_gpio_mask;
351 unsigned int sfp_gpio_inputs;
352 unsigned int sfp_gpio_rx_los;
353 unsigned int sfp_gpio_tx_fault;
354 unsigned int sfp_gpio_mod_absent;
355 unsigned int sfp_gpio_rate_select;
356
357 unsigned int sfp_rx_los;
358 unsigned int sfp_tx_fault;
359 unsigned int sfp_mod_absent;
360 unsigned int sfp_changed;
361 unsigned int sfp_phy_avail;
362 unsigned int sfp_cable_len;
363 enum xgbe_sfp_base sfp_base;
364 enum xgbe_sfp_cable sfp_cable;
365 enum xgbe_sfp_speed sfp_speed;
366 struct xgbe_sfp_eeprom sfp_eeprom;
367
368 /* External PHY support */
369 enum xgbe_mdio_mode phydev_mode;
370 struct mii_bus *mii;
371 struct phy_device *phydev;
372 enum xgbe_mdio_reset mdio_reset;
373 unsigned int mdio_reset_addr;
374 unsigned int mdio_reset_gpio;
375
376 /* Re-driver support */
377 unsigned int redrv;
378 unsigned int redrv_if;
379 unsigned int redrv_addr;
380 unsigned int redrv_lane;
381 unsigned int redrv_model;
382
383 /* KR AN support */
384 unsigned int phy_cdr_notrack;
385 unsigned int phy_cdr_delay;
386 };
387
388 /* I2C, MDIO and GPIO lines are muxed, so only one device at a time */
389 static DEFINE_MUTEX(xgbe_phy_comm_lock);
390
391 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
392
xgbe_phy_i2c_xfer(struct xgbe_prv_data * pdata,struct xgbe_i2c_op * i2c_op)393 static int xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata,
394 struct xgbe_i2c_op *i2c_op)
395 {
396 return pdata->i2c_if.i2c_xfer(pdata, i2c_op);
397 }
398
xgbe_phy_redrv_write(struct xgbe_prv_data * pdata,unsigned int reg,unsigned int val)399 static int xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
400 unsigned int val)
401 {
402 struct xgbe_phy_data *phy_data = pdata->phy_data;
403 struct xgbe_i2c_op i2c_op;
404 __be16 *redrv_val;
405 u8 redrv_data[5], csum;
406 unsigned int i, retry;
407 int ret;
408
409 /* High byte of register contains read/write indicator */
410 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
411 redrv_data[1] = reg & 0xff;
412 redrv_val = (__be16 *)&redrv_data[2];
413 *redrv_val = cpu_to_be16(val);
414
415 /* Calculate 1 byte checksum */
416 csum = 0;
417 for (i = 0; i < 4; i++) {
418 csum += redrv_data[i];
419 if (redrv_data[i] > csum)
420 csum++;
421 }
422 redrv_data[4] = ~csum;
423
424 retry = 1;
425 again1:
426 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
427 i2c_op.target = phy_data->redrv_addr;
428 i2c_op.len = sizeof(redrv_data);
429 i2c_op.buf = redrv_data;
430 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
431 if (ret) {
432 if ((ret == -EAGAIN) && retry--)
433 goto again1;
434
435 return ret;
436 }
437
438 retry = 1;
439 again2:
440 i2c_op.cmd = XGBE_I2C_CMD_READ;
441 i2c_op.target = phy_data->redrv_addr;
442 i2c_op.len = 1;
443 i2c_op.buf = redrv_data;
444 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
445 if (ret) {
446 if ((ret == -EAGAIN) && retry--)
447 goto again2;
448
449 return ret;
450 }
451
452 if (redrv_data[0] != 0xff) {
453 netif_dbg(pdata, drv, pdata->netdev,
454 "Redriver write checksum error\n");
455 ret = -EIO;
456 }
457
458 return ret;
459 }
460
xgbe_phy_i2c_write(struct xgbe_prv_data * pdata,unsigned int target,void * val,unsigned int val_len)461 static int xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target,
462 void *val, unsigned int val_len)
463 {
464 struct xgbe_i2c_op i2c_op;
465 int retry, ret;
466
467 retry = 1;
468 again:
469 /* Write the specfied register */
470 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
471 i2c_op.target = target;
472 i2c_op.len = val_len;
473 i2c_op.buf = val;
474 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
475 if ((ret == -EAGAIN) && retry--)
476 goto again;
477
478 return ret;
479 }
480
xgbe_phy_i2c_read(struct xgbe_prv_data * pdata,unsigned int target,void * reg,unsigned int reg_len,void * val,unsigned int val_len)481 static int xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target,
482 void *reg, unsigned int reg_len,
483 void *val, unsigned int val_len)
484 {
485 struct xgbe_i2c_op i2c_op;
486 int retry, ret;
487
488 retry = 1;
489 again1:
490 /* Set the specified register to read */
491 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
492 i2c_op.target = target;
493 i2c_op.len = reg_len;
494 i2c_op.buf = reg;
495 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
496 if (ret) {
497 if ((ret == -EAGAIN) && retry--)
498 goto again1;
499
500 return ret;
501 }
502
503 retry = 1;
504 again2:
505 /* Read the specfied register */
506 i2c_op.cmd = XGBE_I2C_CMD_READ;
507 i2c_op.target = target;
508 i2c_op.len = val_len;
509 i2c_op.buf = val;
510 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
511 if ((ret == -EAGAIN) && retry--)
512 goto again2;
513
514 return ret;
515 }
516
xgbe_phy_sfp_put_mux(struct xgbe_prv_data * pdata)517 static int xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
518 {
519 struct xgbe_phy_data *phy_data = pdata->phy_data;
520 struct xgbe_i2c_op i2c_op;
521 u8 mux_channel;
522
523 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
524 return 0;
525
526 /* Select no mux channels */
527 mux_channel = 0;
528 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
529 i2c_op.target = phy_data->sfp_mux_address;
530 i2c_op.len = sizeof(mux_channel);
531 i2c_op.buf = &mux_channel;
532
533 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
534 }
535
xgbe_phy_sfp_get_mux(struct xgbe_prv_data * pdata)536 static int xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
537 {
538 struct xgbe_phy_data *phy_data = pdata->phy_data;
539 struct xgbe_i2c_op i2c_op;
540 u8 mux_channel;
541
542 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
543 return 0;
544
545 /* Select desired mux channel */
546 mux_channel = 1 << phy_data->sfp_mux_channel;
547 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
548 i2c_op.target = phy_data->sfp_mux_address;
549 i2c_op.len = sizeof(mux_channel);
550 i2c_op.buf = &mux_channel;
551
552 return xgbe_phy_i2c_xfer(pdata, &i2c_op);
553 }
554
xgbe_phy_put_comm_ownership(struct xgbe_prv_data * pdata)555 static void xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
556 {
557 mutex_unlock(&xgbe_phy_comm_lock);
558 }
559
xgbe_phy_get_comm_ownership(struct xgbe_prv_data * pdata)560 static int xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
561 {
562 struct xgbe_phy_data *phy_data = pdata->phy_data;
563 unsigned long timeout;
564 unsigned int mutex_id;
565
566 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
567 * the driver needs to take the software mutex and then the hardware
568 * mutexes before being able to use the busses.
569 */
570 mutex_lock(&xgbe_phy_comm_lock);
571
572 /* Clear the mutexes */
573 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
574 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
575
576 /* Mutex formats are the same for I2C and MDIO/GPIO */
577 mutex_id = 0;
578 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
579 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
580
581 timeout = jiffies + (5 * HZ);
582 while (time_before(jiffies, timeout)) {
583 /* Must be all zeroes in order to obtain the mutex */
584 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
585 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
586 usleep_range(100, 200);
587 continue;
588 }
589
590 /* Obtain the mutex */
591 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
592 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
593
594 return 0;
595 }
596
597 mutex_unlock(&xgbe_phy_comm_lock);
598
599 netdev_err(pdata->netdev, "unable to obtain hardware mutexes\n");
600
601 return -ETIMEDOUT;
602 }
603
xgbe_phy_mdio_mii_write(struct xgbe_prv_data * pdata,int addr,int reg,u16 val)604 static int xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr,
605 int reg, u16 val)
606 {
607 struct xgbe_phy_data *phy_data = pdata->phy_data;
608
609 if (reg & MII_ADDR_C45) {
610 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
611 return -ENOTSUPP;
612 } else {
613 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
614 return -ENOTSUPP;
615 }
616
617 return pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val);
618 }
619
xgbe_phy_i2c_mii_write(struct xgbe_prv_data * pdata,int reg,u16 val)620 static int xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, u16 val)
621 {
622 __be16 *mii_val;
623 u8 mii_data[3];
624 int ret;
625
626 ret = xgbe_phy_sfp_get_mux(pdata);
627 if (ret)
628 return ret;
629
630 mii_data[0] = reg & 0xff;
631 mii_val = (__be16 *)&mii_data[1];
632 *mii_val = cpu_to_be16(val);
633
634 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
635 mii_data, sizeof(mii_data));
636
637 xgbe_phy_sfp_put_mux(pdata);
638
639 return ret;
640 }
641
xgbe_phy_mii_write(struct mii_bus * mii,int addr,int reg,u16 val)642 static int xgbe_phy_mii_write(struct mii_bus *mii, int addr, int reg, u16 val)
643 {
644 struct xgbe_prv_data *pdata = mii->priv;
645 struct xgbe_phy_data *phy_data = pdata->phy_data;
646 int ret;
647
648 ret = xgbe_phy_get_comm_ownership(pdata);
649 if (ret)
650 return ret;
651
652 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
653 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
654 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
655 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
656 else
657 ret = -ENOTSUPP;
658
659 xgbe_phy_put_comm_ownership(pdata);
660
661 return ret;
662 }
663
xgbe_phy_mdio_mii_read(struct xgbe_prv_data * pdata,int addr,int reg)664 static int xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr,
665 int reg)
666 {
667 struct xgbe_phy_data *phy_data = pdata->phy_data;
668
669 if (reg & MII_ADDR_C45) {
670 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
671 return -ENOTSUPP;
672 } else {
673 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
674 return -ENOTSUPP;
675 }
676
677 return pdata->hw_if.read_ext_mii_regs(pdata, addr, reg);
678 }
679
xgbe_phy_i2c_mii_read(struct xgbe_prv_data * pdata,int reg)680 static int xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
681 {
682 __be16 mii_val;
683 u8 mii_reg;
684 int ret;
685
686 ret = xgbe_phy_sfp_get_mux(pdata);
687 if (ret)
688 return ret;
689
690 mii_reg = reg;
691 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
692 &mii_reg, sizeof(mii_reg),
693 &mii_val, sizeof(mii_val));
694 if (!ret)
695 ret = be16_to_cpu(mii_val);
696
697 xgbe_phy_sfp_put_mux(pdata);
698
699 return ret;
700 }
701
xgbe_phy_mii_read(struct mii_bus * mii,int addr,int reg)702 static int xgbe_phy_mii_read(struct mii_bus *mii, int addr, int reg)
703 {
704 struct xgbe_prv_data *pdata = mii->priv;
705 struct xgbe_phy_data *phy_data = pdata->phy_data;
706 int ret;
707
708 ret = xgbe_phy_get_comm_ownership(pdata);
709 if (ret)
710 return ret;
711
712 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
713 ret = xgbe_phy_i2c_mii_read(pdata, reg);
714 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
715 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
716 else
717 ret = -ENOTSUPP;
718
719 xgbe_phy_put_comm_ownership(pdata);
720
721 return ret;
722 }
723
xgbe_phy_sfp_phy_settings(struct xgbe_prv_data * pdata)724 static void xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
725 {
726 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
727 struct xgbe_phy_data *phy_data = pdata->phy_data;
728
729 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
730 return;
731
732 XGBE_ZERO_SUP(lks);
733
734 if (phy_data->sfp_mod_absent) {
735 pdata->phy.speed = SPEED_UNKNOWN;
736 pdata->phy.duplex = DUPLEX_UNKNOWN;
737 pdata->phy.autoneg = AUTONEG_ENABLE;
738 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
739
740 XGBE_SET_SUP(lks, Autoneg);
741 XGBE_SET_SUP(lks, Pause);
742 XGBE_SET_SUP(lks, Asym_Pause);
743 XGBE_SET_SUP(lks, TP);
744 XGBE_SET_SUP(lks, FIBRE);
745
746 XGBE_LM_COPY(lks, advertising, lks, supported);
747
748 return;
749 }
750
751 switch (phy_data->sfp_base) {
752 case XGBE_SFP_BASE_1000_T:
753 case XGBE_SFP_BASE_1000_SX:
754 case XGBE_SFP_BASE_1000_LX:
755 case XGBE_SFP_BASE_1000_CX:
756 pdata->phy.speed = SPEED_UNKNOWN;
757 pdata->phy.duplex = DUPLEX_UNKNOWN;
758 pdata->phy.autoneg = AUTONEG_ENABLE;
759 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
760 XGBE_SET_SUP(lks, Autoneg);
761 XGBE_SET_SUP(lks, Pause);
762 XGBE_SET_SUP(lks, Asym_Pause);
763 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
764 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
765 XGBE_SET_SUP(lks, 100baseT_Full);
766 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
767 XGBE_SET_SUP(lks, 1000baseT_Full);
768 } else {
769 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
770 XGBE_SET_SUP(lks, 1000baseX_Full);
771 }
772 break;
773 case XGBE_SFP_BASE_10000_SR:
774 case XGBE_SFP_BASE_10000_LR:
775 case XGBE_SFP_BASE_10000_LRM:
776 case XGBE_SFP_BASE_10000_ER:
777 case XGBE_SFP_BASE_10000_CR:
778 pdata->phy.speed = SPEED_10000;
779 pdata->phy.duplex = DUPLEX_FULL;
780 pdata->phy.autoneg = AUTONEG_DISABLE;
781 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
782 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
783 switch (phy_data->sfp_base) {
784 case XGBE_SFP_BASE_10000_SR:
785 XGBE_SET_SUP(lks, 10000baseSR_Full);
786 break;
787 case XGBE_SFP_BASE_10000_LR:
788 XGBE_SET_SUP(lks, 10000baseLR_Full);
789 break;
790 case XGBE_SFP_BASE_10000_LRM:
791 XGBE_SET_SUP(lks, 10000baseLRM_Full);
792 break;
793 case XGBE_SFP_BASE_10000_ER:
794 XGBE_SET_SUP(lks, 10000baseER_Full);
795 break;
796 case XGBE_SFP_BASE_10000_CR:
797 XGBE_SET_SUP(lks, 10000baseCR_Full);
798 break;
799 default:
800 break;
801 }
802 }
803 break;
804 default:
805 pdata->phy.speed = SPEED_UNKNOWN;
806 pdata->phy.duplex = DUPLEX_UNKNOWN;
807 pdata->phy.autoneg = AUTONEG_DISABLE;
808 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
809 break;
810 }
811
812 switch (phy_data->sfp_base) {
813 case XGBE_SFP_BASE_1000_T:
814 case XGBE_SFP_BASE_1000_CX:
815 case XGBE_SFP_BASE_10000_CR:
816 XGBE_SET_SUP(lks, TP);
817 break;
818 default:
819 XGBE_SET_SUP(lks, FIBRE);
820 break;
821 }
822
823 XGBE_LM_COPY(lks, advertising, lks, supported);
824 }
825
xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom * sfp_eeprom,enum xgbe_sfp_speed sfp_speed)826 static bool xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
827 enum xgbe_sfp_speed sfp_speed)
828 {
829 u8 *sfp_base, min, max;
830
831 sfp_base = sfp_eeprom->base;
832
833 switch (sfp_speed) {
834 case XGBE_SFP_SPEED_1000:
835 min = XGBE_SFP_BASE_BR_1GBE_MIN;
836 max = XGBE_SFP_BASE_BR_1GBE_MAX;
837 break;
838 case XGBE_SFP_SPEED_10000:
839 min = XGBE_SFP_BASE_BR_10GBE_MIN;
840 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
841 XGBE_MOLEX_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN) == 0)
842 max = XGBE_MOLEX_SFP_BASE_BR_10GBE_MAX;
843 else
844 max = XGBE_SFP_BASE_BR_10GBE_MAX;
845 break;
846 default:
847 return false;
848 }
849
850 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
851 (sfp_base[XGBE_SFP_BASE_BR] <= max));
852 }
853
xgbe_phy_free_phy_device(struct xgbe_prv_data * pdata)854 static void xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
855 {
856 struct xgbe_phy_data *phy_data = pdata->phy_data;
857
858 if (phy_data->phydev) {
859 phy_detach(phy_data->phydev);
860 phy_device_remove(phy_data->phydev);
861 phy_device_free(phy_data->phydev);
862 phy_data->phydev = NULL;
863 }
864 }
865
xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data * pdata)866 static bool xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
867 {
868 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
869 struct xgbe_phy_data *phy_data = pdata->phy_data;
870 unsigned int phy_id = phy_data->phydev->phy_id;
871
872 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
873 return false;
874
875 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
876 return false;
877
878 /* Enable Base-T AN */
879 phy_write(phy_data->phydev, 0x16, 0x0001);
880 phy_write(phy_data->phydev, 0x00, 0x9140);
881 phy_write(phy_data->phydev, 0x16, 0x0000);
882
883 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
884 phy_write(phy_data->phydev, 0x1b, 0x9084);
885 phy_write(phy_data->phydev, 0x09, 0x0e00);
886 phy_write(phy_data->phydev, 0x00, 0x8140);
887 phy_write(phy_data->phydev, 0x04, 0x0d01);
888 phy_write(phy_data->phydev, 0x00, 0x9140);
889
890 linkmode_set_bit_array(phy_10_100_features_array,
891 ARRAY_SIZE(phy_10_100_features_array),
892 supported);
893 linkmode_set_bit_array(phy_gbit_features_array,
894 ARRAY_SIZE(phy_gbit_features_array),
895 supported);
896
897 linkmode_copy(phy_data->phydev->supported, supported);
898
899 phy_support_asym_pause(phy_data->phydev);
900
901 netif_dbg(pdata, drv, pdata->netdev,
902 "Finisar PHY quirk in place\n");
903
904 return true;
905 }
906
xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data * pdata)907 static bool xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
908 {
909 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
910 struct xgbe_phy_data *phy_data = pdata->phy_data;
911 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
912 unsigned int phy_id = phy_data->phydev->phy_id;
913 int reg;
914
915 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
916 return false;
917
918 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
919 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
920 return false;
921
922 /* For Bel-Fuse, use the extra AN flag */
923 pdata->an_again = 1;
924
925 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
926 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
927 return false;
928
929 if ((phy_id & 0xfffffff0) != 0x03625d10)
930 return false;
931
932 /* Reset PHY - wait for self-clearing reset bit to clear */
933 genphy_soft_reset(phy_data->phydev);
934
935 /* Disable RGMII mode */
936 phy_write(phy_data->phydev, 0x18, 0x7007);
937 reg = phy_read(phy_data->phydev, 0x18);
938 phy_write(phy_data->phydev, 0x18, reg & ~0x0080);
939
940 /* Enable fiber register bank */
941 phy_write(phy_data->phydev, 0x1c, 0x7c00);
942 reg = phy_read(phy_data->phydev, 0x1c);
943 reg &= 0x03ff;
944 reg &= ~0x0001;
945 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);
946
947 /* Power down SerDes */
948 reg = phy_read(phy_data->phydev, 0x00);
949 phy_write(phy_data->phydev, 0x00, reg | 0x00800);
950
951 /* Configure SGMII-to-Copper mode */
952 phy_write(phy_data->phydev, 0x1c, 0x7c00);
953 reg = phy_read(phy_data->phydev, 0x1c);
954 reg &= 0x03ff;
955 reg &= ~0x0006;
956 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);
957
958 /* Power up SerDes */
959 reg = phy_read(phy_data->phydev, 0x00);
960 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
961
962 /* Enable copper register bank */
963 phy_write(phy_data->phydev, 0x1c, 0x7c00);
964 reg = phy_read(phy_data->phydev, 0x1c);
965 reg &= 0x03ff;
966 reg &= ~0x0001;
967 phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);
968
969 /* Power up SerDes */
970 reg = phy_read(phy_data->phydev, 0x00);
971 phy_write(phy_data->phydev, 0x00, reg & ~0x00800);
972
973 linkmode_set_bit_array(phy_10_100_features_array,
974 ARRAY_SIZE(phy_10_100_features_array),
975 supported);
976 linkmode_set_bit_array(phy_gbit_features_array,
977 ARRAY_SIZE(phy_gbit_features_array),
978 supported);
979 linkmode_copy(phy_data->phydev->supported, supported);
980 phy_support_asym_pause(phy_data->phydev);
981
982 netif_dbg(pdata, drv, pdata->netdev,
983 "BelFuse PHY quirk in place\n");
984
985 return true;
986 }
987
xgbe_phy_external_phy_quirks(struct xgbe_prv_data * pdata)988 static void xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
989 {
990 if (xgbe_phy_belfuse_phy_quirks(pdata))
991 return;
992
993 if (xgbe_phy_finisar_phy_quirks(pdata))
994 return;
995 }
996
xgbe_phy_find_phy_device(struct xgbe_prv_data * pdata)997 static int xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
998 {
999 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1000 struct xgbe_phy_data *phy_data = pdata->phy_data;
1001 struct phy_device *phydev;
1002 int ret;
1003
1004 /* If we already have a PHY, just return */
1005 if (phy_data->phydev)
1006 return 0;
1007
1008 /* Clear the extra AN flag */
1009 pdata->an_again = 0;
1010
1011 /* Check for the use of an external PHY */
1012 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE)
1013 return 0;
1014
1015 /* For SFP, only use an external PHY if available */
1016 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1017 !phy_data->sfp_phy_avail)
1018 return 0;
1019
1020 /* Set the proper MDIO mode for the PHY */
1021 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1022 phy_data->phydev_mode);
1023 if (ret) {
1024 netdev_err(pdata->netdev,
1025 "mdio port/clause not compatible (%u/%u)\n",
1026 phy_data->mdio_addr, phy_data->phydev_mode);
1027 return ret;
1028 }
1029
1030 /* Create and connect to the PHY device */
1031 phydev = get_phy_device(phy_data->mii, phy_data->mdio_addr,
1032 (phy_data->phydev_mode == XGBE_MDIO_MODE_CL45));
1033 if (IS_ERR(phydev)) {
1034 netdev_err(pdata->netdev, "get_phy_device failed\n");
1035 return -ENODEV;
1036 }
1037 netif_dbg(pdata, drv, pdata->netdev, "external PHY id is %#010x\n",
1038 phydev->phy_id);
1039
1040 /*TODO: If c45, add request_module based on one of the MMD ids? */
1041
1042 ret = phy_device_register(phydev);
1043 if (ret) {
1044 netdev_err(pdata->netdev, "phy_device_register failed\n");
1045 phy_device_free(phydev);
1046 return ret;
1047 }
1048
1049 ret = phy_attach_direct(pdata->netdev, phydev, phydev->dev_flags,
1050 PHY_INTERFACE_MODE_SGMII);
1051 if (ret) {
1052 netdev_err(pdata->netdev, "phy_attach_direct failed\n");
1053 phy_device_remove(phydev);
1054 phy_device_free(phydev);
1055 return ret;
1056 }
1057 phy_data->phydev = phydev;
1058
1059 xgbe_phy_external_phy_quirks(pdata);
1060
1061 linkmode_and(phydev->advertising, phydev->advertising,
1062 lks->link_modes.advertising);
1063
1064 phy_start_aneg(phy_data->phydev);
1065
1066 return 0;
1067 }
1068
xgbe_phy_sfp_external_phy(struct xgbe_prv_data * pdata)1069 static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1070 {
1071 struct xgbe_phy_data *phy_data = pdata->phy_data;
1072 int ret;
1073
1074 if (!phy_data->sfp_changed)
1075 return;
1076
1077 phy_data->sfp_phy_avail = 0;
1078
1079 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1080 return;
1081
1082 /* Check access to the PHY by reading CTRL1 */
1083 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1084 if (ret < 0)
1085 return;
1086
1087 /* Successfully accessed the PHY */
1088 phy_data->sfp_phy_avail = 1;
1089 }
1090
xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data * phy_data)1091 static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1092 {
1093 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1094
1095 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1096 return false;
1097
1098 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1099 return false;
1100
1101 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1102 return true;
1103
1104 return false;
1105 }
1106
xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data * phy_data)1107 static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1108 {
1109 u8 *sfp_extd = phy_data->sfp_eeprom.extd;
1110
1111 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1112 return false;
1113
1114 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1115 return false;
1116
1117 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1118 return true;
1119
1120 return false;
1121 }
1122
xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data * phy_data)1123 static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1124 {
1125 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1126 return false;
1127
1128 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1129 return true;
1130
1131 return false;
1132 }
1133
xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data * pdata)1134 static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1135 {
1136 struct xgbe_phy_data *phy_data = pdata->phy_data;
1137 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1138 u8 *sfp_base;
1139
1140 sfp_base = sfp_eeprom->base;
1141
1142 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP)
1143 return;
1144
1145 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP)
1146 return;
1147
1148 /* Update transceiver signals (eeprom extd/options) */
1149 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1150 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1151
1152 /* Assume ACTIVE cable unless told it is PASSIVE */
1153 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1154 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1155 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1156 } else {
1157 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1158 }
1159
1160 /* Determine the type of SFP */
1161 if (phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE &&
1162 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1163 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1164 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1165 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1166 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1167 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1168 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1169 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1170 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1171 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1172 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1173 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1174 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1175 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1176 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1177 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1178 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1179 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1180
1181 switch (phy_data->sfp_base) {
1182 case XGBE_SFP_BASE_1000_T:
1183 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1184 break;
1185 case XGBE_SFP_BASE_1000_SX:
1186 case XGBE_SFP_BASE_1000_LX:
1187 case XGBE_SFP_BASE_1000_CX:
1188 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1189 break;
1190 case XGBE_SFP_BASE_10000_SR:
1191 case XGBE_SFP_BASE_10000_LR:
1192 case XGBE_SFP_BASE_10000_LRM:
1193 case XGBE_SFP_BASE_10000_ER:
1194 case XGBE_SFP_BASE_10000_CR:
1195 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1196 break;
1197 default:
1198 break;
1199 }
1200 }
1201
xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data * pdata,struct xgbe_sfp_eeprom * sfp_eeprom)1202 static void xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1203 struct xgbe_sfp_eeprom *sfp_eeprom)
1204 {
1205 struct xgbe_sfp_ascii sfp_ascii;
1206 char *sfp_data = (char *)&sfp_ascii;
1207
1208 netif_dbg(pdata, drv, pdata->netdev, "SFP detected:\n");
1209 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1210 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1211 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1212 netif_dbg(pdata, drv, pdata->netdev, " vendor: %s\n",
1213 sfp_data);
1214
1215 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1216 XGBE_SFP_BASE_VENDOR_PN_LEN);
1217 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1218 netif_dbg(pdata, drv, pdata->netdev, " part number: %s\n",
1219 sfp_data);
1220
1221 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1222 XGBE_SFP_BASE_VENDOR_REV_LEN);
1223 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1224 netif_dbg(pdata, drv, pdata->netdev, " revision level: %s\n",
1225 sfp_data);
1226
1227 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1228 XGBE_SFP_BASE_VENDOR_SN_LEN);
1229 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1230 netif_dbg(pdata, drv, pdata->netdev, " serial number: %s\n",
1231 sfp_data);
1232 }
1233
xgbe_phy_sfp_verify_eeprom(u8 cc_in,u8 * buf,unsigned int len)1234 static bool xgbe_phy_sfp_verify_eeprom(u8 cc_in, u8 *buf, unsigned int len)
1235 {
1236 u8 cc;
1237
1238 for (cc = 0; len; buf++, len--)
1239 cc += *buf;
1240
1241 return cc == cc_in;
1242 }
1243
xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data * pdata)1244 static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1245 {
1246 struct xgbe_phy_data *phy_data = pdata->phy_data;
1247 struct xgbe_sfp_eeprom sfp_eeprom;
1248 u8 eeprom_addr;
1249 int ret;
1250
1251 ret = xgbe_phy_sfp_get_mux(pdata);
1252 if (ret) {
1253 dev_err_once(pdata->dev, "%s: I2C error setting SFP MUX\n",
1254 netdev_name(pdata->netdev));
1255 return ret;
1256 }
1257
1258 /* Read the SFP serial ID eeprom */
1259 eeprom_addr = 0;
1260 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1261 &eeprom_addr, sizeof(eeprom_addr),
1262 &sfp_eeprom, sizeof(sfp_eeprom));
1263 if (ret) {
1264 dev_err_once(pdata->dev, "%s: I2C error reading SFP EEPROM\n",
1265 netdev_name(pdata->netdev));
1266 goto put;
1267 }
1268
1269 /* Validate the contents read */
1270 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1271 sfp_eeprom.base,
1272 sizeof(sfp_eeprom.base) - 1)) {
1273 ret = -EINVAL;
1274 goto put;
1275 }
1276
1277 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1278 sfp_eeprom.extd,
1279 sizeof(sfp_eeprom.extd) - 1)) {
1280 ret = -EINVAL;
1281 goto put;
1282 }
1283
1284 /* Check for an added or changed SFP */
1285 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1286 phy_data->sfp_changed = 1;
1287
1288 if (netif_msg_drv(pdata))
1289 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1290
1291 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1292
1293 xgbe_phy_free_phy_device(pdata);
1294 } else {
1295 phy_data->sfp_changed = 0;
1296 }
1297
1298 put:
1299 xgbe_phy_sfp_put_mux(pdata);
1300
1301 return ret;
1302 }
1303
xgbe_phy_sfp_signals(struct xgbe_prv_data * pdata)1304 static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1305 {
1306 struct xgbe_phy_data *phy_data = pdata->phy_data;
1307 u8 gpio_reg, gpio_ports[2];
1308 int ret;
1309
1310 /* Read the input port registers */
1311 gpio_reg = 0;
1312 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address,
1313 &gpio_reg, sizeof(gpio_reg),
1314 gpio_ports, sizeof(gpio_ports));
1315 if (ret) {
1316 dev_err_once(pdata->dev, "%s: I2C error reading SFP GPIOs\n",
1317 netdev_name(pdata->netdev));
1318 return;
1319 }
1320
1321 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1322
1323 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1324 }
1325
xgbe_phy_sfp_mod_absent(struct xgbe_prv_data * pdata)1326 static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1327 {
1328 struct xgbe_phy_data *phy_data = pdata->phy_data;
1329
1330 xgbe_phy_free_phy_device(pdata);
1331
1332 phy_data->sfp_mod_absent = 1;
1333 phy_data->sfp_phy_avail = 0;
1334 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1335 }
1336
xgbe_phy_sfp_reset(struct xgbe_phy_data * phy_data)1337 static void xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1338 {
1339 phy_data->sfp_rx_los = 0;
1340 phy_data->sfp_tx_fault = 0;
1341 phy_data->sfp_mod_absent = 1;
1342 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1343 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1344 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1345 }
1346
xgbe_phy_sfp_detect(struct xgbe_prv_data * pdata)1347 static void xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1348 {
1349 struct xgbe_phy_data *phy_data = pdata->phy_data;
1350 int ret;
1351
1352 /* Reset the SFP signals and info */
1353 xgbe_phy_sfp_reset(phy_data);
1354
1355 ret = xgbe_phy_get_comm_ownership(pdata);
1356 if (ret)
1357 return;
1358
1359 /* Read the SFP signals and check for module presence */
1360 xgbe_phy_sfp_signals(pdata);
1361 if (phy_data->sfp_mod_absent) {
1362 xgbe_phy_sfp_mod_absent(pdata);
1363 goto put;
1364 }
1365
1366 ret = xgbe_phy_sfp_read_eeprom(pdata);
1367 if (ret) {
1368 /* Treat any error as if there isn't an SFP plugged in */
1369 xgbe_phy_sfp_reset(phy_data);
1370 xgbe_phy_sfp_mod_absent(pdata);
1371 goto put;
1372 }
1373
1374 xgbe_phy_sfp_parse_eeprom(pdata);
1375
1376 xgbe_phy_sfp_external_phy(pdata);
1377
1378 put:
1379 xgbe_phy_sfp_phy_settings(pdata);
1380
1381 xgbe_phy_put_comm_ownership(pdata);
1382 }
1383
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)1384 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
1385 struct ethtool_eeprom *eeprom, u8 *data)
1386 {
1387 struct xgbe_phy_data *phy_data = pdata->phy_data;
1388 u8 eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1389 struct xgbe_sfp_eeprom *sfp_eeprom;
1390 unsigned int i, j, rem;
1391 int ret;
1392
1393 rem = eeprom->len;
1394
1395 if (!eeprom->len) {
1396 ret = -EINVAL;
1397 goto done;
1398 }
1399
1400 if ((eeprom->offset + eeprom->len) > XGBE_SFP_EEPROM_MAX) {
1401 ret = -EINVAL;
1402 goto done;
1403 }
1404
1405 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1406 ret = -ENXIO;
1407 goto done;
1408 }
1409
1410 if (!netif_running(pdata->netdev)) {
1411 ret = -EIO;
1412 goto done;
1413 }
1414
1415 if (phy_data->sfp_mod_absent) {
1416 ret = -EIO;
1417 goto done;
1418 }
1419
1420 ret = xgbe_phy_get_comm_ownership(pdata);
1421 if (ret) {
1422 ret = -EIO;
1423 goto done;
1424 }
1425
1426 ret = xgbe_phy_sfp_get_mux(pdata);
1427 if (ret) {
1428 netdev_err(pdata->netdev, "I2C error setting SFP MUX\n");
1429 ret = -EIO;
1430 goto put_own;
1431 }
1432
1433 /* Read the SFP serial ID eeprom */
1434 eeprom_addr = 0;
1435 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1436 &eeprom_addr, sizeof(eeprom_addr),
1437 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1438 if (ret) {
1439 netdev_err(pdata->netdev,
1440 "I2C error reading SFP EEPROM\n");
1441 ret = -EIO;
1442 goto put_mux;
1443 }
1444
1445 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1446
1447 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1448 /* Read the SFP diagnostic eeprom */
1449 eeprom_addr = 0;
1450 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1451 &eeprom_addr, sizeof(eeprom_addr),
1452 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1453 XGBE_SFP_EEPROM_DIAG_LEN);
1454 if (ret) {
1455 netdev_err(pdata->netdev,
1456 "I2C error reading SFP DIAGS\n");
1457 ret = -EIO;
1458 goto put_mux;
1459 }
1460 }
1461
1462 for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {
1463 if ((j >= XGBE_SFP_EEPROM_BASE_LEN) &&
1464 !XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom))
1465 break;
1466
1467 data[i] = eeprom_data[j];
1468 rem--;
1469 }
1470
1471 put_mux:
1472 xgbe_phy_sfp_put_mux(pdata);
1473
1474 put_own:
1475 xgbe_phy_put_comm_ownership(pdata);
1476
1477 done:
1478 eeprom->len -= rem;
1479
1480 return ret;
1481 }
1482
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)1483 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
1484 struct ethtool_modinfo *modinfo)
1485 {
1486 struct xgbe_phy_data *phy_data = pdata->phy_data;
1487
1488 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1489 return -ENXIO;
1490
1491 if (!netif_running(pdata->netdev))
1492 return -EIO;
1493
1494 if (phy_data->sfp_mod_absent)
1495 return -EIO;
1496
1497 if (XGBE_SFP_DIAGS_SUPPORTED(&phy_data->sfp_eeprom)) {
1498 modinfo->type = ETH_MODULE_SFF_8472;
1499 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1500 } else {
1501 modinfo->type = ETH_MODULE_SFF_8079;
1502 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1503 }
1504
1505 return 0;
1506 }
1507
xgbe_phy_phydev_flowctrl(struct xgbe_prv_data * pdata)1508 static void xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1509 {
1510 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1511 struct xgbe_phy_data *phy_data = pdata->phy_data;
1512 u16 lcl_adv = 0, rmt_adv = 0;
1513 u8 fc;
1514
1515 pdata->phy.tx_pause = 0;
1516 pdata->phy.rx_pause = 0;
1517
1518 if (!phy_data->phydev)
1519 return;
1520
1521 lcl_adv = linkmode_adv_to_lcl_adv_t(phy_data->phydev->advertising);
1522
1523 if (phy_data->phydev->pause) {
1524 XGBE_SET_LP_ADV(lks, Pause);
1525 rmt_adv |= LPA_PAUSE_CAP;
1526 }
1527 if (phy_data->phydev->asym_pause) {
1528 XGBE_SET_LP_ADV(lks, Asym_Pause);
1529 rmt_adv |= LPA_PAUSE_ASYM;
1530 }
1531
1532 fc = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1533 if (fc & FLOW_CTRL_TX)
1534 pdata->phy.tx_pause = 1;
1535 if (fc & FLOW_CTRL_RX)
1536 pdata->phy.rx_pause = 1;
1537 }
1538
xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data * pdata)1539 static enum xgbe_mode xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1540 {
1541 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1542 enum xgbe_mode mode;
1543
1544 XGBE_SET_LP_ADV(lks, Autoneg);
1545 XGBE_SET_LP_ADV(lks, TP);
1546
1547 /* Use external PHY to determine flow control */
1548 if (pdata->phy.pause_autoneg)
1549 xgbe_phy_phydev_flowctrl(pdata);
1550
1551 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1552 case XGBE_SGMII_AN_LINK_SPEED_100:
1553 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1554 XGBE_SET_LP_ADV(lks, 100baseT_Full);
1555 mode = XGBE_MODE_SGMII_100;
1556 } else {
1557 /* Half-duplex not supported */
1558 XGBE_SET_LP_ADV(lks, 100baseT_Half);
1559 mode = XGBE_MODE_UNKNOWN;
1560 }
1561 break;
1562 case XGBE_SGMII_AN_LINK_SPEED_1000:
1563 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1564 XGBE_SET_LP_ADV(lks, 1000baseT_Full);
1565 mode = XGBE_MODE_SGMII_1000;
1566 } else {
1567 /* Half-duplex not supported */
1568 XGBE_SET_LP_ADV(lks, 1000baseT_Half);
1569 mode = XGBE_MODE_UNKNOWN;
1570 }
1571 break;
1572 default:
1573 mode = XGBE_MODE_UNKNOWN;
1574 }
1575
1576 return mode;
1577 }
1578
xgbe_phy_an37_outcome(struct xgbe_prv_data * pdata)1579 static enum xgbe_mode xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1580 {
1581 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1582 enum xgbe_mode mode;
1583 unsigned int ad_reg, lp_reg;
1584
1585 XGBE_SET_LP_ADV(lks, Autoneg);
1586 XGBE_SET_LP_ADV(lks, FIBRE);
1587
1588 /* Compare Advertisement and Link Partner register */
1589 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1590 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1591 if (lp_reg & 0x100)
1592 XGBE_SET_LP_ADV(lks, Pause);
1593 if (lp_reg & 0x80)
1594 XGBE_SET_LP_ADV(lks, Asym_Pause);
1595
1596 if (pdata->phy.pause_autoneg) {
1597 /* Set flow control based on auto-negotiation result */
1598 pdata->phy.tx_pause = 0;
1599 pdata->phy.rx_pause = 0;
1600
1601 if (ad_reg & lp_reg & 0x100) {
1602 pdata->phy.tx_pause = 1;
1603 pdata->phy.rx_pause = 1;
1604 } else if (ad_reg & lp_reg & 0x80) {
1605 if (ad_reg & 0x100)
1606 pdata->phy.rx_pause = 1;
1607 else if (lp_reg & 0x100)
1608 pdata->phy.tx_pause = 1;
1609 }
1610 }
1611
1612 if (lp_reg & 0x20)
1613 XGBE_SET_LP_ADV(lks, 1000baseX_Full);
1614
1615 /* Half duplex is not supported */
1616 ad_reg &= lp_reg;
1617 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1618
1619 return mode;
1620 }
1621
xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data * pdata)1622 static enum xgbe_mode xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1623 {
1624 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1625 struct xgbe_phy_data *phy_data = pdata->phy_data;
1626 enum xgbe_mode mode;
1627 unsigned int ad_reg, lp_reg;
1628
1629 XGBE_SET_LP_ADV(lks, Autoneg);
1630 XGBE_SET_LP_ADV(lks, Backplane);
1631
1632 /* Use external PHY to determine flow control */
1633 if (pdata->phy.pause_autoneg)
1634 xgbe_phy_phydev_flowctrl(pdata);
1635
1636 /* Compare Advertisement and Link Partner register 2 */
1637 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1638 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1639 if (lp_reg & 0x80)
1640 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1641 if (lp_reg & 0x20)
1642 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1643
1644 ad_reg &= lp_reg;
1645 if (ad_reg & 0x80) {
1646 switch (phy_data->port_mode) {
1647 case XGBE_PORT_MODE_BACKPLANE:
1648 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1649 mode = XGBE_MODE_KR;
1650 break;
1651 default:
1652 mode = XGBE_MODE_SFI;
1653 break;
1654 }
1655 } else if (ad_reg & 0x20) {
1656 switch (phy_data->port_mode) {
1657 case XGBE_PORT_MODE_BACKPLANE:
1658 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1659 mode = XGBE_MODE_KX_1000;
1660 break;
1661 case XGBE_PORT_MODE_1000BASE_X:
1662 mode = XGBE_MODE_X;
1663 break;
1664 case XGBE_PORT_MODE_SFP:
1665 switch (phy_data->sfp_base) {
1666 case XGBE_SFP_BASE_1000_T:
1667 if (phy_data->phydev &&
1668 (phy_data->phydev->speed == SPEED_100))
1669 mode = XGBE_MODE_SGMII_100;
1670 else
1671 mode = XGBE_MODE_SGMII_1000;
1672 break;
1673 case XGBE_SFP_BASE_1000_SX:
1674 case XGBE_SFP_BASE_1000_LX:
1675 case XGBE_SFP_BASE_1000_CX:
1676 default:
1677 mode = XGBE_MODE_X;
1678 break;
1679 }
1680 break;
1681 default:
1682 if (phy_data->phydev &&
1683 (phy_data->phydev->speed == SPEED_100))
1684 mode = XGBE_MODE_SGMII_100;
1685 else
1686 mode = XGBE_MODE_SGMII_1000;
1687 break;
1688 }
1689 } else {
1690 mode = XGBE_MODE_UNKNOWN;
1691 }
1692
1693 /* Compare Advertisement and Link Partner register 3 */
1694 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1695 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1696 if (lp_reg & 0xc000)
1697 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1698
1699 return mode;
1700 }
1701
xgbe_phy_an73_outcome(struct xgbe_prv_data * pdata)1702 static enum xgbe_mode xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1703 {
1704 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1705 enum xgbe_mode mode;
1706 unsigned int ad_reg, lp_reg;
1707
1708 XGBE_SET_LP_ADV(lks, Autoneg);
1709 XGBE_SET_LP_ADV(lks, Backplane);
1710
1711 /* Compare Advertisement and Link Partner register 1 */
1712 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1713 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1714 if (lp_reg & 0x400)
1715 XGBE_SET_LP_ADV(lks, Pause);
1716 if (lp_reg & 0x800)
1717 XGBE_SET_LP_ADV(lks, Asym_Pause);
1718
1719 if (pdata->phy.pause_autoneg) {
1720 /* Set flow control based on auto-negotiation result */
1721 pdata->phy.tx_pause = 0;
1722 pdata->phy.rx_pause = 0;
1723
1724 if (ad_reg & lp_reg & 0x400) {
1725 pdata->phy.tx_pause = 1;
1726 pdata->phy.rx_pause = 1;
1727 } else if (ad_reg & lp_reg & 0x800) {
1728 if (ad_reg & 0x400)
1729 pdata->phy.rx_pause = 1;
1730 else if (lp_reg & 0x400)
1731 pdata->phy.tx_pause = 1;
1732 }
1733 }
1734
1735 /* Compare Advertisement and Link Partner register 2 */
1736 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1737 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1738 if (lp_reg & 0x80)
1739 XGBE_SET_LP_ADV(lks, 10000baseKR_Full);
1740 if (lp_reg & 0x20)
1741 XGBE_SET_LP_ADV(lks, 1000baseKX_Full);
1742
1743 ad_reg &= lp_reg;
1744 if (ad_reg & 0x80)
1745 mode = XGBE_MODE_KR;
1746 else if (ad_reg & 0x20)
1747 mode = XGBE_MODE_KX_1000;
1748 else
1749 mode = XGBE_MODE_UNKNOWN;
1750
1751 /* Compare Advertisement and Link Partner register 3 */
1752 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1753 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1754 if (lp_reg & 0xc000)
1755 XGBE_SET_LP_ADV(lks, 10000baseR_FEC);
1756
1757 return mode;
1758 }
1759
xgbe_phy_an_outcome(struct xgbe_prv_data * pdata)1760 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1761 {
1762 switch (pdata->an_mode) {
1763 case XGBE_AN_MODE_CL73:
1764 return xgbe_phy_an73_outcome(pdata);
1765 case XGBE_AN_MODE_CL73_REDRV:
1766 return xgbe_phy_an73_redrv_outcome(pdata);
1767 case XGBE_AN_MODE_CL37:
1768 return xgbe_phy_an37_outcome(pdata);
1769 case XGBE_AN_MODE_CL37_SGMII:
1770 return xgbe_phy_an37_sgmii_outcome(pdata);
1771 default:
1772 return XGBE_MODE_UNKNOWN;
1773 }
1774 }
1775
xgbe_phy_an_advertising(struct xgbe_prv_data * pdata,struct ethtool_link_ksettings * dlks)1776 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata,
1777 struct ethtool_link_ksettings *dlks)
1778 {
1779 struct ethtool_link_ksettings *slks = &pdata->phy.lks;
1780 struct xgbe_phy_data *phy_data = pdata->phy_data;
1781
1782 XGBE_LM_COPY(dlks, advertising, slks, advertising);
1783
1784 /* Without a re-driver, just return current advertising */
1785 if (!phy_data->redrv)
1786 return;
1787
1788 /* With the KR re-driver we need to advertise a single speed */
1789 XGBE_CLR_ADV(dlks, 1000baseKX_Full);
1790 XGBE_CLR_ADV(dlks, 10000baseKR_Full);
1791
1792 /* Advertise FEC support is present */
1793 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1794 XGBE_SET_ADV(dlks, 10000baseR_FEC);
1795
1796 switch (phy_data->port_mode) {
1797 case XGBE_PORT_MODE_BACKPLANE:
1798 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1799 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1800 break;
1801 case XGBE_PORT_MODE_BACKPLANE_2500:
1802 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1803 break;
1804 case XGBE_PORT_MODE_1000BASE_T:
1805 case XGBE_PORT_MODE_1000BASE_X:
1806 case XGBE_PORT_MODE_NBASE_T:
1807 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1808 break;
1809 case XGBE_PORT_MODE_10GBASE_T:
1810 if (phy_data->phydev &&
1811 (phy_data->phydev->speed == SPEED_10000))
1812 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1813 else
1814 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1815 break;
1816 case XGBE_PORT_MODE_10GBASE_R:
1817 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1818 break;
1819 case XGBE_PORT_MODE_SFP:
1820 switch (phy_data->sfp_base) {
1821 case XGBE_SFP_BASE_1000_T:
1822 case XGBE_SFP_BASE_1000_SX:
1823 case XGBE_SFP_BASE_1000_LX:
1824 case XGBE_SFP_BASE_1000_CX:
1825 XGBE_SET_ADV(dlks, 1000baseKX_Full);
1826 break;
1827 default:
1828 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1829 break;
1830 }
1831 break;
1832 default:
1833 XGBE_SET_ADV(dlks, 10000baseKR_Full);
1834 break;
1835 }
1836 }
1837
xgbe_phy_an_config(struct xgbe_prv_data * pdata)1838 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1839 {
1840 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1841 struct xgbe_phy_data *phy_data = pdata->phy_data;
1842 int ret;
1843
1844 ret = xgbe_phy_find_phy_device(pdata);
1845 if (ret)
1846 return ret;
1847
1848 if (!phy_data->phydev)
1849 return 0;
1850
1851 phy_data->phydev->autoneg = pdata->phy.autoneg;
1852 linkmode_and(phy_data->phydev->advertising,
1853 phy_data->phydev->supported,
1854 lks->link_modes.advertising);
1855
1856 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1857 phy_data->phydev->speed = pdata->phy.speed;
1858 phy_data->phydev->duplex = pdata->phy.duplex;
1859 }
1860
1861 ret = phy_start_aneg(phy_data->phydev);
1862
1863 return ret;
1864 }
1865
xgbe_phy_an_sfp_mode(struct xgbe_phy_data * phy_data)1866 static enum xgbe_an_mode xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1867 {
1868 switch (phy_data->sfp_base) {
1869 case XGBE_SFP_BASE_1000_T:
1870 return XGBE_AN_MODE_CL37_SGMII;
1871 case XGBE_SFP_BASE_1000_SX:
1872 case XGBE_SFP_BASE_1000_LX:
1873 case XGBE_SFP_BASE_1000_CX:
1874 return XGBE_AN_MODE_CL37;
1875 default:
1876 return XGBE_AN_MODE_NONE;
1877 }
1878 }
1879
xgbe_phy_an_mode(struct xgbe_prv_data * pdata)1880 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1881 {
1882 struct xgbe_phy_data *phy_data = pdata->phy_data;
1883
1884 /* A KR re-driver will always require CL73 AN */
1885 if (phy_data->redrv)
1886 return XGBE_AN_MODE_CL73_REDRV;
1887
1888 switch (phy_data->port_mode) {
1889 case XGBE_PORT_MODE_BACKPLANE:
1890 return XGBE_AN_MODE_CL73;
1891 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
1892 case XGBE_PORT_MODE_BACKPLANE_2500:
1893 return XGBE_AN_MODE_NONE;
1894 case XGBE_PORT_MODE_1000BASE_T:
1895 return XGBE_AN_MODE_CL37_SGMII;
1896 case XGBE_PORT_MODE_1000BASE_X:
1897 return XGBE_AN_MODE_CL37;
1898 case XGBE_PORT_MODE_NBASE_T:
1899 return XGBE_AN_MODE_CL37_SGMII;
1900 case XGBE_PORT_MODE_10GBASE_T:
1901 return XGBE_AN_MODE_CL73;
1902 case XGBE_PORT_MODE_10GBASE_R:
1903 return XGBE_AN_MODE_NONE;
1904 case XGBE_PORT_MODE_SFP:
1905 return xgbe_phy_an_sfp_mode(phy_data);
1906 default:
1907 return XGBE_AN_MODE_NONE;
1908 }
1909 }
1910
xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1911 static int xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1912 enum xgbe_phy_redrv_mode mode)
1913 {
1914 struct xgbe_phy_data *phy_data = pdata->phy_data;
1915 u16 redrv_reg, redrv_val;
1916
1917 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1918 redrv_val = (u16)mode;
1919
1920 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1921 redrv_reg, redrv_val);
1922 }
1923
xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data * pdata,enum xgbe_phy_redrv_mode mode)1924 static int xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1925 enum xgbe_phy_redrv_mode mode)
1926 {
1927 struct xgbe_phy_data *phy_data = pdata->phy_data;
1928 unsigned int redrv_reg;
1929 int ret;
1930
1931 /* Calculate the register to write */
1932 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1933
1934 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1935
1936 return ret;
1937 }
1938
xgbe_phy_set_redrv_mode(struct xgbe_prv_data * pdata)1939 static void xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1940 {
1941 struct xgbe_phy_data *phy_data = pdata->phy_data;
1942 enum xgbe_phy_redrv_mode mode;
1943 int ret;
1944
1945 if (!phy_data->redrv)
1946 return;
1947
1948 mode = XGBE_PHY_REDRV_MODE_CX;
1949 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1950 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
1951 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
1952 mode = XGBE_PHY_REDRV_MODE_SR;
1953
1954 ret = xgbe_phy_get_comm_ownership(pdata);
1955 if (ret)
1956 return;
1957
1958 if (phy_data->redrv_if)
1959 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
1960 else
1961 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
1962
1963 xgbe_phy_put_comm_ownership(pdata);
1964 }
1965
xgbe_phy_rx_reset(struct xgbe_prv_data * pdata)1966 static void xgbe_phy_rx_reset(struct xgbe_prv_data *pdata)
1967 {
1968 int reg;
1969
1970 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
1971 XGBE_PCS_PSEQ_STATE_MASK);
1972 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
1973 /* Mailbox command timed out, reset of RX block is required.
1974 * This can be done by asseting the reset bit and wait for
1975 * its compeletion.
1976 */
1977 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1978 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);
1979 ndelay(20);
1980 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
1981 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);
1982 usleep_range(40, 50);
1983 netif_err(pdata, link, pdata->netdev, "firmware mailbox reset performed\n");
1984 }
1985 }
1986
xgbe_phy_pll_ctrl(struct xgbe_prv_data * pdata,bool enable)1987 static void xgbe_phy_pll_ctrl(struct xgbe_prv_data *pdata, bool enable)
1988 {
1989 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
1990 if (pdata->phy.autoneg != AUTONEG_DISABLE)
1991 return;
1992
1993 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
1994 XGBE_PMA_PLL_CTRL_MASK,
1995 enable ? XGBE_PMA_PLL_CTRL_ENABLE
1996 : XGBE_PMA_PLL_CTRL_DISABLE);
1997
1998 /* Wait for command to complete */
1999 usleep_range(100, 200);
2000 }
2001
xgbe_phy_perform_ratechange(struct xgbe_prv_data * pdata,enum xgbe_mb_cmd cmd,enum xgbe_mb_subcmd sub_cmd)2002 static void xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata,
2003 enum xgbe_mb_cmd cmd, enum xgbe_mb_subcmd sub_cmd)
2004 {
2005 unsigned int s0 = 0;
2006 unsigned int wait;
2007
2008 /* Disable PLL re-initialization during FW command processing */
2009 xgbe_phy_pll_ctrl(pdata, false);
2010
2011 /* Log if a previous command did not complete */
2012 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2013 netif_dbg(pdata, link, pdata->netdev,
2014 "firmware mailbox not ready for command\n");
2015 xgbe_phy_rx_reset(pdata);
2016 }
2017
2018 /* Construct the command */
2019 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2020 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2021
2022 /* Issue the command */
2023 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2024 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2025 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2026
2027 /* Wait for command to complete */
2028 wait = XGBE_RATECHANGE_COUNT;
2029 while (wait--) {
2030 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2031 goto reenable_pll;
2032
2033 usleep_range(1000, 2000);
2034 }
2035
2036 netif_dbg(pdata, link, pdata->netdev,
2037 "firmware mailbox command did not complete\n");
2038
2039 /* Reset on error */
2040 xgbe_phy_rx_reset(pdata);
2041
2042 reenable_pll:
2043 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
2044 if (cmd != XGBE_MB_CMD_POWER_OFF &&
2045 cmd != XGBE_MB_CMD_RRC)
2046 xgbe_phy_pll_ctrl(pdata, true);
2047 }
2048
xgbe_phy_rrc(struct xgbe_prv_data * pdata)2049 static void xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2050 {
2051 /* Receiver Reset Cycle */
2052 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_RRC, XGBE_MB_SUBCMD_NONE);
2053
2054 netif_dbg(pdata, link, pdata->netdev, "receiver reset complete\n");
2055 }
2056
xgbe_phy_power_off(struct xgbe_prv_data * pdata)2057 static void xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2058 {
2059 struct xgbe_phy_data *phy_data = pdata->phy_data;
2060
2061 /* Power off */
2062 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_POWER_OFF, XGBE_MB_SUBCMD_NONE);
2063
2064 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2065
2066 netif_dbg(pdata, link, pdata->netdev, "phy powered off\n");
2067 }
2068
xgbe_phy_sfi_mode(struct xgbe_prv_data * pdata)2069 static void xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2070 {
2071 struct xgbe_phy_data *phy_data = pdata->phy_data;
2072
2073 xgbe_phy_set_redrv_mode(pdata);
2074
2075 /* 10G/SFI */
2076 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE) {
2077 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI, XGBE_MB_SUBCMD_ACTIVE);
2078 } else {
2079 if (phy_data->sfp_cable_len <= 1)
2080 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2081 XGBE_MB_SUBCMD_PASSIVE_1M);
2082 else if (phy_data->sfp_cable_len <= 3)
2083 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2084 XGBE_MB_SUBCMD_PASSIVE_3M);
2085 else
2086 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_SFI,
2087 XGBE_MB_SUBCMD_PASSIVE_OTHER);
2088 }
2089
2090 phy_data->cur_mode = XGBE_MODE_SFI;
2091
2092 netif_dbg(pdata, link, pdata->netdev, "10GbE SFI mode set\n");
2093 }
2094
xgbe_phy_x_mode(struct xgbe_prv_data * pdata)2095 static void xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2096 {
2097 struct xgbe_phy_data *phy_data = pdata->phy_data;
2098
2099 xgbe_phy_set_redrv_mode(pdata);
2100
2101 /* 1G/X */
2102 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2103
2104 phy_data->cur_mode = XGBE_MODE_X;
2105
2106 netif_dbg(pdata, link, pdata->netdev, "1GbE X mode set\n");
2107 }
2108
xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data * pdata)2109 static void xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2110 {
2111 struct xgbe_phy_data *phy_data = pdata->phy_data;
2112
2113 xgbe_phy_set_redrv_mode(pdata);
2114
2115 /* 1G/SGMII */
2116 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_SGMII);
2117
2118 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2119
2120 netif_dbg(pdata, link, pdata->netdev, "1GbE SGMII mode set\n");
2121 }
2122
xgbe_phy_sgmii_100_mode(struct xgbe_prv_data * pdata)2123 static void xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2124 {
2125 struct xgbe_phy_data *phy_data = pdata->phy_data;
2126
2127 xgbe_phy_set_redrv_mode(pdata);
2128
2129 /* 100M/SGMII */
2130 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_100MBITS);
2131
2132 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2133
2134 netif_dbg(pdata, link, pdata->netdev, "100MbE SGMII mode set\n");
2135 }
2136
xgbe_phy_kr_mode(struct xgbe_prv_data * pdata)2137 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2138 {
2139 struct xgbe_phy_data *phy_data = pdata->phy_data;
2140
2141 xgbe_phy_set_redrv_mode(pdata);
2142
2143 /* 10G/KR */
2144 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_10G_KR, XGBE_MB_SUBCMD_NONE);
2145
2146 phy_data->cur_mode = XGBE_MODE_KR;
2147
2148 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n");
2149 }
2150
xgbe_phy_kx_2500_mode(struct xgbe_prv_data * pdata)2151 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2152 {
2153 struct xgbe_phy_data *phy_data = pdata->phy_data;
2154
2155 xgbe_phy_set_redrv_mode(pdata);
2156
2157 /* 2.5G/KX */
2158 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_2_5G, XGBE_MB_SUBCMD_NONE);
2159
2160 phy_data->cur_mode = XGBE_MODE_KX_2500;
2161
2162 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n");
2163 }
2164
xgbe_phy_kx_1000_mode(struct xgbe_prv_data * pdata)2165 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2166 {
2167 struct xgbe_phy_data *phy_data = pdata->phy_data;
2168
2169 xgbe_phy_set_redrv_mode(pdata);
2170
2171 /* 1G/KX */
2172 xgbe_phy_perform_ratechange(pdata, XGBE_MB_CMD_SET_1G, XGBE_MB_SUBCMD_1G_KX);
2173
2174 phy_data->cur_mode = XGBE_MODE_KX_1000;
2175
2176 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n");
2177 }
2178
xgbe_phy_cur_mode(struct xgbe_prv_data * pdata)2179 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2180 {
2181 struct xgbe_phy_data *phy_data = pdata->phy_data;
2182
2183 return phy_data->cur_mode;
2184 }
2185
xgbe_phy_switch_baset_mode(struct xgbe_prv_data * pdata)2186 static enum xgbe_mode xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2187 {
2188 struct xgbe_phy_data *phy_data = pdata->phy_data;
2189
2190 /* No switching if not 10GBase-T */
2191 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2192 return xgbe_phy_cur_mode(pdata);
2193
2194 switch (xgbe_phy_cur_mode(pdata)) {
2195 case XGBE_MODE_SGMII_100:
2196 case XGBE_MODE_SGMII_1000:
2197 return XGBE_MODE_KR;
2198 case XGBE_MODE_KR:
2199 default:
2200 return XGBE_MODE_SGMII_1000;
2201 }
2202 }
2203
xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data * pdata)2204 static enum xgbe_mode xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2205 {
2206 return XGBE_MODE_KX_2500;
2207 }
2208
xgbe_phy_switch_bp_mode(struct xgbe_prv_data * pdata)2209 static enum xgbe_mode xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2210 {
2211 /* If we are in KR switch to KX, and vice-versa */
2212 switch (xgbe_phy_cur_mode(pdata)) {
2213 case XGBE_MODE_KX_1000:
2214 return XGBE_MODE_KR;
2215 case XGBE_MODE_KR:
2216 default:
2217 return XGBE_MODE_KX_1000;
2218 }
2219 }
2220
xgbe_phy_switch_mode(struct xgbe_prv_data * pdata)2221 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2222 {
2223 struct xgbe_phy_data *phy_data = pdata->phy_data;
2224
2225 switch (phy_data->port_mode) {
2226 case XGBE_PORT_MODE_BACKPLANE:
2227 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2228 return xgbe_phy_switch_bp_mode(pdata);
2229 case XGBE_PORT_MODE_BACKPLANE_2500:
2230 return xgbe_phy_switch_bp_2500_mode(pdata);
2231 case XGBE_PORT_MODE_1000BASE_T:
2232 case XGBE_PORT_MODE_NBASE_T:
2233 case XGBE_PORT_MODE_10GBASE_T:
2234 return xgbe_phy_switch_baset_mode(pdata);
2235 case XGBE_PORT_MODE_1000BASE_X:
2236 case XGBE_PORT_MODE_10GBASE_R:
2237 case XGBE_PORT_MODE_SFP:
2238 /* No switching, so just return current mode */
2239 return xgbe_phy_cur_mode(pdata);
2240 default:
2241 return XGBE_MODE_UNKNOWN;
2242 }
2243 }
2244
xgbe_phy_get_basex_mode(struct xgbe_phy_data * phy_data,int speed)2245 static enum xgbe_mode xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data,
2246 int speed)
2247 {
2248 switch (speed) {
2249 case SPEED_1000:
2250 return XGBE_MODE_X;
2251 case SPEED_10000:
2252 return XGBE_MODE_KR;
2253 default:
2254 return XGBE_MODE_UNKNOWN;
2255 }
2256 }
2257
xgbe_phy_get_baset_mode(struct xgbe_phy_data * phy_data,int speed)2258 static enum xgbe_mode xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data,
2259 int speed)
2260 {
2261 switch (speed) {
2262 case SPEED_100:
2263 return XGBE_MODE_SGMII_100;
2264 case SPEED_1000:
2265 return XGBE_MODE_SGMII_1000;
2266 case SPEED_2500:
2267 return XGBE_MODE_KX_2500;
2268 case SPEED_10000:
2269 return XGBE_MODE_KR;
2270 default:
2271 return XGBE_MODE_UNKNOWN;
2272 }
2273 }
2274
xgbe_phy_get_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2275 static enum xgbe_mode xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data,
2276 int speed)
2277 {
2278 switch (speed) {
2279 case SPEED_100:
2280 return XGBE_MODE_SGMII_100;
2281 case SPEED_1000:
2282 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2283 return XGBE_MODE_SGMII_1000;
2284 else
2285 return XGBE_MODE_X;
2286 case SPEED_10000:
2287 case SPEED_UNKNOWN:
2288 return XGBE_MODE_SFI;
2289 default:
2290 return XGBE_MODE_UNKNOWN;
2291 }
2292 }
2293
xgbe_phy_get_bp_2500_mode(int speed)2294 static enum xgbe_mode xgbe_phy_get_bp_2500_mode(int speed)
2295 {
2296 switch (speed) {
2297 case SPEED_2500:
2298 return XGBE_MODE_KX_2500;
2299 default:
2300 return XGBE_MODE_UNKNOWN;
2301 }
2302 }
2303
xgbe_phy_get_bp_mode(int speed)2304 static enum xgbe_mode xgbe_phy_get_bp_mode(int speed)
2305 {
2306 switch (speed) {
2307 case SPEED_1000:
2308 return XGBE_MODE_KX_1000;
2309 case SPEED_10000:
2310 return XGBE_MODE_KR;
2311 default:
2312 return XGBE_MODE_UNKNOWN;
2313 }
2314 }
2315
xgbe_phy_get_mode(struct xgbe_prv_data * pdata,int speed)2316 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata,
2317 int speed)
2318 {
2319 struct xgbe_phy_data *phy_data = pdata->phy_data;
2320
2321 switch (phy_data->port_mode) {
2322 case XGBE_PORT_MODE_BACKPLANE:
2323 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2324 return xgbe_phy_get_bp_mode(speed);
2325 case XGBE_PORT_MODE_BACKPLANE_2500:
2326 return xgbe_phy_get_bp_2500_mode(speed);
2327 case XGBE_PORT_MODE_1000BASE_T:
2328 case XGBE_PORT_MODE_NBASE_T:
2329 case XGBE_PORT_MODE_10GBASE_T:
2330 return xgbe_phy_get_baset_mode(phy_data, speed);
2331 case XGBE_PORT_MODE_1000BASE_X:
2332 case XGBE_PORT_MODE_10GBASE_R:
2333 return xgbe_phy_get_basex_mode(phy_data, speed);
2334 case XGBE_PORT_MODE_SFP:
2335 return xgbe_phy_get_sfp_mode(phy_data, speed);
2336 default:
2337 return XGBE_MODE_UNKNOWN;
2338 }
2339 }
2340
xgbe_phy_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2341 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2342 {
2343 switch (mode) {
2344 case XGBE_MODE_KX_1000:
2345 xgbe_phy_kx_1000_mode(pdata);
2346 break;
2347 case XGBE_MODE_KX_2500:
2348 xgbe_phy_kx_2500_mode(pdata);
2349 break;
2350 case XGBE_MODE_KR:
2351 xgbe_phy_kr_mode(pdata);
2352 break;
2353 case XGBE_MODE_SGMII_100:
2354 xgbe_phy_sgmii_100_mode(pdata);
2355 break;
2356 case XGBE_MODE_SGMII_1000:
2357 xgbe_phy_sgmii_1000_mode(pdata);
2358 break;
2359 case XGBE_MODE_X:
2360 xgbe_phy_x_mode(pdata);
2361 break;
2362 case XGBE_MODE_SFI:
2363 xgbe_phy_sfi_mode(pdata);
2364 break;
2365 default:
2366 break;
2367 }
2368 }
2369
xgbe_phy_check_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode,bool advert)2370 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata,
2371 enum xgbe_mode mode, bool advert)
2372 {
2373 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
2374 return advert;
2375 } else {
2376 enum xgbe_mode cur_mode;
2377
2378 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2379 if (cur_mode == mode)
2380 return true;
2381 }
2382
2383 return false;
2384 }
2385
xgbe_phy_use_basex_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2386 static bool xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata,
2387 enum xgbe_mode mode)
2388 {
2389 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2390
2391 switch (mode) {
2392 case XGBE_MODE_X:
2393 return xgbe_phy_check_mode(pdata, mode,
2394 XGBE_ADV(lks, 1000baseX_Full));
2395 case XGBE_MODE_KR:
2396 return xgbe_phy_check_mode(pdata, mode,
2397 XGBE_ADV(lks, 10000baseKR_Full));
2398 default:
2399 return false;
2400 }
2401 }
2402
xgbe_phy_use_baset_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2403 static bool xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata,
2404 enum xgbe_mode mode)
2405 {
2406 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2407
2408 switch (mode) {
2409 case XGBE_MODE_SGMII_100:
2410 return xgbe_phy_check_mode(pdata, mode,
2411 XGBE_ADV(lks, 100baseT_Full));
2412 case XGBE_MODE_SGMII_1000:
2413 return xgbe_phy_check_mode(pdata, mode,
2414 XGBE_ADV(lks, 1000baseT_Full));
2415 case XGBE_MODE_KX_2500:
2416 return xgbe_phy_check_mode(pdata, mode,
2417 XGBE_ADV(lks, 2500baseT_Full));
2418 case XGBE_MODE_KR:
2419 return xgbe_phy_check_mode(pdata, mode,
2420 XGBE_ADV(lks, 10000baseT_Full));
2421 default:
2422 return false;
2423 }
2424 }
2425
xgbe_phy_use_sfp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2426 static bool xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata,
2427 enum xgbe_mode mode)
2428 {
2429 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2430 struct xgbe_phy_data *phy_data = pdata->phy_data;
2431
2432 switch (mode) {
2433 case XGBE_MODE_X:
2434 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2435 return false;
2436 return xgbe_phy_check_mode(pdata, mode,
2437 XGBE_ADV(lks, 1000baseX_Full));
2438 case XGBE_MODE_SGMII_100:
2439 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2440 return false;
2441 return xgbe_phy_check_mode(pdata, mode,
2442 XGBE_ADV(lks, 100baseT_Full));
2443 case XGBE_MODE_SGMII_1000:
2444 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2445 return false;
2446 return xgbe_phy_check_mode(pdata, mode,
2447 XGBE_ADV(lks, 1000baseT_Full));
2448 case XGBE_MODE_SFI:
2449 if (phy_data->sfp_mod_absent)
2450 return true;
2451 return xgbe_phy_check_mode(pdata, mode,
2452 XGBE_ADV(lks, 10000baseSR_Full) ||
2453 XGBE_ADV(lks, 10000baseLR_Full) ||
2454 XGBE_ADV(lks, 10000baseLRM_Full) ||
2455 XGBE_ADV(lks, 10000baseER_Full) ||
2456 XGBE_ADV(lks, 10000baseCR_Full));
2457 default:
2458 return false;
2459 }
2460 }
2461
xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2462 static bool xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata,
2463 enum xgbe_mode mode)
2464 {
2465 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2466
2467 switch (mode) {
2468 case XGBE_MODE_KX_2500:
2469 return xgbe_phy_check_mode(pdata, mode,
2470 XGBE_ADV(lks, 2500baseX_Full));
2471 default:
2472 return false;
2473 }
2474 }
2475
xgbe_phy_use_bp_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2476 static bool xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata,
2477 enum xgbe_mode mode)
2478 {
2479 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
2480
2481 switch (mode) {
2482 case XGBE_MODE_KX_1000:
2483 return xgbe_phy_check_mode(pdata, mode,
2484 XGBE_ADV(lks, 1000baseKX_Full));
2485 case XGBE_MODE_KR:
2486 return xgbe_phy_check_mode(pdata, mode,
2487 XGBE_ADV(lks, 10000baseKR_Full));
2488 default:
2489 return false;
2490 }
2491 }
2492
xgbe_phy_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)2493 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2494 {
2495 struct xgbe_phy_data *phy_data = pdata->phy_data;
2496
2497 switch (phy_data->port_mode) {
2498 case XGBE_PORT_MODE_BACKPLANE:
2499 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2500 return xgbe_phy_use_bp_mode(pdata, mode);
2501 case XGBE_PORT_MODE_BACKPLANE_2500:
2502 return xgbe_phy_use_bp_2500_mode(pdata, mode);
2503 case XGBE_PORT_MODE_1000BASE_T:
2504 case XGBE_PORT_MODE_NBASE_T:
2505 case XGBE_PORT_MODE_10GBASE_T:
2506 return xgbe_phy_use_baset_mode(pdata, mode);
2507 case XGBE_PORT_MODE_1000BASE_X:
2508 case XGBE_PORT_MODE_10GBASE_R:
2509 return xgbe_phy_use_basex_mode(pdata, mode);
2510 case XGBE_PORT_MODE_SFP:
2511 return xgbe_phy_use_sfp_mode(pdata, mode);
2512 default:
2513 return false;
2514 }
2515 }
2516
xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data * phy_data,int speed)2517 static bool xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data,
2518 int speed)
2519 {
2520 switch (speed) {
2521 case SPEED_1000:
2522 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2523 case SPEED_10000:
2524 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2525 default:
2526 return false;
2527 }
2528 }
2529
xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data * phy_data,int speed)2530 static bool xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data,
2531 int speed)
2532 {
2533 switch (speed) {
2534 case SPEED_100:
2535 case SPEED_1000:
2536 return true;
2537 case SPEED_2500:
2538 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2539 case SPEED_10000:
2540 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2541 default:
2542 return false;
2543 }
2544 }
2545
xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data * phy_data,int speed)2546 static bool xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data,
2547 int speed)
2548 {
2549 switch (speed) {
2550 case SPEED_100:
2551 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2552 case SPEED_1000:
2553 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2554 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2555 case SPEED_10000:
2556 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2557 default:
2558 return false;
2559 }
2560 }
2561
xgbe_phy_valid_speed_bp_2500_mode(int speed)2562 static bool xgbe_phy_valid_speed_bp_2500_mode(int speed)
2563 {
2564 switch (speed) {
2565 case SPEED_2500:
2566 return true;
2567 default:
2568 return false;
2569 }
2570 }
2571
xgbe_phy_valid_speed_bp_mode(int speed)2572 static bool xgbe_phy_valid_speed_bp_mode(int speed)
2573 {
2574 switch (speed) {
2575 case SPEED_1000:
2576 case SPEED_10000:
2577 return true;
2578 default:
2579 return false;
2580 }
2581 }
2582
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)2583 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2584 {
2585 struct xgbe_phy_data *phy_data = pdata->phy_data;
2586
2587 switch (phy_data->port_mode) {
2588 case XGBE_PORT_MODE_BACKPLANE:
2589 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2590 return xgbe_phy_valid_speed_bp_mode(speed);
2591 case XGBE_PORT_MODE_BACKPLANE_2500:
2592 return xgbe_phy_valid_speed_bp_2500_mode(speed);
2593 case XGBE_PORT_MODE_1000BASE_T:
2594 case XGBE_PORT_MODE_NBASE_T:
2595 case XGBE_PORT_MODE_10GBASE_T:
2596 return xgbe_phy_valid_speed_baset_mode(phy_data, speed);
2597 case XGBE_PORT_MODE_1000BASE_X:
2598 case XGBE_PORT_MODE_10GBASE_R:
2599 return xgbe_phy_valid_speed_basex_mode(phy_data, speed);
2600 case XGBE_PORT_MODE_SFP:
2601 return xgbe_phy_valid_speed_sfp_mode(phy_data, speed);
2602 default:
2603 return false;
2604 }
2605 }
2606
xgbe_phy_link_status(struct xgbe_prv_data * pdata,int * an_restart)2607 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2608 {
2609 struct xgbe_phy_data *phy_data = pdata->phy_data;
2610 unsigned int reg;
2611 int ret;
2612
2613 *an_restart = 0;
2614
2615 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2616 /* Check SFP signals */
2617 xgbe_phy_sfp_detect(pdata);
2618
2619 if (phy_data->sfp_changed) {
2620 *an_restart = 1;
2621 return 0;
2622 }
2623
2624 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los)
2625 return 0;
2626 }
2627
2628 if (phy_data->phydev) {
2629 /* Check external PHY */
2630 ret = phy_read_status(phy_data->phydev);
2631 if (ret < 0)
2632 return 0;
2633
2634 if ((pdata->phy.autoneg == AUTONEG_ENABLE) &&
2635 !phy_aneg_done(phy_data->phydev))
2636 return 0;
2637
2638 if (!phy_data->phydev->link)
2639 return 0;
2640 }
2641
2642 /* Link status is latched low, so read once to clear
2643 * and then read again to get current state
2644 */
2645 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2646 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2647 if (reg & MDIO_STAT1_LSTATUS)
2648 return 1;
2649
2650 if (pdata->phy.autoneg == AUTONEG_ENABLE &&
2651 phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE) {
2652 if (!test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
2653 netif_carrier_off(pdata->netdev);
2654 *an_restart = 1;
2655 }
2656 }
2657
2658 /* No link, attempt a receiver reset cycle */
2659 if (pdata->vdata->enable_rrc && phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2660 phy_data->rrc_count = 0;
2661 xgbe_phy_rrc(pdata);
2662 }
2663
2664 return 0;
2665 }
2666
xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data * pdata)2667 static void xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2668 {
2669 struct xgbe_phy_data *phy_data = pdata->phy_data;
2670
2671 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2672 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2673 GPIO_ADDR);
2674
2675 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2676 GPIO_MASK);
2677
2678 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2679 GPIO_RX_LOS);
2680 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2681 GPIO_TX_FAULT);
2682 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2683 GPIO_MOD_ABS);
2684 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2685 GPIO_RATE_SELECT);
2686
2687 if (netif_msg_probe(pdata)) {
2688 dev_dbg(pdata->dev, "SFP: gpio_address=%#x\n",
2689 phy_data->sfp_gpio_address);
2690 dev_dbg(pdata->dev, "SFP: gpio_mask=%#x\n",
2691 phy_data->sfp_gpio_mask);
2692 dev_dbg(pdata->dev, "SFP: gpio_rx_los=%u\n",
2693 phy_data->sfp_gpio_rx_los);
2694 dev_dbg(pdata->dev, "SFP: gpio_tx_fault=%u\n",
2695 phy_data->sfp_gpio_tx_fault);
2696 dev_dbg(pdata->dev, "SFP: gpio_mod_absent=%u\n",
2697 phy_data->sfp_gpio_mod_absent);
2698 dev_dbg(pdata->dev, "SFP: gpio_rate_select=%u\n",
2699 phy_data->sfp_gpio_rate_select);
2700 }
2701 }
2702
xgbe_phy_sfp_comm_setup(struct xgbe_prv_data * pdata)2703 static void xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2704 {
2705 struct xgbe_phy_data *phy_data = pdata->phy_data;
2706 unsigned int mux_addr_hi, mux_addr_lo;
2707
2708 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2709 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2710 if (mux_addr_lo == XGBE_SFP_DIRECT)
2711 return;
2712
2713 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2714 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2715 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2716 MUX_CHAN);
2717
2718 if (netif_msg_probe(pdata)) {
2719 dev_dbg(pdata->dev, "SFP: mux_address=%#x\n",
2720 phy_data->sfp_mux_address);
2721 dev_dbg(pdata->dev, "SFP: mux_channel=%u\n",
2722 phy_data->sfp_mux_channel);
2723 }
2724 }
2725
xgbe_phy_sfp_setup(struct xgbe_prv_data * pdata)2726 static void xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2727 {
2728 xgbe_phy_sfp_comm_setup(pdata);
2729 xgbe_phy_sfp_gpio_setup(pdata);
2730 }
2731
xgbe_phy_int_mdio_reset(struct xgbe_prv_data * pdata)2732 static int xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2733 {
2734 struct xgbe_phy_data *phy_data = pdata->phy_data;
2735 unsigned int ret;
2736
2737 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2738 if (ret)
2739 return ret;
2740
2741 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2742
2743 return ret;
2744 }
2745
xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data * pdata)2746 static int xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2747 {
2748 struct xgbe_phy_data *phy_data = pdata->phy_data;
2749 u8 gpio_reg, gpio_ports[2], gpio_data[3];
2750 int ret;
2751
2752 /* Read the output port registers */
2753 gpio_reg = 2;
2754 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2755 &gpio_reg, sizeof(gpio_reg),
2756 gpio_ports, sizeof(gpio_ports));
2757 if (ret)
2758 return ret;
2759
2760 /* Prepare to write the GPIO data */
2761 gpio_data[0] = 2;
2762 gpio_data[1] = gpio_ports[0];
2763 gpio_data[2] = gpio_ports[1];
2764
2765 /* Set the GPIO pin */
2766 if (phy_data->mdio_reset_gpio < 8)
2767 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2768 else
2769 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2770
2771 /* Write the output port registers */
2772 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2773 gpio_data, sizeof(gpio_data));
2774 if (ret)
2775 return ret;
2776
2777 /* Clear the GPIO pin */
2778 if (phy_data->mdio_reset_gpio < 8)
2779 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2780 else
2781 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2782
2783 /* Write the output port registers */
2784 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2785 gpio_data, sizeof(gpio_data));
2786
2787 return ret;
2788 }
2789
xgbe_phy_mdio_reset(struct xgbe_prv_data * pdata)2790 static int xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
2791 {
2792 struct xgbe_phy_data *phy_data = pdata->phy_data;
2793 int ret;
2794
2795 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2796 return 0;
2797
2798 ret = xgbe_phy_get_comm_ownership(pdata);
2799 if (ret)
2800 return ret;
2801
2802 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
2803 ret = xgbe_phy_i2c_mdio_reset(pdata);
2804 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
2805 ret = xgbe_phy_int_mdio_reset(pdata);
2806
2807 xgbe_phy_put_comm_ownership(pdata);
2808
2809 return ret;
2810 }
2811
xgbe_phy_redrv_error(struct xgbe_phy_data * phy_data)2812 static bool xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
2813 {
2814 if (!phy_data->redrv)
2815 return false;
2816
2817 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
2818 return true;
2819
2820 switch (phy_data->redrv_model) {
2821 case XGBE_PHY_REDRV_MODEL_4223:
2822 if (phy_data->redrv_lane > 3)
2823 return true;
2824 break;
2825 case XGBE_PHY_REDRV_MODEL_4227:
2826 if (phy_data->redrv_lane > 1)
2827 return true;
2828 break;
2829 default:
2830 return true;
2831 }
2832
2833 return false;
2834 }
2835
xgbe_phy_mdio_reset_setup(struct xgbe_prv_data * pdata)2836 static int xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
2837 {
2838 struct xgbe_phy_data *phy_data = pdata->phy_data;
2839
2840 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
2841 return 0;
2842
2843 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
2844 switch (phy_data->mdio_reset) {
2845 case XGBE_MDIO_RESET_NONE:
2846 case XGBE_MDIO_RESET_I2C_GPIO:
2847 case XGBE_MDIO_RESET_INT_GPIO:
2848 break;
2849 default:
2850 dev_err(pdata->dev, "unsupported MDIO reset (%#x)\n",
2851 phy_data->mdio_reset);
2852 return -EINVAL;
2853 }
2854
2855 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
2856 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
2857 XP_GET_BITS(pdata->pp3, XP_PROP_3,
2858 MDIO_RESET_I2C_ADDR);
2859 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2860 MDIO_RESET_I2C_GPIO);
2861 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO) {
2862 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2863 MDIO_RESET_INT_GPIO);
2864 }
2865
2866 return 0;
2867 }
2868
xgbe_phy_port_mode_mismatch(struct xgbe_prv_data * pdata)2869 static bool xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
2870 {
2871 struct xgbe_phy_data *phy_data = pdata->phy_data;
2872
2873 switch (phy_data->port_mode) {
2874 case XGBE_PORT_MODE_BACKPLANE:
2875 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2876 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2877 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2878 return false;
2879 break;
2880 case XGBE_PORT_MODE_BACKPLANE_2500:
2881 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
2882 return false;
2883 break;
2884 case XGBE_PORT_MODE_1000BASE_T:
2885 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2886 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
2887 return false;
2888 break;
2889 case XGBE_PORT_MODE_1000BASE_X:
2890 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
2891 return false;
2892 break;
2893 case XGBE_PORT_MODE_NBASE_T:
2894 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2895 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2896 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
2897 return false;
2898 break;
2899 case XGBE_PORT_MODE_10GBASE_T:
2900 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2901 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2902 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2903 return false;
2904 break;
2905 case XGBE_PORT_MODE_10GBASE_R:
2906 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
2907 return false;
2908 break;
2909 case XGBE_PORT_MODE_SFP:
2910 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
2911 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
2912 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
2913 return false;
2914 break;
2915 default:
2916 break;
2917 }
2918
2919 return true;
2920 }
2921
xgbe_phy_conn_type_mismatch(struct xgbe_prv_data * pdata)2922 static bool xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
2923 {
2924 struct xgbe_phy_data *phy_data = pdata->phy_data;
2925
2926 switch (phy_data->port_mode) {
2927 case XGBE_PORT_MODE_BACKPLANE:
2928 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
2929 case XGBE_PORT_MODE_BACKPLANE_2500:
2930 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
2931 return false;
2932 break;
2933 case XGBE_PORT_MODE_1000BASE_T:
2934 case XGBE_PORT_MODE_1000BASE_X:
2935 case XGBE_PORT_MODE_NBASE_T:
2936 case XGBE_PORT_MODE_10GBASE_T:
2937 case XGBE_PORT_MODE_10GBASE_R:
2938 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
2939 return false;
2940 break;
2941 case XGBE_PORT_MODE_SFP:
2942 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
2943 return false;
2944 break;
2945 default:
2946 break;
2947 }
2948
2949 return true;
2950 }
2951
xgbe_phy_port_enabled(struct xgbe_prv_data * pdata)2952 static bool xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
2953 {
2954 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
2955 return false;
2956 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
2957 return false;
2958
2959 return true;
2960 }
2961
xgbe_phy_cdr_track(struct xgbe_prv_data * pdata)2962 static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
2963 {
2964 struct xgbe_phy_data *phy_data = pdata->phy_data;
2965
2966 if (!pdata->debugfs_an_cdr_workaround)
2967 return;
2968
2969 if (!phy_data->phy_cdr_notrack)
2970 return;
2971
2972 usleep_range(phy_data->phy_cdr_delay,
2973 phy_data->phy_cdr_delay + 500);
2974
2975 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2976 XGBE_PMA_CDR_TRACK_EN_MASK,
2977 XGBE_PMA_CDR_TRACK_EN_ON);
2978
2979 phy_data->phy_cdr_notrack = 0;
2980 }
2981
xgbe_phy_cdr_notrack(struct xgbe_prv_data * pdata)2982 static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
2983 {
2984 struct xgbe_phy_data *phy_data = pdata->phy_data;
2985
2986 if (!pdata->debugfs_an_cdr_workaround)
2987 return;
2988
2989 if (phy_data->phy_cdr_notrack)
2990 return;
2991
2992 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
2993 XGBE_PMA_CDR_TRACK_EN_MASK,
2994 XGBE_PMA_CDR_TRACK_EN_OFF);
2995
2996 xgbe_phy_rrc(pdata);
2997
2998 phy_data->phy_cdr_notrack = 1;
2999 }
3000
xgbe_phy_kr_training_post(struct xgbe_prv_data * pdata)3001 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3002 {
3003 if (!pdata->debugfs_an_cdr_track_early)
3004 xgbe_phy_cdr_track(pdata);
3005 }
3006
xgbe_phy_kr_training_pre(struct xgbe_prv_data * pdata)3007 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3008 {
3009 if (pdata->debugfs_an_cdr_track_early)
3010 xgbe_phy_cdr_track(pdata);
3011 }
3012
xgbe_phy_an_post(struct xgbe_prv_data * pdata)3013 static void xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3014 {
3015 struct xgbe_phy_data *phy_data = pdata->phy_data;
3016
3017 switch (pdata->an_mode) {
3018 case XGBE_AN_MODE_CL73:
3019 case XGBE_AN_MODE_CL73_REDRV:
3020 if (phy_data->cur_mode != XGBE_MODE_KR)
3021 break;
3022
3023 xgbe_phy_cdr_track(pdata);
3024
3025 switch (pdata->an_result) {
3026 case XGBE_AN_READY:
3027 case XGBE_AN_COMPLETE:
3028 break;
3029 default:
3030 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3031 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3032 else
3033 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3034 break;
3035 }
3036 break;
3037 default:
3038 break;
3039 }
3040 }
3041
xgbe_phy_an_pre(struct xgbe_prv_data * pdata)3042 static void xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3043 {
3044 struct xgbe_phy_data *phy_data = pdata->phy_data;
3045
3046 switch (pdata->an_mode) {
3047 case XGBE_AN_MODE_CL73:
3048 case XGBE_AN_MODE_CL73_REDRV:
3049 if (phy_data->cur_mode != XGBE_MODE_KR)
3050 break;
3051
3052 xgbe_phy_cdr_notrack(pdata);
3053 break;
3054 default:
3055 break;
3056 }
3057 }
3058
xgbe_phy_stop(struct xgbe_prv_data * pdata)3059 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
3060 {
3061 struct xgbe_phy_data *phy_data = pdata->phy_data;
3062
3063 /* If we have an external PHY, free it */
3064 xgbe_phy_free_phy_device(pdata);
3065
3066 /* Reset SFP data */
3067 xgbe_phy_sfp_reset(phy_data);
3068 xgbe_phy_sfp_mod_absent(pdata);
3069
3070 /* Reset CDR support */
3071 xgbe_phy_cdr_track(pdata);
3072
3073 /* Power off the PHY */
3074 xgbe_phy_power_off(pdata);
3075
3076 /* Stop the I2C controller */
3077 pdata->i2c_if.i2c_stop(pdata);
3078 }
3079
xgbe_phy_start(struct xgbe_prv_data * pdata)3080 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
3081 {
3082 struct xgbe_phy_data *phy_data = pdata->phy_data;
3083 int ret;
3084
3085 /* Start the I2C controller */
3086 ret = pdata->i2c_if.i2c_start(pdata);
3087 if (ret)
3088 return ret;
3089
3090 /* Set the proper MDIO mode for the re-driver */
3091 if (phy_data->redrv && !phy_data->redrv_if) {
3092 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3093 XGBE_MDIO_MODE_CL22);
3094 if (ret) {
3095 netdev_err(pdata->netdev,
3096 "redriver mdio port not compatible (%u)\n",
3097 phy_data->redrv_addr);
3098 return ret;
3099 }
3100 }
3101
3102 /* Start in highest supported mode */
3103 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3104
3105 /* Reset CDR support */
3106 xgbe_phy_cdr_track(pdata);
3107
3108 /* After starting the I2C controller, we can check for an SFP */
3109 switch (phy_data->port_mode) {
3110 case XGBE_PORT_MODE_SFP:
3111 xgbe_phy_sfp_detect(pdata);
3112 break;
3113 default:
3114 break;
3115 }
3116
3117 /* If we have an external PHY, start it */
3118 ret = xgbe_phy_find_phy_device(pdata);
3119 if (ret)
3120 goto err_i2c;
3121
3122 return 0;
3123
3124 err_i2c:
3125 pdata->i2c_if.i2c_stop(pdata);
3126
3127 return ret;
3128 }
3129
xgbe_phy_reset(struct xgbe_prv_data * pdata)3130 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
3131 {
3132 struct xgbe_phy_data *phy_data = pdata->phy_data;
3133 enum xgbe_mode cur_mode;
3134 int ret;
3135
3136 /* Reset by power cycling the PHY */
3137 cur_mode = phy_data->cur_mode;
3138 xgbe_phy_power_off(pdata);
3139 xgbe_phy_set_mode(pdata, cur_mode);
3140
3141 if (!phy_data->phydev)
3142 return 0;
3143
3144 /* Reset the external PHY */
3145 ret = xgbe_phy_mdio_reset(pdata);
3146 if (ret)
3147 return ret;
3148
3149 return phy_init_hw(phy_data->phydev);
3150 }
3151
xgbe_phy_exit(struct xgbe_prv_data * pdata)3152 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
3153 {
3154 struct xgbe_phy_data *phy_data = pdata->phy_data;
3155
3156 /* Unregister for driving external PHYs */
3157 mdiobus_unregister(phy_data->mii);
3158 }
3159
xgbe_phy_init(struct xgbe_prv_data * pdata)3160 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
3161 {
3162 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
3163 struct xgbe_phy_data *phy_data;
3164 struct mii_bus *mii;
3165 int ret;
3166
3167 /* Check if enabled */
3168 if (!xgbe_phy_port_enabled(pdata)) {
3169 dev_info(pdata->dev, "device is not enabled\n");
3170 return -ENODEV;
3171 }
3172
3173 /* Initialize the I2C controller */
3174 ret = pdata->i2c_if.i2c_init(pdata);
3175 if (ret)
3176 return ret;
3177
3178 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL);
3179 if (!phy_data)
3180 return -ENOMEM;
3181 pdata->phy_data = phy_data;
3182
3183 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3184 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3185 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3186 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3187 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3188 if (netif_msg_probe(pdata)) {
3189 dev_dbg(pdata->dev, "port mode=%u\n", phy_data->port_mode);
3190 dev_dbg(pdata->dev, "port id=%u\n", phy_data->port_id);
3191 dev_dbg(pdata->dev, "port speeds=%#x\n", phy_data->port_speeds);
3192 dev_dbg(pdata->dev, "conn type=%u\n", phy_data->conn_type);
3193 dev_dbg(pdata->dev, "mdio addr=%u\n", phy_data->mdio_addr);
3194 }
3195
3196 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3197 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3198 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3199 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3200 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3201 if (phy_data->redrv && netif_msg_probe(pdata)) {
3202 dev_dbg(pdata->dev, "redrv present\n");
3203 dev_dbg(pdata->dev, "redrv i/f=%u\n", phy_data->redrv_if);
3204 dev_dbg(pdata->dev, "redrv addr=%#x\n", phy_data->redrv_addr);
3205 dev_dbg(pdata->dev, "redrv lane=%u\n", phy_data->redrv_lane);
3206 dev_dbg(pdata->dev, "redrv model=%u\n", phy_data->redrv_model);
3207 }
3208
3209 /* Validate the connection requested */
3210 if (xgbe_phy_conn_type_mismatch(pdata)) {
3211 dev_err(pdata->dev, "phy mode/connection mismatch (%#x/%#x)\n",
3212 phy_data->port_mode, phy_data->conn_type);
3213 return -EINVAL;
3214 }
3215
3216 /* Validate the mode requested */
3217 if (xgbe_phy_port_mode_mismatch(pdata)) {
3218 dev_err(pdata->dev, "phy mode/speed mismatch (%#x/%#x)\n",
3219 phy_data->port_mode, phy_data->port_speeds);
3220 return -EINVAL;
3221 }
3222
3223 /* Check for and validate MDIO reset support */
3224 ret = xgbe_phy_mdio_reset_setup(pdata);
3225 if (ret)
3226 return ret;
3227
3228 /* Validate the re-driver information */
3229 if (xgbe_phy_redrv_error(phy_data)) {
3230 dev_err(pdata->dev, "phy re-driver settings error\n");
3231 return -EINVAL;
3232 }
3233 pdata->kr_redrv = phy_data->redrv;
3234
3235 /* Indicate current mode is unknown */
3236 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3237
3238 /* Initialize supported features */
3239 XGBE_ZERO_SUP(lks);
3240
3241 switch (phy_data->port_mode) {
3242 /* Backplane support */
3243 case XGBE_PORT_MODE_BACKPLANE:
3244 XGBE_SET_SUP(lks, Autoneg);
3245 fallthrough;
3246 case XGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
3247 XGBE_SET_SUP(lks, Pause);
3248 XGBE_SET_SUP(lks, Asym_Pause);
3249 XGBE_SET_SUP(lks, Backplane);
3250 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3251 XGBE_SET_SUP(lks, 1000baseKX_Full);
3252 phy_data->start_mode = XGBE_MODE_KX_1000;
3253 }
3254 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3255 XGBE_SET_SUP(lks, 10000baseKR_Full);
3256 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3257 XGBE_SET_SUP(lks, 10000baseR_FEC);
3258 phy_data->start_mode = XGBE_MODE_KR;
3259 }
3260
3261 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3262 break;
3263 case XGBE_PORT_MODE_BACKPLANE_2500:
3264 XGBE_SET_SUP(lks, Pause);
3265 XGBE_SET_SUP(lks, Asym_Pause);
3266 XGBE_SET_SUP(lks, Backplane);
3267 XGBE_SET_SUP(lks, 2500baseX_Full);
3268 phy_data->start_mode = XGBE_MODE_KX_2500;
3269
3270 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3271 break;
3272
3273 /* MDIO 1GBase-T support */
3274 case XGBE_PORT_MODE_1000BASE_T:
3275 XGBE_SET_SUP(lks, Autoneg);
3276 XGBE_SET_SUP(lks, Pause);
3277 XGBE_SET_SUP(lks, Asym_Pause);
3278 XGBE_SET_SUP(lks, TP);
3279 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3280 XGBE_SET_SUP(lks, 100baseT_Full);
3281 phy_data->start_mode = XGBE_MODE_SGMII_100;
3282 }
3283 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3284 XGBE_SET_SUP(lks, 1000baseT_Full);
3285 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3286 }
3287
3288 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3289 break;
3290
3291 /* MDIO Base-X support */
3292 case XGBE_PORT_MODE_1000BASE_X:
3293 XGBE_SET_SUP(lks, Autoneg);
3294 XGBE_SET_SUP(lks, Pause);
3295 XGBE_SET_SUP(lks, Asym_Pause);
3296 XGBE_SET_SUP(lks, FIBRE);
3297 XGBE_SET_SUP(lks, 1000baseX_Full);
3298 phy_data->start_mode = XGBE_MODE_X;
3299
3300 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3301 break;
3302
3303 /* MDIO NBase-T support */
3304 case XGBE_PORT_MODE_NBASE_T:
3305 XGBE_SET_SUP(lks, Autoneg);
3306 XGBE_SET_SUP(lks, Pause);
3307 XGBE_SET_SUP(lks, Asym_Pause);
3308 XGBE_SET_SUP(lks, TP);
3309 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3310 XGBE_SET_SUP(lks, 100baseT_Full);
3311 phy_data->start_mode = XGBE_MODE_SGMII_100;
3312 }
3313 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3314 XGBE_SET_SUP(lks, 1000baseT_Full);
3315 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3316 }
3317 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3318 XGBE_SET_SUP(lks, 2500baseT_Full);
3319 phy_data->start_mode = XGBE_MODE_KX_2500;
3320 }
3321
3322 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3323 break;
3324
3325 /* 10GBase-T support */
3326 case XGBE_PORT_MODE_10GBASE_T:
3327 XGBE_SET_SUP(lks, Autoneg);
3328 XGBE_SET_SUP(lks, Pause);
3329 XGBE_SET_SUP(lks, Asym_Pause);
3330 XGBE_SET_SUP(lks, TP);
3331 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3332 XGBE_SET_SUP(lks, 100baseT_Full);
3333 phy_data->start_mode = XGBE_MODE_SGMII_100;
3334 }
3335 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3336 XGBE_SET_SUP(lks, 1000baseT_Full);
3337 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3338 }
3339 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3340 XGBE_SET_SUP(lks, 10000baseT_Full);
3341 phy_data->start_mode = XGBE_MODE_KR;
3342 }
3343
3344 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3345 break;
3346
3347 /* 10GBase-R support */
3348 case XGBE_PORT_MODE_10GBASE_R:
3349 XGBE_SET_SUP(lks, Autoneg);
3350 XGBE_SET_SUP(lks, Pause);
3351 XGBE_SET_SUP(lks, Asym_Pause);
3352 XGBE_SET_SUP(lks, FIBRE);
3353 XGBE_SET_SUP(lks, 10000baseSR_Full);
3354 XGBE_SET_SUP(lks, 10000baseLR_Full);
3355 XGBE_SET_SUP(lks, 10000baseLRM_Full);
3356 XGBE_SET_SUP(lks, 10000baseER_Full);
3357 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3358 XGBE_SET_SUP(lks, 10000baseR_FEC);
3359 phy_data->start_mode = XGBE_MODE_SFI;
3360
3361 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3362 break;
3363
3364 /* SFP support */
3365 case XGBE_PORT_MODE_SFP:
3366 XGBE_SET_SUP(lks, Autoneg);
3367 XGBE_SET_SUP(lks, Pause);
3368 XGBE_SET_SUP(lks, Asym_Pause);
3369 XGBE_SET_SUP(lks, TP);
3370 XGBE_SET_SUP(lks, FIBRE);
3371 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3372 phy_data->start_mode = XGBE_MODE_SGMII_100;
3373 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3374 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3375 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3376 phy_data->start_mode = XGBE_MODE_SFI;
3377
3378 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3379
3380 xgbe_phy_sfp_setup(pdata);
3381 break;
3382 default:
3383 return -EINVAL;
3384 }
3385
3386 if (netif_msg_probe(pdata))
3387 dev_dbg(pdata->dev, "phy supported=0x%*pb\n",
3388 __ETHTOOL_LINK_MODE_MASK_NBITS,
3389 lks->link_modes.supported);
3390
3391 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3392 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3393 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3394 phy_data->phydev_mode);
3395 if (ret) {
3396 dev_err(pdata->dev,
3397 "mdio port/clause not compatible (%d/%u)\n",
3398 phy_data->mdio_addr, phy_data->phydev_mode);
3399 return -EINVAL;
3400 }
3401 }
3402
3403 if (phy_data->redrv && !phy_data->redrv_if) {
3404 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3405 XGBE_MDIO_MODE_CL22);
3406 if (ret) {
3407 dev_err(pdata->dev,
3408 "redriver mdio port not compatible (%u)\n",
3409 phy_data->redrv_addr);
3410 return -EINVAL;
3411 }
3412 }
3413
3414 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3415
3416 /* Register for driving external PHYs */
3417 mii = devm_mdiobus_alloc(pdata->dev);
3418 if (!mii) {
3419 dev_err(pdata->dev, "mdiobus_alloc failed\n");
3420 return -ENOMEM;
3421 }
3422
3423 mii->priv = pdata;
3424 mii->name = "amd-xgbe-mii";
3425 mii->read = xgbe_phy_mii_read;
3426 mii->write = xgbe_phy_mii_write;
3427 mii->parent = pdata->dev;
3428 mii->phy_mask = ~0;
3429 snprintf(mii->id, sizeof(mii->id), "%s", dev_name(pdata->dev));
3430 ret = mdiobus_register(mii);
3431 if (ret) {
3432 dev_err(pdata->dev, "mdiobus_register failed\n");
3433 return ret;
3434 }
3435 phy_data->mii = mii;
3436
3437 return 0;
3438 }
3439
xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if * phy_if)3440 void xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3441 {
3442 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3443
3444 phy_impl->init = xgbe_phy_init;
3445 phy_impl->exit = xgbe_phy_exit;
3446
3447 phy_impl->reset = xgbe_phy_reset;
3448 phy_impl->start = xgbe_phy_start;
3449 phy_impl->stop = xgbe_phy_stop;
3450
3451 phy_impl->link_status = xgbe_phy_link_status;
3452
3453 phy_impl->valid_speed = xgbe_phy_valid_speed;
3454
3455 phy_impl->use_mode = xgbe_phy_use_mode;
3456 phy_impl->set_mode = xgbe_phy_set_mode;
3457 phy_impl->get_mode = xgbe_phy_get_mode;
3458 phy_impl->switch_mode = xgbe_phy_switch_mode;
3459 phy_impl->cur_mode = xgbe_phy_cur_mode;
3460
3461 phy_impl->an_mode = xgbe_phy_an_mode;
3462
3463 phy_impl->an_config = xgbe_phy_an_config;
3464
3465 phy_impl->an_advertising = xgbe_phy_an_advertising;
3466
3467 phy_impl->an_outcome = xgbe_phy_an_outcome;
3468
3469 phy_impl->an_pre = xgbe_phy_an_pre;
3470 phy_impl->an_post = xgbe_phy_an_post;
3471
3472 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3473 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3474
3475 phy_impl->module_info = xgbe_phy_module_info;
3476 phy_impl->module_eeprom = xgbe_phy_module_eeprom;
3477 }
3478
