1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/slab.h>
6 #include <linux/platform_device.h>
7 #include <linux/device.h>
8 #include <linux/delay.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/kernel.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/component.h>
13 #include <sound/tlv.h>
14 #include <linux/of_gpio.h>
15 #include <linux/of.h>
16 #include <sound/jack.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <linux/regmap.h>
20 #include <sound/soc.h>
21 #include <sound/soc-dapm.h>
22 #include <linux/regulator/consumer.h>
23
24 #include "wcd-clsh-v2.h"
25 #include "wcd-mbhc-v2.h"
26 #include "wcd938x.h"
27
28 #define WCD938X_MAX_MICBIAS (4)
29 #define WCD938X_MAX_SUPPLY (4)
30 #define WCD938X_MBHC_MAX_BUTTONS (8)
31 #define TX_ADC_MAX (4)
32 #define WCD938X_TX_MAX_SWR_PORTS (5)
33
34 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
35 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
36 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
37 /* Fractional Rates */
38 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
39 SNDRV_PCM_RATE_176400)
40 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
41 SNDRV_PCM_FMTBIT_S24_LE)
42 /* Convert from vout ctl to micbias voltage in mV */
43 #define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
44 #define SWR_CLK_RATE_0P6MHZ (600000)
45 #define SWR_CLK_RATE_1P2MHZ (1200000)
46 #define SWR_CLK_RATE_2P4MHZ (2400000)
47 #define SWR_CLK_RATE_4P8MHZ (4800000)
48 #define SWR_CLK_RATE_9P6MHZ (9600000)
49 #define SWR_CLK_RATE_11P2896MHZ (1128960)
50
51 #define WCD938X_DRV_NAME "wcd938x_codec"
52 #define WCD938X_VERSION_1_0 (1)
53 #define EAR_RX_PATH_AUX (1)
54
55 #define ADC_MODE_VAL_HIFI 0x01
56 #define ADC_MODE_VAL_LO_HIF 0x02
57 #define ADC_MODE_VAL_NORMAL 0x03
58 #define ADC_MODE_VAL_LP 0x05
59 #define ADC_MODE_VAL_ULP1 0x09
60 #define ADC_MODE_VAL_ULP2 0x0B
61
62 /* Z value defined in milliohm */
63 #define WCD938X_ZDET_VAL_32 (32000)
64 #define WCD938X_ZDET_VAL_400 (400000)
65 #define WCD938X_ZDET_VAL_1200 (1200000)
66 #define WCD938X_ZDET_VAL_100K (100000000)
67 /* Z floating defined in ohms */
68 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
69 #define WCD938X_ZDET_NUM_MEASUREMENTS (900)
70 #define WCD938X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
71 #define WCD938X_MBHC_GET_X1(x) (x & 0x3FFF)
72 /* Z value compared in milliOhm */
73 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
74 #define WCD938X_MBHC_ZDET_CONST (86 * 16384)
75 #define WCD938X_MBHC_MOISTURE_RREF R_24_KOHM
76 #define WCD_MBHC_HS_V_MAX 1600
77
78 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
79 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
80 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
81 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
82 .tlv.p = (tlv_array), \
83 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
84 .put = wcd938x_ear_pa_put_gain, \
85 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
86
87 enum {
88 WCD9380 = 0,
89 WCD9385 = 5,
90 };
91
92 enum {
93 TX_HDR12 = 0,
94 TX_HDR34,
95 TX_HDR_MAX,
96 };
97
98 enum {
99 WCD_RX1,
100 WCD_RX2,
101 WCD_RX3
102 };
103
104 enum {
105 /* INTR_CTRL_INT_MASK_0 */
106 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
107 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
108 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
109 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
110 WCD938X_IRQ_MBHC_SW_DET,
111 WCD938X_IRQ_HPHR_OCP_INT,
112 WCD938X_IRQ_HPHR_CNP_INT,
113 WCD938X_IRQ_HPHL_OCP_INT,
114
115 /* INTR_CTRL_INT_MASK_1 */
116 WCD938X_IRQ_HPHL_CNP_INT,
117 WCD938X_IRQ_EAR_CNP_INT,
118 WCD938X_IRQ_EAR_SCD_INT,
119 WCD938X_IRQ_AUX_CNP_INT,
120 WCD938X_IRQ_AUX_SCD_INT,
121 WCD938X_IRQ_HPHL_PDM_WD_INT,
122 WCD938X_IRQ_HPHR_PDM_WD_INT,
123 WCD938X_IRQ_AUX_PDM_WD_INT,
124
125 /* INTR_CTRL_INT_MASK_2 */
126 WCD938X_IRQ_LDORT_SCD_INT,
127 WCD938X_IRQ_MBHC_MOISTURE_INT,
128 WCD938X_IRQ_HPHL_SURGE_DET_INT,
129 WCD938X_IRQ_HPHR_SURGE_DET_INT,
130 WCD938X_NUM_IRQS,
131 };
132
133 enum {
134 WCD_ADC1 = 0,
135 WCD_ADC2,
136 WCD_ADC3,
137 WCD_ADC4,
138 ALLOW_BUCK_DISABLE,
139 HPH_COMP_DELAY,
140 HPH_PA_DELAY,
141 AMIC2_BCS_ENABLE,
142 WCD_SUPPLIES_LPM_MODE,
143 };
144
145 enum {
146 ADC_MODE_INVALID = 0,
147 ADC_MODE_HIFI,
148 ADC_MODE_LO_HIF,
149 ADC_MODE_NORMAL,
150 ADC_MODE_LP,
151 ADC_MODE_ULP1,
152 ADC_MODE_ULP2,
153 };
154
155 enum {
156 AIF1_PB = 0,
157 AIF1_CAP,
158 NUM_CODEC_DAIS,
159 };
160
161 static u8 tx_mode_bit[] = {
162 [ADC_MODE_INVALID] = 0x00,
163 [ADC_MODE_HIFI] = 0x01,
164 [ADC_MODE_LO_HIF] = 0x02,
165 [ADC_MODE_NORMAL] = 0x04,
166 [ADC_MODE_LP] = 0x08,
167 [ADC_MODE_ULP1] = 0x10,
168 [ADC_MODE_ULP2] = 0x20,
169 };
170
171 struct wcd938x_priv {
172 struct sdw_slave *tx_sdw_dev;
173 struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
174 struct device *txdev;
175 struct device *rxdev;
176 struct device_node *rxnode, *txnode;
177 struct regmap *regmap;
178 struct mutex micb_lock;
179 /* mbhc module */
180 struct wcd_mbhc *wcd_mbhc;
181 struct wcd_mbhc_config mbhc_cfg;
182 struct wcd_mbhc_intr intr_ids;
183 struct wcd_clsh_ctrl *clsh_info;
184 struct irq_domain *virq;
185 struct regmap_irq_chip *wcd_regmap_irq_chip;
186 struct regmap_irq_chip_data *irq_chip;
187 struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
188 struct snd_soc_jack *jack;
189 unsigned long status_mask;
190 s32 micb_ref[WCD938X_MAX_MICBIAS];
191 s32 pullup_ref[WCD938X_MAX_MICBIAS];
192 u32 hph_mode;
193 u32 tx_mode[TX_ADC_MAX];
194 int flyback_cur_det_disable;
195 int ear_rx_path;
196 int variant;
197 int reset_gpio;
198 struct gpio_desc *us_euro_gpio;
199 u32 micb1_mv;
200 u32 micb2_mv;
201 u32 micb3_mv;
202 u32 micb4_mv;
203 int hphr_pdm_wd_int;
204 int hphl_pdm_wd_int;
205 int aux_pdm_wd_int;
206 bool comp1_enable;
207 bool comp2_enable;
208 bool ldoh;
209 bool bcs_dis;
210 };
211
212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
213 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
214 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
215
216 struct wcd938x_mbhc_zdet_param {
217 u16 ldo_ctl;
218 u16 noff;
219 u16 nshift;
220 u16 btn5;
221 u16 btn6;
222 u16 btn7;
223 };
224
225 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
226 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
227 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
228 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
229 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
230 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
231 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
232 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
233 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
234 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
235 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
236 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
237 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
238 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
239 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
240 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
241 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
242 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
243 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
244 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
245 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
246 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
247 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
248 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
249 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
250 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
251 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
252 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
253 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
254 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
255 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
256 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
257 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
258 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
259 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
260 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
261 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
262 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
263 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
264 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
265 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
266 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
267 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
268 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
269 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
270 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
271 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
272 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
273 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
274 };
275
276 static const struct reg_default wcd938x_defaults[] = {
277 {WCD938X_ANA_PAGE_REGISTER, 0x00},
278 {WCD938X_ANA_BIAS, 0x00},
279 {WCD938X_ANA_RX_SUPPLIES, 0x00},
280 {WCD938X_ANA_HPH, 0x0C},
281 {WCD938X_ANA_EAR, 0x00},
282 {WCD938X_ANA_EAR_COMPANDER_CTL, 0x02},
283 {WCD938X_ANA_TX_CH1, 0x20},
284 {WCD938X_ANA_TX_CH2, 0x00},
285 {WCD938X_ANA_TX_CH3, 0x20},
286 {WCD938X_ANA_TX_CH4, 0x00},
287 {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
288 {WCD938X_ANA_MICB3_DSP_EN_LOGIC, 0x00},
289 {WCD938X_ANA_MBHC_MECH, 0x39},
290 {WCD938X_ANA_MBHC_ELECT, 0x08},
291 {WCD938X_ANA_MBHC_ZDET, 0x00},
292 {WCD938X_ANA_MBHC_RESULT_1, 0x00},
293 {WCD938X_ANA_MBHC_RESULT_2, 0x00},
294 {WCD938X_ANA_MBHC_RESULT_3, 0x00},
295 {WCD938X_ANA_MBHC_BTN0, 0x00},
296 {WCD938X_ANA_MBHC_BTN1, 0x10},
297 {WCD938X_ANA_MBHC_BTN2, 0x20},
298 {WCD938X_ANA_MBHC_BTN3, 0x30},
299 {WCD938X_ANA_MBHC_BTN4, 0x40},
300 {WCD938X_ANA_MBHC_BTN5, 0x50},
301 {WCD938X_ANA_MBHC_BTN6, 0x60},
302 {WCD938X_ANA_MBHC_BTN7, 0x70},
303 {WCD938X_ANA_MICB1, 0x10},
304 {WCD938X_ANA_MICB2, 0x10},
305 {WCD938X_ANA_MICB2_RAMP, 0x00},
306 {WCD938X_ANA_MICB3, 0x10},
307 {WCD938X_ANA_MICB4, 0x10},
308 {WCD938X_BIAS_CTL, 0x2A},
309 {WCD938X_BIAS_VBG_FINE_ADJ, 0x55},
310 {WCD938X_LDOL_VDDCX_ADJUST, 0x01},
311 {WCD938X_LDOL_DISABLE_LDOL, 0x00},
312 {WCD938X_MBHC_CTL_CLK, 0x00},
313 {WCD938X_MBHC_CTL_ANA, 0x00},
314 {WCD938X_MBHC_CTL_SPARE_1, 0x00},
315 {WCD938X_MBHC_CTL_SPARE_2, 0x00},
316 {WCD938X_MBHC_CTL_BCS, 0x00},
317 {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS, 0x00},
318 {WCD938X_MBHC_TEST_CTL, 0x00},
319 {WCD938X_LDOH_MODE, 0x2B},
320 {WCD938X_LDOH_BIAS, 0x68},
321 {WCD938X_LDOH_STB_LOADS, 0x00},
322 {WCD938X_LDOH_SLOWRAMP, 0x50},
323 {WCD938X_MICB1_TEST_CTL_1, 0x1A},
324 {WCD938X_MICB1_TEST_CTL_2, 0x00},
325 {WCD938X_MICB1_TEST_CTL_3, 0xA4},
326 {WCD938X_MICB2_TEST_CTL_1, 0x1A},
327 {WCD938X_MICB2_TEST_CTL_2, 0x00},
328 {WCD938X_MICB2_TEST_CTL_3, 0x24},
329 {WCD938X_MICB3_TEST_CTL_1, 0x1A},
330 {WCD938X_MICB3_TEST_CTL_2, 0x00},
331 {WCD938X_MICB3_TEST_CTL_3, 0xA4},
332 {WCD938X_MICB4_TEST_CTL_1, 0x1A},
333 {WCD938X_MICB4_TEST_CTL_2, 0x00},
334 {WCD938X_MICB4_TEST_CTL_3, 0xA4},
335 {WCD938X_TX_COM_ADC_VCM, 0x39},
336 {WCD938X_TX_COM_BIAS_ATEST, 0xE0},
337 {WCD938X_TX_COM_SPARE1, 0x00},
338 {WCD938X_TX_COM_SPARE2, 0x00},
339 {WCD938X_TX_COM_TXFE_DIV_CTL, 0x22},
340 {WCD938X_TX_COM_TXFE_DIV_START, 0x00},
341 {WCD938X_TX_COM_SPARE3, 0x00},
342 {WCD938X_TX_COM_SPARE4, 0x00},
343 {WCD938X_TX_1_2_TEST_EN, 0xCC},
344 {WCD938X_TX_1_2_ADC_IB, 0xE9},
345 {WCD938X_TX_1_2_ATEST_REFCTL, 0x0A},
346 {WCD938X_TX_1_2_TEST_CTL, 0x38},
347 {WCD938X_TX_1_2_TEST_BLK_EN1, 0xFF},
348 {WCD938X_TX_1_2_TXFE1_CLKDIV, 0x00},
349 {WCD938X_TX_1_2_SAR2_ERR, 0x00},
350 {WCD938X_TX_1_2_SAR1_ERR, 0x00},
351 {WCD938X_TX_3_4_TEST_EN, 0xCC},
352 {WCD938X_TX_3_4_ADC_IB, 0xE9},
353 {WCD938X_TX_3_4_ATEST_REFCTL, 0x0A},
354 {WCD938X_TX_3_4_TEST_CTL, 0x38},
355 {WCD938X_TX_3_4_TEST_BLK_EN3, 0xFF},
356 {WCD938X_TX_3_4_TXFE3_CLKDIV, 0x00},
357 {WCD938X_TX_3_4_SAR4_ERR, 0x00},
358 {WCD938X_TX_3_4_SAR3_ERR, 0x00},
359 {WCD938X_TX_3_4_TEST_BLK_EN2, 0xFB},
360 {WCD938X_TX_3_4_TXFE2_CLKDIV, 0x00},
361 {WCD938X_TX_3_4_SPARE1, 0x00},
362 {WCD938X_TX_3_4_TEST_BLK_EN4, 0xFB},
363 {WCD938X_TX_3_4_TXFE4_CLKDIV, 0x00},
364 {WCD938X_TX_3_4_SPARE2, 0x00},
365 {WCD938X_CLASSH_MODE_1, 0x40},
366 {WCD938X_CLASSH_MODE_2, 0x3A},
367 {WCD938X_CLASSH_MODE_3, 0x00},
368 {WCD938X_CLASSH_CTRL_VCL_1, 0x70},
369 {WCD938X_CLASSH_CTRL_VCL_2, 0x82},
370 {WCD938X_CLASSH_CTRL_CCL_1, 0x31},
371 {WCD938X_CLASSH_CTRL_CCL_2, 0x80},
372 {WCD938X_CLASSH_CTRL_CCL_3, 0x80},
373 {WCD938X_CLASSH_CTRL_CCL_4, 0x51},
374 {WCD938X_CLASSH_CTRL_CCL_5, 0x00},
375 {WCD938X_CLASSH_BUCK_TMUX_A_D, 0x00},
376 {WCD938X_CLASSH_BUCK_SW_DRV_CNTL, 0x77},
377 {WCD938X_CLASSH_SPARE, 0x00},
378 {WCD938X_FLYBACK_EN, 0x4E},
379 {WCD938X_FLYBACK_VNEG_CTRL_1, 0x0B},
380 {WCD938X_FLYBACK_VNEG_CTRL_2, 0x45},
381 {WCD938X_FLYBACK_VNEG_CTRL_3, 0x74},
382 {WCD938X_FLYBACK_VNEG_CTRL_4, 0x7F},
383 {WCD938X_FLYBACK_VNEG_CTRL_5, 0x83},
384 {WCD938X_FLYBACK_VNEG_CTRL_6, 0x98},
385 {WCD938X_FLYBACK_VNEG_CTRL_7, 0xA9},
386 {WCD938X_FLYBACK_VNEG_CTRL_8, 0x68},
387 {WCD938X_FLYBACK_VNEG_CTRL_9, 0x64},
388 {WCD938X_FLYBACK_VNEGDAC_CTRL_1, 0xED},
389 {WCD938X_FLYBACK_VNEGDAC_CTRL_2, 0xF0},
390 {WCD938X_FLYBACK_VNEGDAC_CTRL_3, 0xA6},
391 {WCD938X_FLYBACK_CTRL_1, 0x65},
392 {WCD938X_FLYBACK_TEST_CTL, 0x00},
393 {WCD938X_RX_AUX_SW_CTL, 0x00},
394 {WCD938X_RX_PA_AUX_IN_CONN, 0x01},
395 {WCD938X_RX_TIMER_DIV, 0x32},
396 {WCD938X_RX_OCP_CTL, 0x1F},
397 {WCD938X_RX_OCP_COUNT, 0x77},
398 {WCD938X_RX_BIAS_EAR_DAC, 0xA0},
399 {WCD938X_RX_BIAS_EAR_AMP, 0xAA},
400 {WCD938X_RX_BIAS_HPH_LDO, 0xA9},
401 {WCD938X_RX_BIAS_HPH_PA, 0xAA},
402 {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8A},
403 {WCD938X_RX_BIAS_HPH_RDAC_LDO, 0x88},
404 {WCD938X_RX_BIAS_HPH_CNP1, 0x82},
405 {WCD938X_RX_BIAS_HPH_LOWPOWER, 0x82},
406 {WCD938X_RX_BIAS_AUX_DAC, 0xA0},
407 {WCD938X_RX_BIAS_AUX_AMP, 0xAA},
408 {WCD938X_RX_BIAS_VNEGDAC_BLEEDER, 0x50},
409 {WCD938X_RX_BIAS_MISC, 0x00},
410 {WCD938X_RX_BIAS_BUCK_RST, 0x08},
411 {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44},
412 {WCD938X_RX_BIAS_FLYB_ERRAMP, 0x40},
413 {WCD938X_RX_BIAS_FLYB_BUFF, 0xAA},
414 {WCD938X_RX_BIAS_FLYB_MID_RST, 0x14},
415 {WCD938X_HPH_L_STATUS, 0x04},
416 {WCD938X_HPH_R_STATUS, 0x04},
417 {WCD938X_HPH_CNP_EN, 0x80},
418 {WCD938X_HPH_CNP_WG_CTL, 0x9A},
419 {WCD938X_HPH_CNP_WG_TIME, 0x14},
420 {WCD938X_HPH_OCP_CTL, 0x28},
421 {WCD938X_HPH_AUTO_CHOP, 0x16},
422 {WCD938X_HPH_CHOP_CTL, 0x83},
423 {WCD938X_HPH_PA_CTL1, 0x46},
424 {WCD938X_HPH_PA_CTL2, 0x50},
425 {WCD938X_HPH_L_EN, 0x80},
426 {WCD938X_HPH_L_TEST, 0xE0},
427 {WCD938X_HPH_L_ATEST, 0x50},
428 {WCD938X_HPH_R_EN, 0x80},
429 {WCD938X_HPH_R_TEST, 0xE0},
430 {WCD938X_HPH_R_ATEST, 0x54},
431 {WCD938X_HPH_RDAC_CLK_CTL1, 0x99},
432 {WCD938X_HPH_RDAC_CLK_CTL2, 0x9B},
433 {WCD938X_HPH_RDAC_LDO_CTL, 0x33},
434 {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00},
435 {WCD938X_HPH_REFBUFF_UHQA_CTL, 0x68},
436 {WCD938X_HPH_REFBUFF_LP_CTL, 0x0E},
437 {WCD938X_HPH_L_DAC_CTL, 0x20},
438 {WCD938X_HPH_R_DAC_CTL, 0x20},
439 {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL, 0x55},
440 {WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0x19},
441 {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1, 0xA0},
442 {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS, 0x00},
443 {WCD938X_EAR_EAR_EN_REG, 0x22},
444 {WCD938X_EAR_EAR_PA_CON, 0x44},
445 {WCD938X_EAR_EAR_SP_CON, 0xDB},
446 {WCD938X_EAR_EAR_DAC_CON, 0x80},
447 {WCD938X_EAR_EAR_CNP_FSM_CON, 0xB2},
448 {WCD938X_EAR_TEST_CTL, 0x00},
449 {WCD938X_EAR_STATUS_REG_1, 0x00},
450 {WCD938X_EAR_STATUS_REG_2, 0x08},
451 {WCD938X_ANA_NEW_PAGE_REGISTER, 0x00},
452 {WCD938X_HPH_NEW_ANA_HPH2, 0x00},
453 {WCD938X_HPH_NEW_ANA_HPH3, 0x00},
454 {WCD938X_SLEEP_CTL, 0x16},
455 {WCD938X_SLEEP_WATCHDOG_CTL, 0x00},
456 {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00},
457 {WCD938X_MBHC_NEW_CTL_1, 0x02},
458 {WCD938X_MBHC_NEW_CTL_2, 0x05},
459 {WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0xE9},
460 {WCD938X_MBHC_NEW_ZDET_ANA_CTL, 0x0F},
461 {WCD938X_MBHC_NEW_ZDET_RAMP_CTL, 0x00},
462 {WCD938X_MBHC_NEW_FSM_STATUS, 0x00},
463 {WCD938X_MBHC_NEW_ADC_RESULT, 0x00},
464 {WCD938X_TX_NEW_AMIC_MUX_CFG, 0x00},
465 {WCD938X_AUX_AUXPA, 0x00},
466 {WCD938X_LDORXTX_MODE, 0x0C},
467 {WCD938X_LDORXTX_CONFIG, 0x10},
468 {WCD938X_DIE_CRACK_DIE_CRK_DET_EN, 0x00},
469 {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT, 0x00},
470 {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40},
471 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81},
472 {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10},
473 {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00},
474 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81},
475 {WCD938X_HPH_NEW_INT_PA_MISC1, 0x22},
476 {WCD938X_HPH_NEW_INT_PA_MISC2, 0x00},
477 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC, 0x00},
478 {WCD938X_HPH_NEW_INT_HPH_TIMER1, 0xFE},
479 {WCD938X_HPH_NEW_INT_HPH_TIMER2, 0x02},
480 {WCD938X_HPH_NEW_INT_HPH_TIMER3, 0x4E},
481 {WCD938X_HPH_NEW_INT_HPH_TIMER4, 0x54},
482 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00},
483 {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00},
484 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW, 0x90},
485 {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW, 0x90},
486 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62},
487 {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01},
488 {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11},
489 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL, 0x57},
490 {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL, 0x01},
491 {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x00},
492 {WCD938X_MBHC_NEW_INT_SPARE_2, 0x00},
493 {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON, 0xA8},
494 {WCD938X_EAR_INT_NEW_CNP_VCM_CON1, 0x42},
495 {WCD938X_EAR_INT_NEW_CNP_VCM_CON2, 0x22},
496 {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS, 0x00},
497 {WCD938X_AUX_INT_EN_REG, 0x00},
498 {WCD938X_AUX_INT_PA_CTRL, 0x06},
499 {WCD938X_AUX_INT_SP_CTRL, 0xD2},
500 {WCD938X_AUX_INT_DAC_CTRL, 0x80},
501 {WCD938X_AUX_INT_CLK_CTRL, 0x50},
502 {WCD938X_AUX_INT_TEST_CTRL, 0x00},
503 {WCD938X_AUX_INT_STATUS_REG, 0x00},
504 {WCD938X_AUX_INT_MISC, 0x00},
505 {WCD938X_LDORXTX_INT_BIAS, 0x6E},
506 {WCD938X_LDORXTX_INT_STB_LOADS_DTEST, 0x50},
507 {WCD938X_LDORXTX_INT_TEST0, 0x1C},
508 {WCD938X_LDORXTX_INT_STARTUP_TIMER, 0xFF},
509 {WCD938X_LDORXTX_INT_TEST1, 0x1F},
510 {WCD938X_LDORXTX_INT_STATUS, 0x00},
511 {WCD938X_SLEEP_INT_WATCHDOG_CTL_1, 0x0A},
512 {WCD938X_SLEEP_INT_WATCHDOG_CTL_2, 0x0A},
513 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1, 0x02},
514 {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2, 0x60},
515 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2, 0xFF},
516 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1, 0x7F},
517 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0, 0x3F},
518 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M, 0x1F},
519 {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M, 0x0F},
520 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1, 0xD7},
521 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0, 0xC8},
522 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP, 0xC6},
523 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1, 0xD5},
524 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0, 0xCA},
525 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
526 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0, 0xA5},
527 {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP, 0x13},
528 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1, 0x88},
529 {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP, 0x42},
530 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2, 0xFF},
531 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1, 0x64},
532 {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0, 0x64},
533 {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP, 0x77},
534 {WCD938X_DIGITAL_PAGE_REGISTER, 0x00},
535 {WCD938X_DIGITAL_CHIP_ID0, 0x00},
536 {WCD938X_DIGITAL_CHIP_ID1, 0x00},
537 {WCD938X_DIGITAL_CHIP_ID2, 0x0D},
538 {WCD938X_DIGITAL_CHIP_ID3, 0x01},
539 {WCD938X_DIGITAL_SWR_TX_CLK_RATE, 0x00},
540 {WCD938X_DIGITAL_CDC_RST_CTL, 0x03},
541 {WCD938X_DIGITAL_TOP_CLK_CFG, 0x00},
542 {WCD938X_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
543 {WCD938X_DIGITAL_CDC_DIG_CLK_CTL, 0xF0},
544 {WCD938X_DIGITAL_SWR_RST_EN, 0x00},
545 {WCD938X_DIGITAL_CDC_PATH_MODE, 0x55},
546 {WCD938X_DIGITAL_CDC_RX_RST, 0x00},
547 {WCD938X_DIGITAL_CDC_RX0_CTL, 0xFC},
548 {WCD938X_DIGITAL_CDC_RX1_CTL, 0xFC},
549 {WCD938X_DIGITAL_CDC_RX2_CTL, 0xFC},
550 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1, 0x00},
551 {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3, 0x00},
552 {WCD938X_DIGITAL_CDC_COMP_CTL_0, 0x00},
553 {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL, 0x1E},
554 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0, 0x00},
555 {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1, 0x01},
556 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0, 0x63},
557 {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1, 0x04},
558 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0, 0xAC},
559 {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1, 0x04},
560 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0, 0x1A},
561 {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1, 0x03},
562 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0, 0xBC},
563 {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1, 0x02},
564 {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0, 0xC7},
565 {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0, 0xF8},
566 {WCD938X_DIGITAL_CDC_HPH_DSM_C_0, 0x47},
567 {WCD938X_DIGITAL_CDC_HPH_DSM_C_1, 0x43},
568 {WCD938X_DIGITAL_CDC_HPH_DSM_C_2, 0xB1},
569 {WCD938X_DIGITAL_CDC_HPH_DSM_C_3, 0x17},
570 {WCD938X_DIGITAL_CDC_HPH_DSM_R1, 0x4D},
571 {WCD938X_DIGITAL_CDC_HPH_DSM_R2, 0x29},
572 {WCD938X_DIGITAL_CDC_HPH_DSM_R3, 0x34},
573 {WCD938X_DIGITAL_CDC_HPH_DSM_R4, 0x59},
574 {WCD938X_DIGITAL_CDC_HPH_DSM_R5, 0x66},
575 {WCD938X_DIGITAL_CDC_HPH_DSM_R6, 0x87},
576 {WCD938X_DIGITAL_CDC_HPH_DSM_R7, 0x64},
577 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0, 0x00},
578 {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1, 0x01},
579 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0, 0x96},
580 {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1, 0x09},
581 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0, 0xAB},
582 {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1, 0x05},
583 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0, 0x1C},
584 {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1, 0x02},
585 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0, 0x17},
586 {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1, 0x02},
587 {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0, 0xAA},
588 {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0, 0xE3},
589 {WCD938X_DIGITAL_CDC_AUX_DSM_C_0, 0x69},
590 {WCD938X_DIGITAL_CDC_AUX_DSM_C_1, 0x54},
591 {WCD938X_DIGITAL_CDC_AUX_DSM_C_2, 0x02},
592 {WCD938X_DIGITAL_CDC_AUX_DSM_C_3, 0x15},
593 {WCD938X_DIGITAL_CDC_AUX_DSM_R1, 0xA4},
594 {WCD938X_DIGITAL_CDC_AUX_DSM_R2, 0xB5},
595 {WCD938X_DIGITAL_CDC_AUX_DSM_R3, 0x86},
596 {WCD938X_DIGITAL_CDC_AUX_DSM_R4, 0x85},
597 {WCD938X_DIGITAL_CDC_AUX_DSM_R5, 0xAA},
598 {WCD938X_DIGITAL_CDC_AUX_DSM_R6, 0xE2},
599 {WCD938X_DIGITAL_CDC_AUX_DSM_R7, 0x62},
600 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0, 0x55},
601 {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1, 0xA9},
602 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0, 0x3D},
603 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1, 0x2E},
604 {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2, 0x01},
605 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0, 0x00},
606 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1, 0xFC},
607 {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2, 0x01},
608 {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL, 0x00},
609 {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL, 0x00},
610 {WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0x00},
611 {WCD938X_DIGITAL_CDC_SWR_CLH, 0x00},
612 {WCD938X_DIGITAL_SWR_CLH_BYP, 0x00},
613 {WCD938X_DIGITAL_CDC_TX0_CTL, 0x68},
614 {WCD938X_DIGITAL_CDC_TX1_CTL, 0x68},
615 {WCD938X_DIGITAL_CDC_TX2_CTL, 0x68},
616 {WCD938X_DIGITAL_CDC_TX_RST, 0x00},
617 {WCD938X_DIGITAL_CDC_REQ_CTL, 0x01},
618 {WCD938X_DIGITAL_CDC_RST, 0x00},
619 {WCD938X_DIGITAL_CDC_AMIC_CTL, 0x0F},
620 {WCD938X_DIGITAL_CDC_DMIC_CTL, 0x04},
621 {WCD938X_DIGITAL_CDC_DMIC1_CTL, 0x01},
622 {WCD938X_DIGITAL_CDC_DMIC2_CTL, 0x01},
623 {WCD938X_DIGITAL_CDC_DMIC3_CTL, 0x01},
624 {WCD938X_DIGITAL_CDC_DMIC4_CTL, 0x01},
625 {WCD938X_DIGITAL_EFUSE_PRG_CTL, 0x00},
626 {WCD938X_DIGITAL_EFUSE_CTL, 0x2B},
627 {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2, 0x11},
628 {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4, 0x11},
629 {WCD938X_DIGITAL_PDM_WD_CTL0, 0x00},
630 {WCD938X_DIGITAL_PDM_WD_CTL1, 0x00},
631 {WCD938X_DIGITAL_PDM_WD_CTL2, 0x00},
632 {WCD938X_DIGITAL_INTR_MODE, 0x00},
633 {WCD938X_DIGITAL_INTR_MASK_0, 0xFF},
634 {WCD938X_DIGITAL_INTR_MASK_1, 0xFF},
635 {WCD938X_DIGITAL_INTR_MASK_2, 0x3F},
636 {WCD938X_DIGITAL_INTR_STATUS_0, 0x00},
637 {WCD938X_DIGITAL_INTR_STATUS_1, 0x00},
638 {WCD938X_DIGITAL_INTR_STATUS_2, 0x00},
639 {WCD938X_DIGITAL_INTR_CLEAR_0, 0x00},
640 {WCD938X_DIGITAL_INTR_CLEAR_1, 0x00},
641 {WCD938X_DIGITAL_INTR_CLEAR_2, 0x00},
642 {WCD938X_DIGITAL_INTR_LEVEL_0, 0x00},
643 {WCD938X_DIGITAL_INTR_LEVEL_1, 0x00},
644 {WCD938X_DIGITAL_INTR_LEVEL_2, 0x00},
645 {WCD938X_DIGITAL_INTR_SET_0, 0x00},
646 {WCD938X_DIGITAL_INTR_SET_1, 0x00},
647 {WCD938X_DIGITAL_INTR_SET_2, 0x00},
648 {WCD938X_DIGITAL_INTR_TEST_0, 0x00},
649 {WCD938X_DIGITAL_INTR_TEST_1, 0x00},
650 {WCD938X_DIGITAL_INTR_TEST_2, 0x00},
651 {WCD938X_DIGITAL_TX_MODE_DBG_EN, 0x00},
652 {WCD938X_DIGITAL_TX_MODE_DBG_0_1, 0x00},
653 {WCD938X_DIGITAL_TX_MODE_DBG_2_3, 0x00},
654 {WCD938X_DIGITAL_LB_IN_SEL_CTL, 0x00},
655 {WCD938X_DIGITAL_LOOP_BACK_MODE, 0x00},
656 {WCD938X_DIGITAL_SWR_DAC_TEST, 0x00},
657 {WCD938X_DIGITAL_SWR_HM_TEST_RX_0, 0x40},
658 {WCD938X_DIGITAL_SWR_HM_TEST_TX_0, 0x40},
659 {WCD938X_DIGITAL_SWR_HM_TEST_RX_1, 0x00},
660 {WCD938X_DIGITAL_SWR_HM_TEST_TX_1, 0x00},
661 {WCD938X_DIGITAL_SWR_HM_TEST_TX_2, 0x00},
662 {WCD938X_DIGITAL_SWR_HM_TEST_0, 0x00},
663 {WCD938X_DIGITAL_SWR_HM_TEST_1, 0x00},
664 {WCD938X_DIGITAL_PAD_CTL_SWR_0, 0x8F},
665 {WCD938X_DIGITAL_PAD_CTL_SWR_1, 0x06},
666 {WCD938X_DIGITAL_I2C_CTL, 0x00},
667 {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE, 0x00},
668 {WCD938X_DIGITAL_EFUSE_TEST_CTL_0, 0x00},
669 {WCD938X_DIGITAL_EFUSE_TEST_CTL_1, 0x00},
670 {WCD938X_DIGITAL_EFUSE_T_DATA_0, 0x00},
671 {WCD938X_DIGITAL_EFUSE_T_DATA_1, 0x00},
672 {WCD938X_DIGITAL_PAD_CTL_PDM_RX0, 0xF1},
673 {WCD938X_DIGITAL_PAD_CTL_PDM_RX1, 0xF1},
674 {WCD938X_DIGITAL_PAD_CTL_PDM_TX0, 0xF1},
675 {WCD938X_DIGITAL_PAD_CTL_PDM_TX1, 0xF1},
676 {WCD938X_DIGITAL_PAD_CTL_PDM_TX2, 0xF1},
677 {WCD938X_DIGITAL_PAD_INP_DIS_0, 0x00},
678 {WCD938X_DIGITAL_PAD_INP_DIS_1, 0x00},
679 {WCD938X_DIGITAL_DRIVE_STRENGTH_0, 0x00},
680 {WCD938X_DIGITAL_DRIVE_STRENGTH_1, 0x00},
681 {WCD938X_DIGITAL_DRIVE_STRENGTH_2, 0x00},
682 {WCD938X_DIGITAL_RX_DATA_EDGE_CTL, 0x1F},
683 {WCD938X_DIGITAL_TX_DATA_EDGE_CTL, 0x80},
684 {WCD938X_DIGITAL_GPIO_MODE, 0x00},
685 {WCD938X_DIGITAL_PIN_CTL_OE, 0x00},
686 {WCD938X_DIGITAL_PIN_CTL_DATA_0, 0x00},
687 {WCD938X_DIGITAL_PIN_CTL_DATA_1, 0x00},
688 {WCD938X_DIGITAL_PIN_STATUS_0, 0x00},
689 {WCD938X_DIGITAL_PIN_STATUS_1, 0x00},
690 {WCD938X_DIGITAL_DIG_DEBUG_CTL, 0x00},
691 {WCD938X_DIGITAL_DIG_DEBUG_EN, 0x00},
692 {WCD938X_DIGITAL_ANA_CSR_DBG_ADD, 0x00},
693 {WCD938X_DIGITAL_ANA_CSR_DBG_CTL, 0x48},
694 {WCD938X_DIGITAL_SSP_DBG, 0x00},
695 {WCD938X_DIGITAL_MODE_STATUS_0, 0x00},
696 {WCD938X_DIGITAL_MODE_STATUS_1, 0x00},
697 {WCD938X_DIGITAL_SPARE_0, 0x00},
698 {WCD938X_DIGITAL_SPARE_1, 0x00},
699 {WCD938X_DIGITAL_SPARE_2, 0x00},
700 {WCD938X_DIGITAL_EFUSE_REG_0, 0x00},
701 {WCD938X_DIGITAL_EFUSE_REG_1, 0xFF},
702 {WCD938X_DIGITAL_EFUSE_REG_2, 0xFF},
703 {WCD938X_DIGITAL_EFUSE_REG_3, 0xFF},
704 {WCD938X_DIGITAL_EFUSE_REG_4, 0xFF},
705 {WCD938X_DIGITAL_EFUSE_REG_5, 0xFF},
706 {WCD938X_DIGITAL_EFUSE_REG_6, 0xFF},
707 {WCD938X_DIGITAL_EFUSE_REG_7, 0xFF},
708 {WCD938X_DIGITAL_EFUSE_REG_8, 0xFF},
709 {WCD938X_DIGITAL_EFUSE_REG_9, 0xFF},
710 {WCD938X_DIGITAL_EFUSE_REG_10, 0xFF},
711 {WCD938X_DIGITAL_EFUSE_REG_11, 0xFF},
712 {WCD938X_DIGITAL_EFUSE_REG_12, 0xFF},
713 {WCD938X_DIGITAL_EFUSE_REG_13, 0xFF},
714 {WCD938X_DIGITAL_EFUSE_REG_14, 0xFF},
715 {WCD938X_DIGITAL_EFUSE_REG_15, 0xFF},
716 {WCD938X_DIGITAL_EFUSE_REG_16, 0xFF},
717 {WCD938X_DIGITAL_EFUSE_REG_17, 0xFF},
718 {WCD938X_DIGITAL_EFUSE_REG_18, 0xFF},
719 {WCD938X_DIGITAL_EFUSE_REG_19, 0xFF},
720 {WCD938X_DIGITAL_EFUSE_REG_20, 0x0E},
721 {WCD938X_DIGITAL_EFUSE_REG_21, 0x00},
722 {WCD938X_DIGITAL_EFUSE_REG_22, 0x00},
723 {WCD938X_DIGITAL_EFUSE_REG_23, 0xF8},
724 {WCD938X_DIGITAL_EFUSE_REG_24, 0x16},
725 {WCD938X_DIGITAL_EFUSE_REG_25, 0x00},
726 {WCD938X_DIGITAL_EFUSE_REG_26, 0x00},
727 {WCD938X_DIGITAL_EFUSE_REG_27, 0x00},
728 {WCD938X_DIGITAL_EFUSE_REG_28, 0x00},
729 {WCD938X_DIGITAL_EFUSE_REG_29, 0x00},
730 {WCD938X_DIGITAL_EFUSE_REG_30, 0x00},
731 {WCD938X_DIGITAL_EFUSE_REG_31, 0x00},
732 {WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0x88},
733 {WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0x88},
734 {WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0x88},
735 {WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0x88},
736 {WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0x88},
737 {WCD938X_DIGITAL_DEM_BYPASS_DATA0, 0x55},
738 {WCD938X_DIGITAL_DEM_BYPASS_DATA1, 0x55},
739 {WCD938X_DIGITAL_DEM_BYPASS_DATA2, 0x55},
740 {WCD938X_DIGITAL_DEM_BYPASS_DATA3, 0x01},
741 };
742
wcd938x_rdwr_register(struct device * dev,unsigned int reg)743 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
744 {
745 switch (reg) {
746 case WCD938X_ANA_PAGE_REGISTER:
747 case WCD938X_ANA_BIAS:
748 case WCD938X_ANA_RX_SUPPLIES:
749 case WCD938X_ANA_HPH:
750 case WCD938X_ANA_EAR:
751 case WCD938X_ANA_EAR_COMPANDER_CTL:
752 case WCD938X_ANA_TX_CH1:
753 case WCD938X_ANA_TX_CH2:
754 case WCD938X_ANA_TX_CH3:
755 case WCD938X_ANA_TX_CH4:
756 case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
757 case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
758 case WCD938X_ANA_MBHC_MECH:
759 case WCD938X_ANA_MBHC_ELECT:
760 case WCD938X_ANA_MBHC_ZDET:
761 case WCD938X_ANA_MBHC_BTN0:
762 case WCD938X_ANA_MBHC_BTN1:
763 case WCD938X_ANA_MBHC_BTN2:
764 case WCD938X_ANA_MBHC_BTN3:
765 case WCD938X_ANA_MBHC_BTN4:
766 case WCD938X_ANA_MBHC_BTN5:
767 case WCD938X_ANA_MBHC_BTN6:
768 case WCD938X_ANA_MBHC_BTN7:
769 case WCD938X_ANA_MICB1:
770 case WCD938X_ANA_MICB2:
771 case WCD938X_ANA_MICB2_RAMP:
772 case WCD938X_ANA_MICB3:
773 case WCD938X_ANA_MICB4:
774 case WCD938X_BIAS_CTL:
775 case WCD938X_BIAS_VBG_FINE_ADJ:
776 case WCD938X_LDOL_VDDCX_ADJUST:
777 case WCD938X_LDOL_DISABLE_LDOL:
778 case WCD938X_MBHC_CTL_CLK:
779 case WCD938X_MBHC_CTL_ANA:
780 case WCD938X_MBHC_CTL_SPARE_1:
781 case WCD938X_MBHC_CTL_SPARE_2:
782 case WCD938X_MBHC_CTL_BCS:
783 case WCD938X_MBHC_TEST_CTL:
784 case WCD938X_LDOH_MODE:
785 case WCD938X_LDOH_BIAS:
786 case WCD938X_LDOH_STB_LOADS:
787 case WCD938X_LDOH_SLOWRAMP:
788 case WCD938X_MICB1_TEST_CTL_1:
789 case WCD938X_MICB1_TEST_CTL_2:
790 case WCD938X_MICB1_TEST_CTL_3:
791 case WCD938X_MICB2_TEST_CTL_1:
792 case WCD938X_MICB2_TEST_CTL_2:
793 case WCD938X_MICB2_TEST_CTL_3:
794 case WCD938X_MICB3_TEST_CTL_1:
795 case WCD938X_MICB3_TEST_CTL_2:
796 case WCD938X_MICB3_TEST_CTL_3:
797 case WCD938X_MICB4_TEST_CTL_1:
798 case WCD938X_MICB4_TEST_CTL_2:
799 case WCD938X_MICB4_TEST_CTL_3:
800 case WCD938X_TX_COM_ADC_VCM:
801 case WCD938X_TX_COM_BIAS_ATEST:
802 case WCD938X_TX_COM_SPARE1:
803 case WCD938X_TX_COM_SPARE2:
804 case WCD938X_TX_COM_TXFE_DIV_CTL:
805 case WCD938X_TX_COM_TXFE_DIV_START:
806 case WCD938X_TX_COM_SPARE3:
807 case WCD938X_TX_COM_SPARE4:
808 case WCD938X_TX_1_2_TEST_EN:
809 case WCD938X_TX_1_2_ADC_IB:
810 case WCD938X_TX_1_2_ATEST_REFCTL:
811 case WCD938X_TX_1_2_TEST_CTL:
812 case WCD938X_TX_1_2_TEST_BLK_EN1:
813 case WCD938X_TX_1_2_TXFE1_CLKDIV:
814 case WCD938X_TX_3_4_TEST_EN:
815 case WCD938X_TX_3_4_ADC_IB:
816 case WCD938X_TX_3_4_ATEST_REFCTL:
817 case WCD938X_TX_3_4_TEST_CTL:
818 case WCD938X_TX_3_4_TEST_BLK_EN3:
819 case WCD938X_TX_3_4_TXFE3_CLKDIV:
820 case WCD938X_TX_3_4_TEST_BLK_EN2:
821 case WCD938X_TX_3_4_TXFE2_CLKDIV:
822 case WCD938X_TX_3_4_SPARE1:
823 case WCD938X_TX_3_4_TEST_BLK_EN4:
824 case WCD938X_TX_3_4_TXFE4_CLKDIV:
825 case WCD938X_TX_3_4_SPARE2:
826 case WCD938X_CLASSH_MODE_1:
827 case WCD938X_CLASSH_MODE_2:
828 case WCD938X_CLASSH_MODE_3:
829 case WCD938X_CLASSH_CTRL_VCL_1:
830 case WCD938X_CLASSH_CTRL_VCL_2:
831 case WCD938X_CLASSH_CTRL_CCL_1:
832 case WCD938X_CLASSH_CTRL_CCL_2:
833 case WCD938X_CLASSH_CTRL_CCL_3:
834 case WCD938X_CLASSH_CTRL_CCL_4:
835 case WCD938X_CLASSH_CTRL_CCL_5:
836 case WCD938X_CLASSH_BUCK_TMUX_A_D:
837 case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
838 case WCD938X_CLASSH_SPARE:
839 case WCD938X_FLYBACK_EN:
840 case WCD938X_FLYBACK_VNEG_CTRL_1:
841 case WCD938X_FLYBACK_VNEG_CTRL_2:
842 case WCD938X_FLYBACK_VNEG_CTRL_3:
843 case WCD938X_FLYBACK_VNEG_CTRL_4:
844 case WCD938X_FLYBACK_VNEG_CTRL_5:
845 case WCD938X_FLYBACK_VNEG_CTRL_6:
846 case WCD938X_FLYBACK_VNEG_CTRL_7:
847 case WCD938X_FLYBACK_VNEG_CTRL_8:
848 case WCD938X_FLYBACK_VNEG_CTRL_9:
849 case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
850 case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
851 case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
852 case WCD938X_FLYBACK_CTRL_1:
853 case WCD938X_FLYBACK_TEST_CTL:
854 case WCD938X_RX_AUX_SW_CTL:
855 case WCD938X_RX_PA_AUX_IN_CONN:
856 case WCD938X_RX_TIMER_DIV:
857 case WCD938X_RX_OCP_CTL:
858 case WCD938X_RX_OCP_COUNT:
859 case WCD938X_RX_BIAS_EAR_DAC:
860 case WCD938X_RX_BIAS_EAR_AMP:
861 case WCD938X_RX_BIAS_HPH_LDO:
862 case WCD938X_RX_BIAS_HPH_PA:
863 case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
864 case WCD938X_RX_BIAS_HPH_RDAC_LDO:
865 case WCD938X_RX_BIAS_HPH_CNP1:
866 case WCD938X_RX_BIAS_HPH_LOWPOWER:
867 case WCD938X_RX_BIAS_AUX_DAC:
868 case WCD938X_RX_BIAS_AUX_AMP:
869 case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
870 case WCD938X_RX_BIAS_MISC:
871 case WCD938X_RX_BIAS_BUCK_RST:
872 case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
873 case WCD938X_RX_BIAS_FLYB_ERRAMP:
874 case WCD938X_RX_BIAS_FLYB_BUFF:
875 case WCD938X_RX_BIAS_FLYB_MID_RST:
876 case WCD938X_HPH_CNP_EN:
877 case WCD938X_HPH_CNP_WG_CTL:
878 case WCD938X_HPH_CNP_WG_TIME:
879 case WCD938X_HPH_OCP_CTL:
880 case WCD938X_HPH_AUTO_CHOP:
881 case WCD938X_HPH_CHOP_CTL:
882 case WCD938X_HPH_PA_CTL1:
883 case WCD938X_HPH_PA_CTL2:
884 case WCD938X_HPH_L_EN:
885 case WCD938X_HPH_L_TEST:
886 case WCD938X_HPH_L_ATEST:
887 case WCD938X_HPH_R_EN:
888 case WCD938X_HPH_R_TEST:
889 case WCD938X_HPH_R_ATEST:
890 case WCD938X_HPH_RDAC_CLK_CTL1:
891 case WCD938X_HPH_RDAC_CLK_CTL2:
892 case WCD938X_HPH_RDAC_LDO_CTL:
893 case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
894 case WCD938X_HPH_REFBUFF_UHQA_CTL:
895 case WCD938X_HPH_REFBUFF_LP_CTL:
896 case WCD938X_HPH_L_DAC_CTL:
897 case WCD938X_HPH_R_DAC_CTL:
898 case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
899 case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
900 case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
901 case WCD938X_EAR_EAR_EN_REG:
902 case WCD938X_EAR_EAR_PA_CON:
903 case WCD938X_EAR_EAR_SP_CON:
904 case WCD938X_EAR_EAR_DAC_CON:
905 case WCD938X_EAR_EAR_CNP_FSM_CON:
906 case WCD938X_EAR_TEST_CTL:
907 case WCD938X_ANA_NEW_PAGE_REGISTER:
908 case WCD938X_HPH_NEW_ANA_HPH2:
909 case WCD938X_HPH_NEW_ANA_HPH3:
910 case WCD938X_SLEEP_CTL:
911 case WCD938X_SLEEP_WATCHDOG_CTL:
912 case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
913 case WCD938X_MBHC_NEW_CTL_1:
914 case WCD938X_MBHC_NEW_CTL_2:
915 case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
916 case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
917 case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
918 case WCD938X_TX_NEW_AMIC_MUX_CFG:
919 case WCD938X_AUX_AUXPA:
920 case WCD938X_LDORXTX_MODE:
921 case WCD938X_LDORXTX_CONFIG:
922 case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
923 case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
924 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
925 case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
926 case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
927 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
928 case WCD938X_HPH_NEW_INT_PA_MISC1:
929 case WCD938X_HPH_NEW_INT_PA_MISC2:
930 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
931 case WCD938X_HPH_NEW_INT_HPH_TIMER1:
932 case WCD938X_HPH_NEW_INT_HPH_TIMER2:
933 case WCD938X_HPH_NEW_INT_HPH_TIMER3:
934 case WCD938X_HPH_NEW_INT_HPH_TIMER4:
935 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
936 case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
937 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
938 case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
939 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
940 case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
941 case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
942 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
943 case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
944 case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
945 case WCD938X_MBHC_NEW_INT_SPARE_2:
946 case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
947 case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
948 case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
949 case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
950 case WCD938X_AUX_INT_EN_REG:
951 case WCD938X_AUX_INT_PA_CTRL:
952 case WCD938X_AUX_INT_SP_CTRL:
953 case WCD938X_AUX_INT_DAC_CTRL:
954 case WCD938X_AUX_INT_CLK_CTRL:
955 case WCD938X_AUX_INT_TEST_CTRL:
956 case WCD938X_AUX_INT_MISC:
957 case WCD938X_LDORXTX_INT_BIAS:
958 case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
959 case WCD938X_LDORXTX_INT_TEST0:
960 case WCD938X_LDORXTX_INT_STARTUP_TIMER:
961 case WCD938X_LDORXTX_INT_TEST1:
962 case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
963 case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
964 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
965 case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
966 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
967 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
968 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
969 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
970 case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
971 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
972 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
973 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
974 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
975 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
976 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
977 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
978 case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
979 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
980 case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
981 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
982 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
983 case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
984 case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
985 case WCD938X_DIGITAL_PAGE_REGISTER:
986 case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
987 case WCD938X_DIGITAL_CDC_RST_CTL:
988 case WCD938X_DIGITAL_TOP_CLK_CFG:
989 case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
990 case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
991 case WCD938X_DIGITAL_SWR_RST_EN:
992 case WCD938X_DIGITAL_CDC_PATH_MODE:
993 case WCD938X_DIGITAL_CDC_RX_RST:
994 case WCD938X_DIGITAL_CDC_RX0_CTL:
995 case WCD938X_DIGITAL_CDC_RX1_CTL:
996 case WCD938X_DIGITAL_CDC_RX2_CTL:
997 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
998 case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
999 case WCD938X_DIGITAL_CDC_COMP_CTL_0:
1000 case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
1001 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
1002 case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
1003 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
1004 case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
1005 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
1006 case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
1007 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
1008 case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
1009 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
1010 case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
1011 case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
1012 case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
1013 case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
1014 case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
1015 case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
1016 case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
1017 case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
1018 case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
1019 case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
1020 case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
1021 case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
1022 case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
1023 case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
1024 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
1025 case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
1026 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
1027 case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
1028 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
1029 case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
1030 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
1031 case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
1032 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
1033 case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
1034 case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
1035 case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
1036 case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
1037 case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
1038 case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
1039 case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
1040 case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
1041 case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
1042 case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
1043 case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
1044 case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
1045 case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
1046 case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
1047 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
1048 case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
1049 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
1050 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
1051 case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
1052 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
1053 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
1054 case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
1055 case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
1056 case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
1057 case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
1058 case WCD938X_DIGITAL_CDC_SWR_CLH:
1059 case WCD938X_DIGITAL_SWR_CLH_BYP:
1060 case WCD938X_DIGITAL_CDC_TX0_CTL:
1061 case WCD938X_DIGITAL_CDC_TX1_CTL:
1062 case WCD938X_DIGITAL_CDC_TX2_CTL:
1063 case WCD938X_DIGITAL_CDC_TX_RST:
1064 case WCD938X_DIGITAL_CDC_REQ_CTL:
1065 case WCD938X_DIGITAL_CDC_RST:
1066 case WCD938X_DIGITAL_CDC_AMIC_CTL:
1067 case WCD938X_DIGITAL_CDC_DMIC_CTL:
1068 case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1069 case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1070 case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1071 case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1072 case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1073 case WCD938X_DIGITAL_EFUSE_CTL:
1074 case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1075 case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1076 case WCD938X_DIGITAL_PDM_WD_CTL0:
1077 case WCD938X_DIGITAL_PDM_WD_CTL1:
1078 case WCD938X_DIGITAL_PDM_WD_CTL2:
1079 case WCD938X_DIGITAL_INTR_MODE:
1080 case WCD938X_DIGITAL_INTR_MASK_0:
1081 case WCD938X_DIGITAL_INTR_MASK_1:
1082 case WCD938X_DIGITAL_INTR_MASK_2:
1083 case WCD938X_DIGITAL_INTR_CLEAR_0:
1084 case WCD938X_DIGITAL_INTR_CLEAR_1:
1085 case WCD938X_DIGITAL_INTR_CLEAR_2:
1086 case WCD938X_DIGITAL_INTR_LEVEL_0:
1087 case WCD938X_DIGITAL_INTR_LEVEL_1:
1088 case WCD938X_DIGITAL_INTR_LEVEL_2:
1089 case WCD938X_DIGITAL_INTR_SET_0:
1090 case WCD938X_DIGITAL_INTR_SET_1:
1091 case WCD938X_DIGITAL_INTR_SET_2:
1092 case WCD938X_DIGITAL_INTR_TEST_0:
1093 case WCD938X_DIGITAL_INTR_TEST_1:
1094 case WCD938X_DIGITAL_INTR_TEST_2:
1095 case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1096 case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1097 case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1098 case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1099 case WCD938X_DIGITAL_LOOP_BACK_MODE:
1100 case WCD938X_DIGITAL_SWR_DAC_TEST:
1101 case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1102 case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1103 case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1104 case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1105 case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1106 case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1107 case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1108 case WCD938X_DIGITAL_I2C_CTL:
1109 case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1110 case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1111 case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1112 case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1113 case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1114 case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1115 case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1116 case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1117 case WCD938X_DIGITAL_PAD_INP_DIS_0:
1118 case WCD938X_DIGITAL_PAD_INP_DIS_1:
1119 case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1120 case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1121 case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1122 case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1123 case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1124 case WCD938X_DIGITAL_GPIO_MODE:
1125 case WCD938X_DIGITAL_PIN_CTL_OE:
1126 case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1127 case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1128 case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1129 case WCD938X_DIGITAL_DIG_DEBUG_EN:
1130 case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1131 case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1132 case WCD938X_DIGITAL_SSP_DBG:
1133 case WCD938X_DIGITAL_SPARE_0:
1134 case WCD938X_DIGITAL_SPARE_1:
1135 case WCD938X_DIGITAL_SPARE_2:
1136 case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1137 case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1138 case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1139 case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1140 case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1141 case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1142 case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1143 case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1144 case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1145 return true;
1146 }
1147
1148 return false;
1149 }
1150
wcd938x_readonly_register(struct device * dev,unsigned int reg)1151 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1152 {
1153 switch (reg) {
1154 case WCD938X_ANA_MBHC_RESULT_1:
1155 case WCD938X_ANA_MBHC_RESULT_2:
1156 case WCD938X_ANA_MBHC_RESULT_3:
1157 case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1158 case WCD938X_TX_1_2_SAR2_ERR:
1159 case WCD938X_TX_1_2_SAR1_ERR:
1160 case WCD938X_TX_3_4_SAR4_ERR:
1161 case WCD938X_TX_3_4_SAR3_ERR:
1162 case WCD938X_HPH_L_STATUS:
1163 case WCD938X_HPH_R_STATUS:
1164 case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1165 case WCD938X_EAR_STATUS_REG_1:
1166 case WCD938X_EAR_STATUS_REG_2:
1167 case WCD938X_MBHC_NEW_FSM_STATUS:
1168 case WCD938X_MBHC_NEW_ADC_RESULT:
1169 case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1170 case WCD938X_AUX_INT_STATUS_REG:
1171 case WCD938X_LDORXTX_INT_STATUS:
1172 case WCD938X_DIGITAL_CHIP_ID0:
1173 case WCD938X_DIGITAL_CHIP_ID1:
1174 case WCD938X_DIGITAL_CHIP_ID2:
1175 case WCD938X_DIGITAL_CHIP_ID3:
1176 case WCD938X_DIGITAL_INTR_STATUS_0:
1177 case WCD938X_DIGITAL_INTR_STATUS_1:
1178 case WCD938X_DIGITAL_INTR_STATUS_2:
1179 case WCD938X_DIGITAL_INTR_CLEAR_0:
1180 case WCD938X_DIGITAL_INTR_CLEAR_1:
1181 case WCD938X_DIGITAL_INTR_CLEAR_2:
1182 case WCD938X_DIGITAL_SWR_HM_TEST_0:
1183 case WCD938X_DIGITAL_SWR_HM_TEST_1:
1184 case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1185 case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1186 case WCD938X_DIGITAL_PIN_STATUS_0:
1187 case WCD938X_DIGITAL_PIN_STATUS_1:
1188 case WCD938X_DIGITAL_MODE_STATUS_0:
1189 case WCD938X_DIGITAL_MODE_STATUS_1:
1190 case WCD938X_DIGITAL_EFUSE_REG_0:
1191 case WCD938X_DIGITAL_EFUSE_REG_1:
1192 case WCD938X_DIGITAL_EFUSE_REG_2:
1193 case WCD938X_DIGITAL_EFUSE_REG_3:
1194 case WCD938X_DIGITAL_EFUSE_REG_4:
1195 case WCD938X_DIGITAL_EFUSE_REG_5:
1196 case WCD938X_DIGITAL_EFUSE_REG_6:
1197 case WCD938X_DIGITAL_EFUSE_REG_7:
1198 case WCD938X_DIGITAL_EFUSE_REG_8:
1199 case WCD938X_DIGITAL_EFUSE_REG_9:
1200 case WCD938X_DIGITAL_EFUSE_REG_10:
1201 case WCD938X_DIGITAL_EFUSE_REG_11:
1202 case WCD938X_DIGITAL_EFUSE_REG_12:
1203 case WCD938X_DIGITAL_EFUSE_REG_13:
1204 case WCD938X_DIGITAL_EFUSE_REG_14:
1205 case WCD938X_DIGITAL_EFUSE_REG_15:
1206 case WCD938X_DIGITAL_EFUSE_REG_16:
1207 case WCD938X_DIGITAL_EFUSE_REG_17:
1208 case WCD938X_DIGITAL_EFUSE_REG_18:
1209 case WCD938X_DIGITAL_EFUSE_REG_19:
1210 case WCD938X_DIGITAL_EFUSE_REG_20:
1211 case WCD938X_DIGITAL_EFUSE_REG_21:
1212 case WCD938X_DIGITAL_EFUSE_REG_22:
1213 case WCD938X_DIGITAL_EFUSE_REG_23:
1214 case WCD938X_DIGITAL_EFUSE_REG_24:
1215 case WCD938X_DIGITAL_EFUSE_REG_25:
1216 case WCD938X_DIGITAL_EFUSE_REG_26:
1217 case WCD938X_DIGITAL_EFUSE_REG_27:
1218 case WCD938X_DIGITAL_EFUSE_REG_28:
1219 case WCD938X_DIGITAL_EFUSE_REG_29:
1220 case WCD938X_DIGITAL_EFUSE_REG_30:
1221 case WCD938X_DIGITAL_EFUSE_REG_31:
1222 return true;
1223 }
1224 return false;
1225 }
1226
wcd938x_readable_register(struct device * dev,unsigned int reg)1227 static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1228 {
1229 bool ret;
1230
1231 ret = wcd938x_readonly_register(dev, reg);
1232 if (!ret)
1233 return wcd938x_rdwr_register(dev, reg);
1234
1235 return ret;
1236 }
1237
wcd938x_writeable_register(struct device * dev,unsigned int reg)1238 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1239 {
1240 return wcd938x_rdwr_register(dev, reg);
1241 }
1242
wcd938x_volatile_register(struct device * dev,unsigned int reg)1243 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1244 {
1245 if (reg <= WCD938X_BASE_ADDRESS)
1246 return false;
1247
1248 if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1249 return true;
1250
1251 if (wcd938x_readonly_register(dev, reg))
1252 return true;
1253
1254 return false;
1255 }
1256
1257 static struct regmap_config wcd938x_regmap_config = {
1258 .name = "wcd938x_csr",
1259 .reg_bits = 32,
1260 .val_bits = 8,
1261 .cache_type = REGCACHE_RBTREE,
1262 .reg_defaults = wcd938x_defaults,
1263 .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1264 .max_register = WCD938X_MAX_REGISTER,
1265 .readable_reg = wcd938x_readable_register,
1266 .writeable_reg = wcd938x_writeable_register,
1267 .volatile_reg = wcd938x_volatile_register,
1268 .can_multi_write = true,
1269 };
1270
1271 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1272 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1273 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1274 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1275 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1276 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1277 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1278 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1279 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1280 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1281 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1282 REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1283 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1284 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1285 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1286 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1287 REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1288 REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1289 REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1290 REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1291 REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1292 };
1293
1294 static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1295 .name = "wcd938x",
1296 .irqs = wcd938x_irqs,
1297 .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1298 .num_regs = 3,
1299 .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1300 .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1301 .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1302 .use_ack = 1,
1303 .runtime_pm = true,
1304 .irq_drv_data = NULL,
1305 };
1306
wcd938x_get_clk_rate(int mode)1307 static int wcd938x_get_clk_rate(int mode)
1308 {
1309 int rate;
1310
1311 switch (mode) {
1312 case ADC_MODE_ULP2:
1313 rate = SWR_CLK_RATE_0P6MHZ;
1314 break;
1315 case ADC_MODE_ULP1:
1316 rate = SWR_CLK_RATE_1P2MHZ;
1317 break;
1318 case ADC_MODE_LP:
1319 rate = SWR_CLK_RATE_4P8MHZ;
1320 break;
1321 case ADC_MODE_NORMAL:
1322 case ADC_MODE_LO_HIF:
1323 case ADC_MODE_HIFI:
1324 case ADC_MODE_INVALID:
1325 default:
1326 rate = SWR_CLK_RATE_9P6MHZ;
1327 break;
1328 }
1329
1330 return rate;
1331 }
1332
wcd938x_set_swr_clk_rate(struct snd_soc_component * component,int rate,int bank)1333 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
1334 {
1335 u8 mask = (bank ? 0xF0 : 0x0F);
1336 u8 val = 0;
1337
1338 switch (rate) {
1339 case SWR_CLK_RATE_0P6MHZ:
1340 val = (bank ? 0x60 : 0x06);
1341 break;
1342 case SWR_CLK_RATE_1P2MHZ:
1343 val = (bank ? 0x50 : 0x05);
1344 break;
1345 case SWR_CLK_RATE_2P4MHZ:
1346 val = (bank ? 0x30 : 0x03);
1347 break;
1348 case SWR_CLK_RATE_4P8MHZ:
1349 val = (bank ? 0x10 : 0x01);
1350 break;
1351 case SWR_CLK_RATE_9P6MHZ:
1352 default:
1353 val = 0x00;
1354 break;
1355 }
1356 snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
1357 mask, val);
1358
1359 return 0;
1360 }
1361
wcd938x_io_init(struct wcd938x_priv * wcd938x)1362 static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1363 {
1364 struct regmap *rm = wcd938x->regmap;
1365
1366 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1367 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1368 /* 1 msec delay as per HW requirement */
1369 usleep_range(1000, 1010);
1370 regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1371 /* 1 msec delay as per HW requirement */
1372 usleep_range(1000, 1010);
1373 regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1374 regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1375 0xF0, 0x80);
1376 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1377 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1378 /* 10 msec delay as per HW requirement */
1379 usleep_range(10000, 10010);
1380
1381 regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1382 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1383 0xF0, 0x00);
1384 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1385 0x1F, 0x15);
1386 regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1387 0x1F, 0x15);
1388 regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1389 0xC0, 0x80);
1390 regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1391 0x02, 0x02);
1392
1393 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1394 0xFF, 0x14);
1395 regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1396 0x1F, 0x08);
1397
1398 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1399 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1400 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1401 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1402 regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1403
1404 /* Set Noise Filter Resistor value */
1405 regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1406 regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1407 regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1408 regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1409
1410 regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1411 regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1412
1413 return 0;
1414
1415 }
1416
wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info * ch_info,struct sdw_port_config * port_config,u8 enable)1417 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1418 struct sdw_port_config *port_config,
1419 u8 enable)
1420 {
1421 u8 ch_mask, port_num;
1422
1423 port_num = ch_info->port_num;
1424 ch_mask = ch_info->ch_mask;
1425
1426 port_config->num = port_num;
1427
1428 if (enable)
1429 port_config->ch_mask |= ch_mask;
1430 else
1431 port_config->ch_mask &= ~ch_mask;
1432
1433 return 0;
1434 }
1435
wcd938x_connect_port(struct wcd938x_sdw_priv * wcd,u8 port_num,u8 ch_id,u8 enable)1436 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
1437 {
1438 return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1439 &wcd->port_config[port_num - 1],
1440 enable);
1441 }
1442
wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1443 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1444 struct snd_kcontrol *kcontrol,
1445 int event)
1446 {
1447 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1448
1449 switch (event) {
1450 case SND_SOC_DAPM_PRE_PMU:
1451 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1452 WCD938X_ANA_RX_CLK_EN_MASK, 1);
1453 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1454 WCD938X_RX_BIAS_EN_MASK, 1);
1455 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1456 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1457 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1458 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1459 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1460 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1461 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1462 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1463 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1464 WCD938X_AUXPA_CLK_EN_MASK, 1);
1465 break;
1466 case SND_SOC_DAPM_POST_PMD:
1467 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1468 WCD938X_VNEG_EN_MASK, 0);
1469 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1470 WCD938X_VPOS_EN_MASK, 0);
1471 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1472 WCD938X_RX_BIAS_EN_MASK, 0);
1473 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1474 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1475 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1476 WCD938X_ANA_RX_CLK_EN_MASK, 0);
1477 break;
1478 }
1479 return 0;
1480 }
1481
wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1482 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1483 struct snd_kcontrol *kcontrol,
1484 int event)
1485 {
1486 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1487 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1488
1489 switch (event) {
1490 case SND_SOC_DAPM_PRE_PMU:
1491 snd_soc_component_write_field(component,
1492 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1493 WCD938X_RXD0_CLK_EN_MASK, 0x01);
1494 snd_soc_component_write_field(component,
1495 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1496 WCD938X_HPHL_RX_EN_MASK, 1);
1497 snd_soc_component_write_field(component,
1498 WCD938X_HPH_RDAC_CLK_CTL1,
1499 WCD938X_CHOP_CLK_EN_MASK, 0);
1500 break;
1501 case SND_SOC_DAPM_POST_PMU:
1502 snd_soc_component_write_field(component,
1503 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1504 WCD938X_HPH_RES_DIV_MASK, 0x02);
1505 if (wcd938x->comp1_enable) {
1506 snd_soc_component_write_field(component,
1507 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1508 WCD938X_HPHL_COMP_EN_MASK, 1);
1509 /* 5msec compander delay as per HW requirement */
1510 if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1511 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1512 usleep_range(5000, 5010);
1513 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1514 WCD938X_AUTOCHOP_TIMER_EN, 0);
1515 } else {
1516 snd_soc_component_write_field(component,
1517 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1518 WCD938X_HPHL_COMP_EN_MASK, 0);
1519 snd_soc_component_write_field(component,
1520 WCD938X_HPH_L_EN,
1521 WCD938X_GAIN_SRC_SEL_MASK,
1522 WCD938X_GAIN_SRC_SEL_REGISTER);
1523
1524 }
1525 break;
1526 case SND_SOC_DAPM_POST_PMD:
1527 snd_soc_component_write_field(component,
1528 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1529 WCD938X_HPH_RES_DIV_MASK, 0x1);
1530 break;
1531 }
1532
1533 return 0;
1534 }
1535
wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1536 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1537 struct snd_kcontrol *kcontrol,
1538 int event)
1539 {
1540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1541 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1542
1543 switch (event) {
1544 case SND_SOC_DAPM_PRE_PMU:
1545 snd_soc_component_write_field(component,
1546 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1547 WCD938X_RXD1_CLK_EN_MASK, 1);
1548 snd_soc_component_write_field(component,
1549 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1550 WCD938X_HPHR_RX_EN_MASK, 1);
1551 snd_soc_component_write_field(component,
1552 WCD938X_HPH_RDAC_CLK_CTL1,
1553 WCD938X_CHOP_CLK_EN_MASK, 0);
1554 break;
1555 case SND_SOC_DAPM_POST_PMU:
1556 snd_soc_component_write_field(component,
1557 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1558 WCD938X_HPH_RES_DIV_MASK, 0x02);
1559 if (wcd938x->comp2_enable) {
1560 snd_soc_component_write_field(component,
1561 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1562 WCD938X_HPHR_COMP_EN_MASK, 1);
1563 /* 5msec compander delay as per HW requirement */
1564 if (!wcd938x->comp1_enable ||
1565 (snd_soc_component_read(component,
1566 WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1567 usleep_range(5000, 5010);
1568 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1569 WCD938X_AUTOCHOP_TIMER_EN, 0);
1570 } else {
1571 snd_soc_component_write_field(component,
1572 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1573 WCD938X_HPHR_COMP_EN_MASK, 0);
1574 snd_soc_component_write_field(component,
1575 WCD938X_HPH_R_EN,
1576 WCD938X_GAIN_SRC_SEL_MASK,
1577 WCD938X_GAIN_SRC_SEL_REGISTER);
1578 }
1579 break;
1580 case SND_SOC_DAPM_POST_PMD:
1581 snd_soc_component_write_field(component,
1582 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1583 WCD938X_HPH_RES_DIV_MASK, 0x01);
1584 break;
1585 }
1586
1587 return 0;
1588 }
1589
wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1590 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1591 struct snd_kcontrol *kcontrol,
1592 int event)
1593 {
1594 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1595 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1596
1597 switch (event) {
1598 case SND_SOC_DAPM_PRE_PMU:
1599 wcd938x->ear_rx_path =
1600 snd_soc_component_read(
1601 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1602 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1603 snd_soc_component_write_field(component,
1604 WCD938X_EAR_EAR_DAC_CON,
1605 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1606 snd_soc_component_write_field(component,
1607 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1608 WCD938X_AUX_EN_MASK, 1);
1609 snd_soc_component_write_field(component,
1610 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1611 WCD938X_RXD2_CLK_EN_MASK, 1);
1612 snd_soc_component_write_field(component,
1613 WCD938X_ANA_EAR_COMPANDER_CTL,
1614 WCD938X_GAIN_OVRD_REG_MASK, 1);
1615 } else {
1616 snd_soc_component_write_field(component,
1617 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1618 WCD938X_HPHL_RX_EN_MASK, 1);
1619 snd_soc_component_write_field(component,
1620 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1621 WCD938X_RXD0_CLK_EN_MASK, 1);
1622 if (wcd938x->comp1_enable)
1623 snd_soc_component_write_field(component,
1624 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1625 WCD938X_HPHL_COMP_EN_MASK, 1);
1626 }
1627 /* 5 msec delay as per HW requirement */
1628 usleep_range(5000, 5010);
1629 if (wcd938x->flyback_cur_det_disable == 0)
1630 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1631 WCD938X_EN_CUR_DET_MASK, 0);
1632 wcd938x->flyback_cur_det_disable++;
1633 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1634 WCD_CLSH_EVENT_PRE_DAC,
1635 WCD_CLSH_STATE_EAR,
1636 wcd938x->hph_mode);
1637 break;
1638 case SND_SOC_DAPM_POST_PMD:
1639 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1640 snd_soc_component_write_field(component,
1641 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1642 WCD938X_AUX_EN_MASK, 0);
1643 snd_soc_component_write_field(component,
1644 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1645 WCD938X_RXD2_CLK_EN_MASK, 0);
1646 } else {
1647 snd_soc_component_write_field(component,
1648 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1649 WCD938X_HPHL_RX_EN_MASK, 0);
1650 snd_soc_component_write_field(component,
1651 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1652 WCD938X_RXD0_CLK_EN_MASK, 0);
1653 if (wcd938x->comp1_enable)
1654 snd_soc_component_write_field(component,
1655 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1656 WCD938X_HPHL_COMP_EN_MASK, 0);
1657 }
1658 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1659 WCD938X_GAIN_OVRD_REG_MASK, 0);
1660 snd_soc_component_write_field(component,
1661 WCD938X_EAR_EAR_DAC_CON,
1662 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1663 break;
1664 }
1665 return 0;
1666
1667 }
1668
wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1669 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1670 struct snd_kcontrol *kcontrol,
1671 int event)
1672 {
1673 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1674 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1675
1676 switch (event) {
1677 case SND_SOC_DAPM_PRE_PMU:
1678 snd_soc_component_write_field(component,
1679 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1680 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1681 snd_soc_component_write_field(component,
1682 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1683 WCD938X_RXD2_CLK_EN_MASK, 1);
1684 snd_soc_component_write_field(component,
1685 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1686 WCD938X_AUX_EN_MASK, 1);
1687 if (wcd938x->flyback_cur_det_disable == 0)
1688 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1689 WCD938X_EN_CUR_DET_MASK, 0);
1690 wcd938x->flyback_cur_det_disable++;
1691 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1692 WCD_CLSH_EVENT_PRE_DAC,
1693 WCD_CLSH_STATE_AUX,
1694 wcd938x->hph_mode);
1695 break;
1696 case SND_SOC_DAPM_POST_PMD:
1697 snd_soc_component_write_field(component,
1698 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1699 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1700 break;
1701 }
1702 return 0;
1703
1704 }
1705
wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1706 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1707 struct snd_kcontrol *kcontrol, int event)
1708 {
1709 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1710 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1711 int hph_mode = wcd938x->hph_mode;
1712
1713 switch (event) {
1714 case SND_SOC_DAPM_PRE_PMU:
1715 if (wcd938x->ldoh)
1716 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1717 WCD938X_LDOH_EN_MASK, 1);
1718 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1719 WCD_CLSH_STATE_HPHR, hph_mode);
1720 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1721
1722 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1723 hph_mode == CLS_H_ULP) {
1724 snd_soc_component_write_field(component,
1725 WCD938X_HPH_REFBUFF_LP_CTL,
1726 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1727 }
1728 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1729 WCD938X_HPHR_REF_EN_MASK, 1);
1730 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1731 /* 100 usec delay as per HW requirement */
1732 usleep_range(100, 110);
1733 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1734 snd_soc_component_write_field(component,
1735 WCD938X_DIGITAL_PDM_WD_CTL1,
1736 WCD938X_PDM_WD_EN_MASK, 0x3);
1737 break;
1738 case SND_SOC_DAPM_POST_PMU:
1739 /*
1740 * 7ms sleep is required if compander is enabled as per
1741 * HW requirement. If compander is disabled, then
1742 * 20ms delay is required.
1743 */
1744 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1745 if (!wcd938x->comp2_enable)
1746 usleep_range(20000, 20100);
1747 else
1748 usleep_range(7000, 7100);
1749
1750 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1751 hph_mode == CLS_H_ULP)
1752 snd_soc_component_write_field(component,
1753 WCD938X_HPH_REFBUFF_LP_CTL,
1754 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1755 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1756 }
1757 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1758 WCD938X_AUTOCHOP_TIMER_EN, 1);
1759 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1760 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1761 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1762 WCD938X_REGULATOR_MODE_MASK,
1763 WCD938X_REGULATOR_MODE_CLASS_AB);
1764 enable_irq(wcd938x->hphr_pdm_wd_int);
1765 break;
1766 case SND_SOC_DAPM_PRE_PMD:
1767 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1768 /*
1769 * 7ms sleep is required if compander is enabled as per
1770 * HW requirement. If compander is disabled, then
1771 * 20ms delay is required.
1772 */
1773 if (!wcd938x->comp2_enable)
1774 usleep_range(20000, 20100);
1775 else
1776 usleep_range(7000, 7100);
1777 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1778 WCD938X_HPHR_EN_MASK, 0);
1779 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1780 WCD_EVENT_PRE_HPHR_PA_OFF);
1781 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1782 break;
1783 case SND_SOC_DAPM_POST_PMD:
1784 /*
1785 * 7ms sleep is required if compander is enabled as per
1786 * HW requirement. If compander is disabled, then
1787 * 20ms delay is required.
1788 */
1789 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1790 if (!wcd938x->comp2_enable)
1791 usleep_range(20000, 20100);
1792 else
1793 usleep_range(7000, 7100);
1794 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1795 }
1796 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1797 WCD_EVENT_POST_HPHR_PA_OFF);
1798 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1799 WCD938X_HPHR_REF_EN_MASK, 0);
1800 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1801 WCD938X_PDM_WD_EN_MASK, 0);
1802 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1803 WCD_CLSH_STATE_HPHR, hph_mode);
1804 if (wcd938x->ldoh)
1805 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1806 WCD938X_LDOH_EN_MASK, 0);
1807 break;
1808 }
1809
1810 return 0;
1811 }
1812
wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1813 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1814 struct snd_kcontrol *kcontrol, int event)
1815 {
1816 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1817 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1818 int hph_mode = wcd938x->hph_mode;
1819
1820 switch (event) {
1821 case SND_SOC_DAPM_PRE_PMU:
1822 if (wcd938x->ldoh)
1823 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1824 WCD938X_LDOH_EN_MASK, 1);
1825 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1826 WCD_CLSH_STATE_HPHL, hph_mode);
1827 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1828 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1829 hph_mode == CLS_H_ULP) {
1830 snd_soc_component_write_field(component,
1831 WCD938X_HPH_REFBUFF_LP_CTL,
1832 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1833 }
1834 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1835 WCD938X_HPHL_REF_EN_MASK, 1);
1836 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1837 /* 100 usec delay as per HW requirement */
1838 usleep_range(100, 110);
1839 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1840 snd_soc_component_write_field(component,
1841 WCD938X_DIGITAL_PDM_WD_CTL0,
1842 WCD938X_PDM_WD_EN_MASK, 0x3);
1843 break;
1844 case SND_SOC_DAPM_POST_PMU:
1845 /*
1846 * 7ms sleep is required if compander is enabled as per
1847 * HW requirement. If compander is disabled, then
1848 * 20ms delay is required.
1849 */
1850 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1851 if (!wcd938x->comp1_enable)
1852 usleep_range(20000, 20100);
1853 else
1854 usleep_range(7000, 7100);
1855 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1856 hph_mode == CLS_H_ULP)
1857 snd_soc_component_write_field(component,
1858 WCD938X_HPH_REFBUFF_LP_CTL,
1859 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1860 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1861 }
1862
1863 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1864 WCD938X_AUTOCHOP_TIMER_EN, 1);
1865 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1866 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1867 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1868 WCD938X_REGULATOR_MODE_MASK,
1869 WCD938X_REGULATOR_MODE_CLASS_AB);
1870 enable_irq(wcd938x->hphl_pdm_wd_int);
1871 break;
1872 case SND_SOC_DAPM_PRE_PMD:
1873 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1874 /*
1875 * 7ms sleep is required if compander is enabled as per
1876 * HW requirement. If compander is disabled, then
1877 * 20ms delay is required.
1878 */
1879 if (!wcd938x->comp1_enable)
1880 usleep_range(20000, 20100);
1881 else
1882 usleep_range(7000, 7100);
1883 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1884 WCD938X_HPHL_EN_MASK, 0);
1885 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
1886 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1887 break;
1888 case SND_SOC_DAPM_POST_PMD:
1889 /*
1890 * 7ms sleep is required if compander is enabled as per
1891 * HW requirement. If compander is disabled, then
1892 * 20ms delay is required.
1893 */
1894 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1895 if (!wcd938x->comp1_enable)
1896 usleep_range(21000, 21100);
1897 else
1898 usleep_range(7000, 7100);
1899 clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1900 }
1901 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1902 WCD_EVENT_POST_HPHL_PA_OFF);
1903 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1904 WCD938X_HPHL_REF_EN_MASK, 0);
1905 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1906 WCD938X_PDM_WD_EN_MASK, 0);
1907 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1908 WCD_CLSH_STATE_HPHL, hph_mode);
1909 if (wcd938x->ldoh)
1910 snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1911 WCD938X_LDOH_EN_MASK, 0);
1912 break;
1913 }
1914
1915 return 0;
1916 }
1917
wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1918 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1919 struct snd_kcontrol *kcontrol, int event)
1920 {
1921 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1922 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1923 int hph_mode = wcd938x->hph_mode;
1924
1925 switch (event) {
1926 case SND_SOC_DAPM_PRE_PMU:
1927 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1928 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1929 break;
1930 case SND_SOC_DAPM_POST_PMU:
1931 /* 1 msec delay as per HW requirement */
1932 usleep_range(1000, 1010);
1933 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1934 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1935 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1936 WCD938X_REGULATOR_MODE_MASK,
1937 WCD938X_REGULATOR_MODE_CLASS_AB);
1938 enable_irq(wcd938x->aux_pdm_wd_int);
1939 break;
1940 case SND_SOC_DAPM_PRE_PMD:
1941 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1942 break;
1943 case SND_SOC_DAPM_POST_PMD:
1944 /* 1 msec delay as per HW requirement */
1945 usleep_range(1000, 1010);
1946 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1947 WCD938X_AUX_PDM_WD_EN_MASK, 0);
1948 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1949 WCD_CLSH_EVENT_POST_PA,
1950 WCD_CLSH_STATE_AUX,
1951 hph_mode);
1952
1953 wcd938x->flyback_cur_det_disable--;
1954 if (wcd938x->flyback_cur_det_disable == 0)
1955 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1956 WCD938X_EN_CUR_DET_MASK, 1);
1957 break;
1958 }
1959 return 0;
1960 }
1961
wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1962 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1963 struct snd_kcontrol *kcontrol, int event)
1964 {
1965 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1966 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1967 int hph_mode = wcd938x->hph_mode;
1968
1969 switch (event) {
1970 case SND_SOC_DAPM_PRE_PMU:
1971 /*
1972 * Enable watchdog interrupt for HPHL or AUX
1973 * depending on mux value
1974 */
1975 wcd938x->ear_rx_path = snd_soc_component_read(component,
1976 WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1977 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1978 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1979 WCD938X_AUX_PDM_WD_EN_MASK, 1);
1980 else
1981 snd_soc_component_write_field(component,
1982 WCD938X_DIGITAL_PDM_WD_CTL0,
1983 WCD938X_PDM_WD_EN_MASK, 0x3);
1984 if (!wcd938x->comp1_enable)
1985 snd_soc_component_write_field(component,
1986 WCD938X_ANA_EAR_COMPANDER_CTL,
1987 WCD938X_GAIN_OVRD_REG_MASK, 1);
1988
1989 break;
1990 case SND_SOC_DAPM_POST_PMU:
1991 /* 6 msec delay as per HW requirement */
1992 usleep_range(6000, 6010);
1993 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1994 hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1995 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1996 WCD938X_REGULATOR_MODE_MASK,
1997 WCD938X_REGULATOR_MODE_CLASS_AB);
1998 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1999 enable_irq(wcd938x->aux_pdm_wd_int);
2000 else
2001 enable_irq(wcd938x->hphl_pdm_wd_int);
2002 break;
2003 case SND_SOC_DAPM_PRE_PMD:
2004 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2005 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
2006 else
2007 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
2008 break;
2009 case SND_SOC_DAPM_POST_PMD:
2010 if (!wcd938x->comp1_enable)
2011 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2012 WCD938X_GAIN_OVRD_REG_MASK, 0);
2013 /* 7 msec delay as per HW requirement */
2014 usleep_range(7000, 7010);
2015 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2016 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
2017 WCD938X_AUX_PDM_WD_EN_MASK, 0);
2018 else
2019 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
2020 WCD938X_PDM_WD_EN_MASK, 0);
2021
2022 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
2023 WCD_CLSH_STATE_EAR, hph_mode);
2024
2025 wcd938x->flyback_cur_det_disable--;
2026 if (wcd938x->flyback_cur_det_disable == 0)
2027 snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
2028 WCD938X_EN_CUR_DET_MASK, 1);
2029 break;
2030 }
2031
2032 return 0;
2033 }
2034
wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2035 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2036 struct snd_kcontrol *kcontrol,
2037 int event)
2038 {
2039 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2040 u16 dmic_clk_reg, dmic_clk_en_reg;
2041 u8 dmic_sel_mask, dmic_clk_mask;
2042
2043 switch (w->shift) {
2044 case 0:
2045 case 1:
2046 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2047 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
2048 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
2049 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
2050 break;
2051 case 2:
2052 case 3:
2053 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2054 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
2055 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
2056 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
2057 break;
2058 case 4:
2059 case 5:
2060 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2061 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
2062 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
2063 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
2064 break;
2065 case 6:
2066 case 7:
2067 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2068 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
2069 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
2070 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
2071 break;
2072 default:
2073 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
2074 __func__);
2075 return -EINVAL;
2076 }
2077
2078 switch (event) {
2079 case SND_SOC_DAPM_PRE_PMU:
2080 snd_soc_component_write_field(component,
2081 WCD938X_DIGITAL_CDC_AMIC_CTL,
2082 dmic_sel_mask,
2083 WCD938X_AMIC1_IN_SEL_DMIC);
2084 /* 250us sleep as per HW requirement */
2085 usleep_range(250, 260);
2086 /* Setting DMIC clock rate to 2.4MHz */
2087 snd_soc_component_write_field(component, dmic_clk_reg,
2088 dmic_clk_mask,
2089 WCD938X_DMIC4_RATE_2P4MHZ);
2090 snd_soc_component_write_field(component, dmic_clk_en_reg,
2091 WCD938X_DMIC_CLK_EN_MASK, 1);
2092 /* enable clock scaling */
2093 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
2094 WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
2095 break;
2096 case SND_SOC_DAPM_POST_PMD:
2097 snd_soc_component_write_field(component,
2098 WCD938X_DIGITAL_CDC_AMIC_CTL,
2099 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
2100 snd_soc_component_write_field(component, dmic_clk_en_reg,
2101 WCD938X_DMIC_CLK_EN_MASK, 0);
2102 break;
2103 }
2104 return 0;
2105 }
2106
wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2107 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
2108 struct snd_kcontrol *kcontrol, int event)
2109 {
2110 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2111 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2112 int bank;
2113 int rate;
2114
2115 bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
2116 bank = bank ? 0 : 1;
2117
2118 switch (event) {
2119 case SND_SOC_DAPM_PRE_PMU:
2120 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2121 int i = 0, mode = 0;
2122
2123 if (test_bit(WCD_ADC1, &wcd938x->status_mask))
2124 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
2125 if (test_bit(WCD_ADC2, &wcd938x->status_mask))
2126 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
2127 if (test_bit(WCD_ADC3, &wcd938x->status_mask))
2128 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
2129 if (test_bit(WCD_ADC4, &wcd938x->status_mask))
2130 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
2131
2132 if (mode != 0) {
2133 for (i = 0; i < ADC_MODE_ULP2; i++) {
2134 if (mode & (1 << i)) {
2135 i++;
2136 break;
2137 }
2138 }
2139 }
2140 rate = wcd938x_get_clk_rate(i);
2141 wcd938x_set_swr_clk_rate(component, rate, bank);
2142 /* Copy clk settings to active bank */
2143 wcd938x_set_swr_clk_rate(component, rate, !bank);
2144 }
2145 break;
2146 case SND_SOC_DAPM_POST_PMD:
2147 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2148 rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
2149 wcd938x_set_swr_clk_rate(component, rate, !bank);
2150 wcd938x_set_swr_clk_rate(component, rate, bank);
2151 }
2152 break;
2153 }
2154
2155 return 0;
2156 }
2157
wcd938x_get_adc_mode(int val)2158 static int wcd938x_get_adc_mode(int val)
2159 {
2160 int ret = 0;
2161
2162 switch (val) {
2163 case ADC_MODE_INVALID:
2164 ret = ADC_MODE_VAL_NORMAL;
2165 break;
2166 case ADC_MODE_HIFI:
2167 ret = ADC_MODE_VAL_HIFI;
2168 break;
2169 case ADC_MODE_LO_HIF:
2170 ret = ADC_MODE_VAL_LO_HIF;
2171 break;
2172 case ADC_MODE_NORMAL:
2173 ret = ADC_MODE_VAL_NORMAL;
2174 break;
2175 case ADC_MODE_LP:
2176 ret = ADC_MODE_VAL_LP;
2177 break;
2178 case ADC_MODE_ULP1:
2179 ret = ADC_MODE_VAL_ULP1;
2180 break;
2181 case ADC_MODE_ULP2:
2182 ret = ADC_MODE_VAL_ULP2;
2183 break;
2184 default:
2185 ret = -EINVAL;
2186 break;
2187 }
2188 return ret;
2189 }
2190
wcd938x_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2191 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
2192 struct snd_kcontrol *kcontrol, int event)
2193 {
2194 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2195 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2196
2197 switch (event) {
2198 case SND_SOC_DAPM_PRE_PMU:
2199 snd_soc_component_write_field(component,
2200 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2201 WCD938X_ANA_TX_CLK_EN_MASK, 1);
2202 snd_soc_component_write_field(component,
2203 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2204 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2205 set_bit(w->shift, &wcd938x->status_mask);
2206 break;
2207 case SND_SOC_DAPM_POST_PMD:
2208 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2209 WCD938X_ANA_TX_CLK_EN_MASK, 0);
2210 clear_bit(w->shift, &wcd938x->status_mask);
2211 break;
2212 }
2213
2214 return 0;
2215 }
2216
wcd938x_tx_channel_config(struct snd_soc_component * component,int channel,int mode)2217 static void wcd938x_tx_channel_config(struct snd_soc_component *component,
2218 int channel, int mode)
2219 {
2220 int reg, mask;
2221
2222 switch (channel) {
2223 case 0:
2224 reg = WCD938X_ANA_TX_CH2;
2225 mask = WCD938X_HPF1_INIT_MASK;
2226 break;
2227 case 1:
2228 reg = WCD938X_ANA_TX_CH2;
2229 mask = WCD938X_HPF2_INIT_MASK;
2230 break;
2231 case 2:
2232 reg = WCD938X_ANA_TX_CH4;
2233 mask = WCD938X_HPF3_INIT_MASK;
2234 break;
2235 case 3:
2236 reg = WCD938X_ANA_TX_CH4;
2237 mask = WCD938X_HPF4_INIT_MASK;
2238 break;
2239 default:
2240 return;
2241 }
2242
2243 snd_soc_component_write_field(component, reg, mask, mode);
2244 }
2245
wcd938x_adc_enable_req(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2246 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
2247 struct snd_kcontrol *kcontrol, int event)
2248 {
2249 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2250 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2251 int mode;
2252
2253 switch (event) {
2254 case SND_SOC_DAPM_PRE_PMU:
2255 snd_soc_component_write_field(component,
2256 WCD938X_DIGITAL_CDC_REQ_CTL,
2257 WCD938X_FS_RATE_4P8_MASK, 1);
2258 snd_soc_component_write_field(component,
2259 WCD938X_DIGITAL_CDC_REQ_CTL,
2260 WCD938X_NO_NOTCH_MASK, 0);
2261 wcd938x_tx_channel_config(component, w->shift, 1);
2262 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
2263 if (mode < 0) {
2264 dev_info(component->dev, "Invalid ADC mode\n");
2265 return -EINVAL;
2266 }
2267 switch (w->shift) {
2268 case 0:
2269 snd_soc_component_write_field(component,
2270 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2271 WCD938X_TXD0_MODE_MASK, mode);
2272 snd_soc_component_write_field(component,
2273 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2274 WCD938X_TXD0_CLK_EN_MASK, 1);
2275 break;
2276 case 1:
2277 snd_soc_component_write_field(component,
2278 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2279 WCD938X_TXD1_MODE_MASK, mode);
2280 snd_soc_component_write_field(component,
2281 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2282 WCD938X_TXD1_CLK_EN_MASK, 1);
2283 break;
2284 case 2:
2285 snd_soc_component_write_field(component,
2286 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2287 WCD938X_TXD2_MODE_MASK, mode);
2288 snd_soc_component_write_field(component,
2289 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2290 WCD938X_TXD2_CLK_EN_MASK, 1);
2291 break;
2292 case 3:
2293 snd_soc_component_write_field(component,
2294 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2295 WCD938X_TXD3_MODE_MASK, mode);
2296 snd_soc_component_write_field(component,
2297 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2298 WCD938X_TXD3_CLK_EN_MASK, 1);
2299 break;
2300 default:
2301 break;
2302 }
2303
2304 wcd938x_tx_channel_config(component, w->shift, 0);
2305 break;
2306 case SND_SOC_DAPM_POST_PMD:
2307 switch (w->shift) {
2308 case 0:
2309 snd_soc_component_write_field(component,
2310 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2311 WCD938X_TXD0_MODE_MASK, 0);
2312 snd_soc_component_write_field(component,
2313 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2314 WCD938X_TXD0_CLK_EN_MASK, 0);
2315 break;
2316 case 1:
2317 snd_soc_component_write_field(component,
2318 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2319 WCD938X_TXD1_MODE_MASK, 0);
2320 snd_soc_component_write_field(component,
2321 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2322 WCD938X_TXD1_CLK_EN_MASK, 0);
2323 break;
2324 case 2:
2325 snd_soc_component_write_field(component,
2326 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2327 WCD938X_TXD2_MODE_MASK, 0);
2328 snd_soc_component_write_field(component,
2329 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2330 WCD938X_TXD2_CLK_EN_MASK, 0);
2331 break;
2332 case 3:
2333 snd_soc_component_write_field(component,
2334 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2335 WCD938X_TXD3_MODE_MASK, 0);
2336 snd_soc_component_write_field(component,
2337 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2338 WCD938X_TXD3_CLK_EN_MASK, 0);
2339 break;
2340 default:
2341 break;
2342 }
2343 snd_soc_component_write_field(component,
2344 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2345 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
2346 break;
2347 }
2348
2349 return 0;
2350 }
2351
wcd938x_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2352 static int wcd938x_micbias_control(struct snd_soc_component *component,
2353 int micb_num, int req, bool is_dapm)
2354 {
2355 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2356 int micb_index = micb_num - 1;
2357 u16 micb_reg;
2358
2359 switch (micb_num) {
2360 case MIC_BIAS_1:
2361 micb_reg = WCD938X_ANA_MICB1;
2362 break;
2363 case MIC_BIAS_2:
2364 micb_reg = WCD938X_ANA_MICB2;
2365 break;
2366 case MIC_BIAS_3:
2367 micb_reg = WCD938X_ANA_MICB3;
2368 break;
2369 case MIC_BIAS_4:
2370 micb_reg = WCD938X_ANA_MICB4;
2371 break;
2372 default:
2373 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2374 __func__, micb_num);
2375 return -EINVAL;
2376 }
2377
2378 switch (req) {
2379 case MICB_PULLUP_ENABLE:
2380 wcd938x->pullup_ref[micb_index]++;
2381 if ((wcd938x->pullup_ref[micb_index] == 1) &&
2382 (wcd938x->micb_ref[micb_index] == 0))
2383 snd_soc_component_write_field(component, micb_reg,
2384 WCD938X_MICB_EN_MASK,
2385 WCD938X_MICB_PULL_UP);
2386 break;
2387 case MICB_PULLUP_DISABLE:
2388 if (wcd938x->pullup_ref[micb_index] > 0)
2389 wcd938x->pullup_ref[micb_index]--;
2390
2391 if ((wcd938x->pullup_ref[micb_index] == 0) &&
2392 (wcd938x->micb_ref[micb_index] == 0))
2393 snd_soc_component_write_field(component, micb_reg,
2394 WCD938X_MICB_EN_MASK, 0);
2395 break;
2396 case MICB_ENABLE:
2397 wcd938x->micb_ref[micb_index]++;
2398 if (wcd938x->micb_ref[micb_index] == 1) {
2399 snd_soc_component_write_field(component,
2400 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2401 WCD938X_TX_CLK_EN_MASK, 0xF);
2402 snd_soc_component_write_field(component,
2403 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2404 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2405 snd_soc_component_write_field(component,
2406 WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
2407 WCD938X_TX_SC_CLK_EN_MASK, 1);
2408
2409 snd_soc_component_write_field(component, micb_reg,
2410 WCD938X_MICB_EN_MASK,
2411 WCD938X_MICB_ENABLE);
2412 if (micb_num == MIC_BIAS_2)
2413 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2414 WCD_EVENT_POST_MICBIAS_2_ON);
2415 }
2416 if (micb_num == MIC_BIAS_2 && is_dapm)
2417 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2418 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2419
2420
2421 break;
2422 case MICB_DISABLE:
2423 if (wcd938x->micb_ref[micb_index] > 0)
2424 wcd938x->micb_ref[micb_index]--;
2425
2426 if ((wcd938x->micb_ref[micb_index] == 0) &&
2427 (wcd938x->pullup_ref[micb_index] > 0))
2428 snd_soc_component_write_field(component, micb_reg,
2429 WCD938X_MICB_EN_MASK,
2430 WCD938X_MICB_PULL_UP);
2431 else if ((wcd938x->micb_ref[micb_index] == 0) &&
2432 (wcd938x->pullup_ref[micb_index] == 0)) {
2433 if (micb_num == MIC_BIAS_2)
2434 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2435 WCD_EVENT_PRE_MICBIAS_2_OFF);
2436
2437 snd_soc_component_write_field(component, micb_reg,
2438 WCD938X_MICB_EN_MASK, 0);
2439 if (micb_num == MIC_BIAS_2)
2440 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2441 WCD_EVENT_POST_MICBIAS_2_OFF);
2442 }
2443 if (is_dapm && micb_num == MIC_BIAS_2)
2444 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2445 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2446 break;
2447 }
2448
2449 return 0;
2450 }
2451
wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2452 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2453 struct snd_kcontrol *kcontrol,
2454 int event)
2455 {
2456 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2457 int micb_num = w->shift;
2458
2459 switch (event) {
2460 case SND_SOC_DAPM_PRE_PMU:
2461 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
2462 break;
2463 case SND_SOC_DAPM_POST_PMU:
2464 /* 1 msec delay as per HW requirement */
2465 usleep_range(1000, 1100);
2466 break;
2467 case SND_SOC_DAPM_POST_PMD:
2468 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
2469 break;
2470 }
2471
2472 return 0;
2473 }
2474
wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2475 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
2476 struct snd_kcontrol *kcontrol,
2477 int event)
2478 {
2479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2480 int micb_num = w->shift;
2481
2482 switch (event) {
2483 case SND_SOC_DAPM_PRE_PMU:
2484 wcd938x_micbias_control(component, micb_num,
2485 MICB_PULLUP_ENABLE, true);
2486 break;
2487 case SND_SOC_DAPM_POST_PMU:
2488 /* 1 msec delay as per HW requirement */
2489 usleep_range(1000, 1100);
2490 break;
2491 case SND_SOC_DAPM_POST_PMD:
2492 wcd938x_micbias_control(component, micb_num,
2493 MICB_PULLUP_DISABLE, true);
2494 break;
2495 }
2496
2497 return 0;
2498 }
2499
wcd938x_tx_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2500 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
2501 struct snd_ctl_elem_value *ucontrol)
2502 {
2503 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2504 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2505 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2506 int path = e->shift_l;
2507
2508 ucontrol->value.enumerated.item[0] = wcd938x->tx_mode[path];
2509
2510 return 0;
2511 }
2512
wcd938x_tx_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2513 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
2514 struct snd_ctl_elem_value *ucontrol)
2515 {
2516 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2517 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2518 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2519 int path = e->shift_l;
2520
2521 if (wcd938x->tx_mode[path] == ucontrol->value.enumerated.item[0])
2522 return 0;
2523
2524 wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
2525
2526 return 1;
2527 }
2528
wcd938x_rx_hph_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2529 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
2530 struct snd_ctl_elem_value *ucontrol)
2531 {
2532 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2533 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2534
2535 ucontrol->value.enumerated.item[0] = wcd938x->hph_mode;
2536
2537 return 0;
2538 }
2539
wcd938x_rx_hph_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2540 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
2541 struct snd_ctl_elem_value *ucontrol)
2542 {
2543 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2544 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2545
2546 if (wcd938x->hph_mode == ucontrol->value.enumerated.item[0])
2547 return 0;
2548
2549 wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
2550
2551 return 1;
2552 }
2553
wcd938x_ear_pa_put_gain(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2554 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
2555 struct snd_ctl_elem_value *ucontrol)
2556 {
2557 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2558 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2559
2560 if (wcd938x->comp1_enable) {
2561 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
2562 return -EINVAL;
2563 }
2564
2565 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2566 WCD938X_EAR_GAIN_MASK,
2567 ucontrol->value.integer.value[0]);
2568
2569 return 1;
2570 }
2571
wcd938x_get_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2572 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
2573 struct snd_ctl_elem_value *ucontrol)
2574 {
2575
2576 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2577 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2578 struct soc_mixer_control *mc;
2579 bool hphr;
2580
2581 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2582 hphr = mc->shift;
2583
2584 if (hphr)
2585 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
2586 else
2587 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2588
2589 return 0;
2590 }
2591
wcd938x_set_compander(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2592 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2593 struct snd_ctl_elem_value *ucontrol)
2594 {
2595 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2596 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2597 struct wcd938x_sdw_priv *wcd;
2598 int value = ucontrol->value.integer.value[0];
2599 int portidx;
2600 struct soc_mixer_control *mc;
2601 bool hphr;
2602
2603 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2604 hphr = mc->shift;
2605
2606 wcd = wcd938x->sdw_priv[AIF1_PB];
2607
2608 if (hphr)
2609 wcd938x->comp2_enable = value;
2610 else
2611 wcd938x->comp1_enable = value;
2612
2613 portidx = wcd->ch_info[mc->reg].port_num;
2614
2615 if (value)
2616 wcd938x_connect_port(wcd, portidx, mc->reg, true);
2617 else
2618 wcd938x_connect_port(wcd, portidx, mc->reg, false);
2619
2620 return 1;
2621 }
2622
wcd938x_ldoh_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2623 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2624 struct snd_ctl_elem_value *ucontrol)
2625 {
2626 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2627 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2628
2629 ucontrol->value.integer.value[0] = wcd938x->ldoh;
2630
2631 return 0;
2632 }
2633
wcd938x_ldoh_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2634 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2635 struct snd_ctl_elem_value *ucontrol)
2636 {
2637 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2638 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2639
2640 if (wcd938x->ldoh == ucontrol->value.integer.value[0])
2641 return 0;
2642
2643 wcd938x->ldoh = ucontrol->value.integer.value[0];
2644
2645 return 1;
2646 }
2647
wcd938x_bcs_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2648 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2649 struct snd_ctl_elem_value *ucontrol)
2650 {
2651 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2652 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2653
2654 ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2655
2656 return 0;
2657 }
2658
wcd938x_bcs_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2659 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2660 struct snd_ctl_elem_value *ucontrol)
2661 {
2662 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2663 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2664
2665 if (wcd938x->bcs_dis == ucontrol->value.integer.value[0])
2666 return 0;
2667
2668 wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2669
2670 return 1;
2671 }
2672
2673 static const char * const tx_mode_mux_text_wcd9380[] = {
2674 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2675 };
2676
2677 static const char * const tx_mode_mux_text[] = {
2678 "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2679 "ADC_ULP1", "ADC_ULP2",
2680 };
2681
2682 static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2683 "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2684 "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2685 "CLS_AB_LOHIFI",
2686 };
2687
2688 static const char * const rx_hph_mode_mux_text[] = {
2689 "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2690 "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2691 };
2692
2693 static const char * const adc2_mux_text[] = {
2694 "INP2", "INP3"
2695 };
2696
2697 static const char * const adc3_mux_text[] = {
2698 "INP4", "INP6"
2699 };
2700
2701 static const char * const adc4_mux_text[] = {
2702 "INP5", "INP7"
2703 };
2704
2705 static const char * const rdac3_mux_text[] = {
2706 "RX1", "RX3"
2707 };
2708
2709 static const char * const hdr12_mux_text[] = {
2710 "NO_HDR12", "HDR12"
2711 };
2712
2713 static const char * const hdr34_mux_text[] = {
2714 "NO_HDR34", "HDR34"
2715 };
2716
2717 static const struct soc_enum tx0_mode_enum_wcd9380 =
2718 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2719 tx_mode_mux_text_wcd9380);
2720
2721 static const struct soc_enum tx1_mode_enum_wcd9380 =
2722 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2723 tx_mode_mux_text_wcd9380);
2724
2725 static const struct soc_enum tx2_mode_enum_wcd9380 =
2726 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2727 tx_mode_mux_text_wcd9380);
2728
2729 static const struct soc_enum tx3_mode_enum_wcd9380 =
2730 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2731 tx_mode_mux_text_wcd9380);
2732
2733 static const struct soc_enum tx0_mode_enum_wcd9385 =
2734 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2735 tx_mode_mux_text);
2736
2737 static const struct soc_enum tx1_mode_enum_wcd9385 =
2738 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2739 tx_mode_mux_text);
2740
2741 static const struct soc_enum tx2_mode_enum_wcd9385 =
2742 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2743 tx_mode_mux_text);
2744
2745 static const struct soc_enum tx3_mode_enum_wcd9385 =
2746 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2747 tx_mode_mux_text);
2748
2749 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2750 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2751 rx_hph_mode_mux_text_wcd9380);
2752
2753 static const struct soc_enum rx_hph_mode_mux_enum =
2754 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2755 rx_hph_mode_mux_text);
2756
2757 static const struct soc_enum adc2_enum =
2758 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
2759 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2760
2761 static const struct soc_enum adc3_enum =
2762 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
2763 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
2764
2765 static const struct soc_enum adc4_enum =
2766 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
2767 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
2768
2769 static const struct soc_enum hdr12_enum =
2770 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
2771 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
2772
2773 static const struct soc_enum hdr34_enum =
2774 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
2775 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
2776
2777 static const struct soc_enum rdac3_enum =
2778 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2779 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2780
2781 static const struct snd_kcontrol_new adc1_switch[] = {
2782 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2783 };
2784
2785 static const struct snd_kcontrol_new adc2_switch[] = {
2786 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2787 };
2788
2789 static const struct snd_kcontrol_new adc3_switch[] = {
2790 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2791 };
2792
2793 static const struct snd_kcontrol_new adc4_switch[] = {
2794 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2795 };
2796
2797 static const struct snd_kcontrol_new dmic1_switch[] = {
2798 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2799 };
2800
2801 static const struct snd_kcontrol_new dmic2_switch[] = {
2802 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2803 };
2804
2805 static const struct snd_kcontrol_new dmic3_switch[] = {
2806 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2807 };
2808
2809 static const struct snd_kcontrol_new dmic4_switch[] = {
2810 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2811 };
2812
2813 static const struct snd_kcontrol_new dmic5_switch[] = {
2814 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2815 };
2816
2817 static const struct snd_kcontrol_new dmic6_switch[] = {
2818 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2819 };
2820
2821 static const struct snd_kcontrol_new dmic7_switch[] = {
2822 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2823 };
2824
2825 static const struct snd_kcontrol_new dmic8_switch[] = {
2826 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2827 };
2828
2829 static const struct snd_kcontrol_new ear_rdac_switch[] = {
2830 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2831 };
2832
2833 static const struct snd_kcontrol_new aux_rdac_switch[] = {
2834 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2835 };
2836
2837 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2838 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2839 };
2840
2841 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2842 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2843 };
2844
2845 static const struct snd_kcontrol_new tx_adc2_mux =
2846 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2847
2848 static const struct snd_kcontrol_new tx_adc3_mux =
2849 SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
2850
2851 static const struct snd_kcontrol_new tx_adc4_mux =
2852 SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
2853
2854 static const struct snd_kcontrol_new tx_hdr12_mux =
2855 SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
2856
2857 static const struct snd_kcontrol_new tx_hdr34_mux =
2858 SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
2859
2860 static const struct snd_kcontrol_new rx_rdac3_mux =
2861 SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2862
2863 static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2864 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2865 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2866 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2867 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2868 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2869 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2870 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2871 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2872 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2873 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2874 };
2875
2876 static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2877 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2878 wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2879 SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2880 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2881 SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2882 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2883 SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2884 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2885 SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2886 wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2887 };
2888
wcd938x_get_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2889 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2890 struct snd_ctl_elem_value *ucontrol)
2891 {
2892 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2893 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2894 struct wcd938x_sdw_priv *wcd;
2895 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2896 int dai_id = mixer->shift;
2897 int portidx, ch_idx = mixer->reg;
2898
2899
2900 wcd = wcd938x->sdw_priv[dai_id];
2901 portidx = wcd->ch_info[ch_idx].port_num;
2902
2903 ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2904
2905 return 0;
2906 }
2907
wcd938x_set_swr_port(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)2908 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2909 struct snd_ctl_elem_value *ucontrol)
2910 {
2911 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2912 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2913 struct wcd938x_sdw_priv *wcd;
2914 struct soc_mixer_control *mixer =
2915 (struct soc_mixer_control *)kcontrol->private_value;
2916 int ch_idx = mixer->reg;
2917 int portidx;
2918 int dai_id = mixer->shift;
2919 bool enable;
2920
2921 wcd = wcd938x->sdw_priv[dai_id];
2922
2923 portidx = wcd->ch_info[ch_idx].port_num;
2924 if (ucontrol->value.integer.value[0])
2925 enable = true;
2926 else
2927 enable = false;
2928
2929 wcd->port_enable[portidx] = enable;
2930
2931 wcd938x_connect_port(wcd, portidx, ch_idx, enable);
2932
2933 return 1;
2934
2935 }
2936
2937 /* MBHC related */
wcd938x_mbhc_clk_setup(struct snd_soc_component * component,bool enable)2938 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
2939 bool enable)
2940 {
2941 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
2942 WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
2943 }
2944
wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component * component,bool enable)2945 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2946 bool enable)
2947 {
2948 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
2949 WCD938X_ANA_MBHC_BIAS_EN, enable);
2950 }
2951
wcd938x_mbhc_program_btn_thr(struct snd_soc_component * component,int * btn_low,int * btn_high,int num_btn,bool is_micbias)2952 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
2953 int *btn_low, int *btn_high,
2954 int num_btn, bool is_micbias)
2955 {
2956 int i, vth;
2957
2958 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2959 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2960 __func__, num_btn);
2961 return;
2962 }
2963
2964 for (i = 0; i < num_btn; i++) {
2965 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2966 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
2967 WCD938X_MBHC_BTN_VTH_MASK, vth);
2968 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
2969 __func__, i, btn_high[i], vth);
2970 }
2971 }
2972
wcd938x_mbhc_micb_en_status(struct snd_soc_component * component,int micb_num)2973 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2974 {
2975 u8 val;
2976
2977 if (micb_num == MIC_BIAS_2) {
2978 val = snd_soc_component_read_field(component,
2979 WCD938X_ANA_MICB2,
2980 WCD938X_ANA_MICB2_ENABLE_MASK);
2981 if (val == WCD938X_MICB_ENABLE)
2982 return true;
2983 }
2984 return false;
2985 }
2986
wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component * component,int pull_up_cur)2987 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2988 int pull_up_cur)
2989 {
2990 /* Default pull up current to 2uA */
2991 if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
2992 pull_up_cur = HS_PULLUP_I_2P0_UA;
2993
2994 snd_soc_component_write_field(component,
2995 WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
2996 WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
2997 }
2998
wcd938x_mbhc_request_micbias(struct snd_soc_component * component,int micb_num,int req)2999 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
3000 int micb_num, int req)
3001 {
3002 return wcd938x_micbias_control(component, micb_num, req, false);
3003 }
3004
wcd938x_mbhc_micb_ramp_control(struct snd_soc_component * component,bool enable)3005 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
3006 bool enable)
3007 {
3008 if (enable) {
3009 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3010 WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
3011 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3012 WCD938X_RAMP_EN_MASK, 1);
3013 } else {
3014 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3015 WCD938X_RAMP_EN_MASK, 0);
3016 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3017 WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
3018 }
3019 }
3020
wcd938x_get_micb_vout_ctl_val(u32 micb_mv)3021 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3022 {
3023 /* min micbias voltage is 1V and maximum is 2.85V */
3024 if (micb_mv < 1000 || micb_mv > 2850)
3025 return -EINVAL;
3026
3027 return (micb_mv - 1000) / 50;
3028 }
3029
wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component * component,int req_volt,int micb_num)3030 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
3031 int req_volt, int micb_num)
3032 {
3033 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3034 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
3035
3036 switch (micb_num) {
3037 case MIC_BIAS_1:
3038 micb_reg = WCD938X_ANA_MICB1;
3039 break;
3040 case MIC_BIAS_2:
3041 micb_reg = WCD938X_ANA_MICB2;
3042 break;
3043 case MIC_BIAS_3:
3044 micb_reg = WCD938X_ANA_MICB3;
3045 break;
3046 case MIC_BIAS_4:
3047 micb_reg = WCD938X_ANA_MICB4;
3048 break;
3049 default:
3050 return -EINVAL;
3051 }
3052 mutex_lock(&wcd938x->micb_lock);
3053 /*
3054 * If requested micbias voltage is same as current micbias
3055 * voltage, then just return. Otherwise, adjust voltage as
3056 * per requested value. If micbias is already enabled, then
3057 * to avoid slow micbias ramp-up or down enable pull-up
3058 * momentarily, change the micbias value and then re-enable
3059 * micbias.
3060 */
3061 micb_en = snd_soc_component_read_field(component, micb_reg,
3062 WCD938X_MICB_EN_MASK);
3063 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
3064 WCD938X_MICB_VOUT_MASK);
3065
3066 req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
3067 if (req_vout_ctl < 0) {
3068 ret = -EINVAL;
3069 goto exit;
3070 }
3071
3072 if (cur_vout_ctl == req_vout_ctl) {
3073 ret = 0;
3074 goto exit;
3075 }
3076
3077 if (micb_en == WCD938X_MICB_ENABLE)
3078 snd_soc_component_write_field(component, micb_reg,
3079 WCD938X_MICB_EN_MASK,
3080 WCD938X_MICB_PULL_UP);
3081
3082 snd_soc_component_write_field(component, micb_reg,
3083 WCD938X_MICB_VOUT_MASK,
3084 req_vout_ctl);
3085
3086 if (micb_en == WCD938X_MICB_ENABLE) {
3087 snd_soc_component_write_field(component, micb_reg,
3088 WCD938X_MICB_EN_MASK,
3089 WCD938X_MICB_ENABLE);
3090 /*
3091 * Add 2ms delay as per HW requirement after enabling
3092 * micbias
3093 */
3094 usleep_range(2000, 2100);
3095 }
3096 exit:
3097 mutex_unlock(&wcd938x->micb_lock);
3098 return ret;
3099 }
3100
wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component * component,int micb_num,bool req_en)3101 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
3102 int micb_num, bool req_en)
3103 {
3104 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3105 int micb_mv;
3106
3107 if (micb_num != MIC_BIAS_2)
3108 return -EINVAL;
3109 /*
3110 * If device tree micbias level is already above the minimum
3111 * voltage needed to detect threshold microphone, then do
3112 * not change the micbias, just return.
3113 */
3114 if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
3115 return 0;
3116
3117 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
3118
3119 return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
3120 }
3121
wcd938x_mbhc_get_result_params(struct wcd938x_priv * wcd938x,s16 * d1_a,u16 noff,int32_t * zdet)3122 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x,
3123 s16 *d1_a, u16 noff,
3124 int32_t *zdet)
3125 {
3126 int i;
3127 int val, val1;
3128 s16 c1;
3129 s32 x1, d1;
3130 int32_t denom;
3131 int minCode_param[] = {
3132 3277, 1639, 820, 410, 205, 103, 52, 26
3133 };
3134
3135 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
3136 for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
3137 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
3138 if (val & 0x80)
3139 break;
3140 }
3141 val = val << 0x8;
3142 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
3143 val |= val1;
3144 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
3145 x1 = WCD938X_MBHC_GET_X1(val);
3146 c1 = WCD938X_MBHC_GET_C1(val);
3147 /* If ramp is not complete, give additional 5ms */
3148 if ((c1 < 2) && x1)
3149 usleep_range(5000, 5050);
3150
3151 if (!c1 || !x1) {
3152 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
3153 __func__, c1, x1);
3154 goto ramp_down;
3155 }
3156 d1 = d1_a[c1];
3157 denom = (x1 * d1) - (1 << (14 - noff));
3158 if (denom > 0)
3159 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom;
3160 else if (x1 < minCode_param[noff])
3161 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
3162
3163 pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
3164 __func__, d1, c1, x1, *zdet);
3165 ramp_down:
3166 i = 0;
3167 while (x1) {
3168 regmap_read(wcd938x->regmap,
3169 WCD938X_ANA_MBHC_RESULT_1, &val);
3170 regmap_read(wcd938x->regmap,
3171 WCD938X_ANA_MBHC_RESULT_2, &val1);
3172 val = val << 0x08;
3173 val |= val1;
3174 x1 = WCD938X_MBHC_GET_X1(val);
3175 i++;
3176 if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
3177 break;
3178 }
3179 }
3180
wcd938x_mbhc_zdet_ramp(struct snd_soc_component * component,struct wcd938x_mbhc_zdet_param * zdet_param,int32_t * zl,int32_t * zr,s16 * d1_a)3181 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
3182 struct wcd938x_mbhc_zdet_param *zdet_param,
3183 int32_t *zl, int32_t *zr, s16 *d1_a)
3184 {
3185 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3186 int32_t zdet = 0;
3187
3188 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3189 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
3190 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
3191 WCD938X_VTH_MASK, zdet_param->btn5);
3192 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
3193 WCD938X_VTH_MASK, zdet_param->btn6);
3194 snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
3195 WCD938X_VTH_MASK, zdet_param->btn7);
3196 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3197 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
3198 snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
3199 0x0F, zdet_param->nshift);
3200
3201 if (!zl)
3202 goto z_right;
3203 /* Start impedance measurement for HPH_L */
3204 regmap_update_bits(wcd938x->regmap,
3205 WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
3206 dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
3207 __func__, zdet_param->noff);
3208 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3209 regmap_update_bits(wcd938x->regmap,
3210 WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
3211
3212 *zl = zdet;
3213
3214 z_right:
3215 if (!zr)
3216 return;
3217 /* Start impedance measurement for HPH_R */
3218 regmap_update_bits(wcd938x->regmap,
3219 WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
3220 dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
3221 __func__, zdet_param->noff);
3222 wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3223 regmap_update_bits(wcd938x->regmap,
3224 WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
3225
3226 *zr = zdet;
3227 }
3228
wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component * component,int32_t * z_val,int flag_l_r)3229 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
3230 int32_t *z_val, int flag_l_r)
3231 {
3232 s16 q1;
3233 int q1_cal;
3234
3235 if (*z_val < (WCD938X_ZDET_VAL_400/1000))
3236 q1 = snd_soc_component_read(component,
3237 WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
3238 else
3239 q1 = snd_soc_component_read(component,
3240 WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
3241 if (q1 & 0x80)
3242 q1_cal = (10000 - ((q1 & 0x7F) * 25));
3243 else
3244 q1_cal = (10000 + (q1 * 25));
3245 if (q1_cal > 0)
3246 *z_val = ((*z_val) * 10000) / q1_cal;
3247 }
3248
wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component * component,uint32_t * zl,uint32_t * zr)3249 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
3250 uint32_t *zl, uint32_t *zr)
3251 {
3252 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3253 s16 reg0, reg1, reg2, reg3, reg4;
3254 int32_t z1L, z1R, z1Ls;
3255 int zMono, z_diff1, z_diff2;
3256 bool is_fsm_disable = false;
3257 struct wcd938x_mbhc_zdet_param zdet_param[] = {
3258 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
3259 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
3260 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
3261 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
3262 };
3263 struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
3264 s16 d1_a[][4] = {
3265 {0, 30, 90, 30},
3266 {0, 30, 30, 5},
3267 {0, 30, 30, 5},
3268 {0, 30, 30, 5},
3269 };
3270 s16 *d1 = NULL;
3271
3272 reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
3273 reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
3274 reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
3275 reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
3276 reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
3277
3278 if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
3279 is_fsm_disable = true;
3280 regmap_update_bits(wcd938x->regmap,
3281 WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
3282 }
3283
3284 /* For NO-jack, disable L_DET_EN before Z-det measurements */
3285 if (wcd938x->mbhc_cfg.hphl_swh)
3286 regmap_update_bits(wcd938x->regmap,
3287 WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
3288
3289 /* Turn off 100k pull down on HPHL */
3290 regmap_update_bits(wcd938x->regmap,
3291 WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
3292
3293 /* Disable surge protection before impedance detection.
3294 * This is done to give correct value for high impedance.
3295 */
3296 regmap_update_bits(wcd938x->regmap,
3297 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
3298 /* 1ms delay needed after disable surge protection */
3299 usleep_range(1000, 1010);
3300
3301 /* First get impedance on Left */
3302 d1 = d1_a[1];
3303 zdet_param_ptr = &zdet_param[1];
3304 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3305
3306 if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
3307 goto left_ch_impedance;
3308
3309 /* Second ramp for left ch */
3310 if (z1L < WCD938X_ZDET_VAL_32) {
3311 zdet_param_ptr = &zdet_param[0];
3312 d1 = d1_a[0];
3313 } else if ((z1L > WCD938X_ZDET_VAL_400) &&
3314 (z1L <= WCD938X_ZDET_VAL_1200)) {
3315 zdet_param_ptr = &zdet_param[2];
3316 d1 = d1_a[2];
3317 } else if (z1L > WCD938X_ZDET_VAL_1200) {
3318 zdet_param_ptr = &zdet_param[3];
3319 d1 = d1_a[3];
3320 }
3321 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3322
3323 left_ch_impedance:
3324 if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3325 (z1L > WCD938X_ZDET_VAL_100K)) {
3326 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
3327 zdet_param_ptr = &zdet_param[1];
3328 d1 = d1_a[1];
3329 } else {
3330 *zl = z1L/1000;
3331 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
3332 }
3333 dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
3334 __func__, *zl);
3335
3336 /* Start of right impedance ramp and calculation */
3337 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3338 if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
3339 if (((z1R > WCD938X_ZDET_VAL_1200) &&
3340 (zdet_param_ptr->noff == 0x6)) ||
3341 ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
3342 goto right_ch_impedance;
3343 /* Second ramp for right ch */
3344 if (z1R < WCD938X_ZDET_VAL_32) {
3345 zdet_param_ptr = &zdet_param[0];
3346 d1 = d1_a[0];
3347 } else if ((z1R > WCD938X_ZDET_VAL_400) &&
3348 (z1R <= WCD938X_ZDET_VAL_1200)) {
3349 zdet_param_ptr = &zdet_param[2];
3350 d1 = d1_a[2];
3351 } else if (z1R > WCD938X_ZDET_VAL_1200) {
3352 zdet_param_ptr = &zdet_param[3];
3353 d1 = d1_a[3];
3354 }
3355 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3356 }
3357 right_ch_impedance:
3358 if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3359 (z1R > WCD938X_ZDET_VAL_100K)) {
3360 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
3361 } else {
3362 *zr = z1R/1000;
3363 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
3364 }
3365 dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
3366 __func__, *zr);
3367
3368 /* Mono/stereo detection */
3369 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
3370 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
3371 dev_dbg(component->dev,
3372 "%s: plug type is invalid or extension cable\n",
3373 __func__);
3374 goto zdet_complete;
3375 }
3376 if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3377 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3378 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
3379 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
3380 dev_dbg(component->dev,
3381 "%s: Mono plug type with one ch floating or shorted to GND\n",
3382 __func__);
3383 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3384 goto zdet_complete;
3385 }
3386 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3387 WCD938X_HPHPA_GND_OVR_MASK, 1);
3388 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3389 WCD938X_HPHPA_GND_R_MASK, 1);
3390 if (*zl < (WCD938X_ZDET_VAL_32/1000))
3391 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
3392 else
3393 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
3394 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3395 WCD938X_HPHPA_GND_R_MASK, 0);
3396 snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3397 WCD938X_HPHPA_GND_OVR_MASK, 0);
3398 z1Ls /= 1000;
3399 wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
3400 /* Parallel of left Z and 9 ohm pull down resistor */
3401 zMono = ((*zl) * 9) / ((*zl) + 9);
3402 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
3403 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
3404 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
3405 dev_dbg(component->dev, "%s: stereo plug type detected\n",
3406 __func__);
3407 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
3408 } else {
3409 dev_dbg(component->dev, "%s: MONO plug type detected\n",
3410 __func__);
3411 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3412 }
3413
3414 /* Enable surge protection again after impedance detection */
3415 regmap_update_bits(wcd938x->regmap,
3416 WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
3417 zdet_complete:
3418 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
3419 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
3420 snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
3421 /* Turn on 100k pull down on HPHL */
3422 regmap_update_bits(wcd938x->regmap,
3423 WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
3424
3425 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
3426 if (wcd938x->mbhc_cfg.hphl_swh)
3427 regmap_update_bits(wcd938x->regmap,
3428 WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
3429
3430 snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
3431 snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
3432 if (is_fsm_disable)
3433 regmap_update_bits(wcd938x->regmap,
3434 WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
3435 }
3436
wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component * component,bool enable)3437 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
3438 bool enable)
3439 {
3440 if (enable) {
3441 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3442 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
3443 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3444 WCD938X_MBHC_GND_DET_EN_MASK, 1);
3445 } else {
3446 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3447 WCD938X_MBHC_GND_DET_EN_MASK, 0);
3448 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3449 WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
3450 }
3451 }
3452
wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component * component,bool enable)3453 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
3454 bool enable)
3455 {
3456 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3457 WCD938X_HPHPA_GND_R_MASK, enable);
3458 snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3459 WCD938X_HPHPA_GND_L_MASK, enable);
3460 }
3461
wcd938x_mbhc_moisture_config(struct snd_soc_component * component)3462 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
3463 {
3464 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3465
3466 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3467 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3468 WCD938X_M_RTH_CTL_MASK, R_OFF);
3469 return;
3470 }
3471
3472 /* Do not enable moisture detection if jack type is NC */
3473 if (!wcd938x->mbhc_cfg.hphl_swh) {
3474 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3475 __func__);
3476 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3477 WCD938X_M_RTH_CTL_MASK, R_OFF);
3478 return;
3479 }
3480
3481 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3482 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3483 }
3484
wcd938x_mbhc_moisture_detect_en(struct snd_soc_component * component,bool enable)3485 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
3486 {
3487 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3488
3489 if (enable)
3490 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3491 WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3492 else
3493 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3494 WCD938X_M_RTH_CTL_MASK, R_OFF);
3495 }
3496
wcd938x_mbhc_get_moisture_status(struct snd_soc_component * component)3497 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
3498 {
3499 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3500 bool ret = false;
3501
3502 if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3503 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3504 WCD938X_M_RTH_CTL_MASK, R_OFF);
3505 goto done;
3506 }
3507
3508 /* Do not enable moisture detection if jack type is NC */
3509 if (!wcd938x->mbhc_cfg.hphl_swh) {
3510 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3511 __func__);
3512 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3513 WCD938X_M_RTH_CTL_MASK, R_OFF);
3514 goto done;
3515 }
3516
3517 /*
3518 * If moisture_en is already enabled, then skip to plug type
3519 * detection.
3520 */
3521 if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
3522 goto done;
3523
3524 wcd938x_mbhc_moisture_detect_en(component, true);
3525 /* Read moisture comparator status */
3526 ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
3527 & 0x20) ? 0 : 1);
3528
3529 done:
3530 return ret;
3531
3532 }
3533
wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component * component,bool enable)3534 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
3535 bool enable)
3536 {
3537 snd_soc_component_write_field(component,
3538 WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
3539 WCD938X_MOISTURE_EN_POLLING_MASK, enable);
3540 }
3541
3542 static const struct wcd_mbhc_cb mbhc_cb = {
3543 .clk_setup = wcd938x_mbhc_clk_setup,
3544 .mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
3545 .set_btn_thr = wcd938x_mbhc_program_btn_thr,
3546 .micbias_enable_status = wcd938x_mbhc_micb_en_status,
3547 .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
3548 .mbhc_micbias_control = wcd938x_mbhc_request_micbias,
3549 .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
3550 .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
3551 .compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
3552 .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
3553 .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
3554 .mbhc_moisture_config = wcd938x_mbhc_moisture_config,
3555 .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
3556 .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
3557 .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
3558 };
3559
wcd938x_get_hph_type(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3560 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
3561 struct snd_ctl_elem_value *ucontrol)
3562 {
3563 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3564 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3565
3566 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
3567
3568 return 0;
3569 }
3570
wcd938x_hph_impedance_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)3571 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
3572 struct snd_ctl_elem_value *ucontrol)
3573 {
3574 uint32_t zl, zr;
3575 bool hphr;
3576 struct soc_mixer_control *mc;
3577 struct snd_soc_component *component =
3578 snd_soc_kcontrol_component(kcontrol);
3579 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3580
3581 mc = (struct soc_mixer_control *)(kcontrol->private_value);
3582 hphr = mc->shift;
3583 wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
3584 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
3585 ucontrol->value.integer.value[0] = hphr ? zr : zl;
3586
3587 return 0;
3588 }
3589
3590 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3591 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
3592 wcd938x_get_hph_type, NULL),
3593 };
3594
3595 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3596 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3597 wcd938x_hph_impedance_get, NULL),
3598 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3599 wcd938x_hph_impedance_get, NULL),
3600 };
3601
wcd938x_mbhc_init(struct snd_soc_component * component)3602 static int wcd938x_mbhc_init(struct snd_soc_component *component)
3603 {
3604 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3605 struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
3606
3607 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3608 WCD938X_IRQ_MBHC_SW_DET);
3609 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3610 WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
3611 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3612 WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
3613 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3614 WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3615 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3616 WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
3617 intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3618 WCD938X_IRQ_HPHL_OCP_INT);
3619 intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3620 WCD938X_IRQ_HPHR_OCP_INT);
3621
3622 wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3623
3624 snd_soc_add_component_controls(component, impedance_detect_controls,
3625 ARRAY_SIZE(impedance_detect_controls));
3626 snd_soc_add_component_controls(component, hph_type_detect_controls,
3627 ARRAY_SIZE(hph_type_detect_controls));
3628
3629 return 0;
3630 }
3631 /* END MBHC */
3632
3633 static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
3634 SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
3635 wcd938x_get_compander, wcd938x_set_compander),
3636 SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
3637 wcd938x_get_compander, wcd938x_set_compander),
3638 SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
3639 wcd938x_get_swr_port, wcd938x_set_swr_port),
3640 SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
3641 wcd938x_get_swr_port, wcd938x_set_swr_port),
3642 SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
3643 wcd938x_get_swr_port, wcd938x_set_swr_port),
3644 SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
3645 wcd938x_get_swr_port, wcd938x_set_swr_port),
3646 SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
3647 wcd938x_get_swr_port, wcd938x_set_swr_port),
3648 SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
3649 wcd938x_get_swr_port, wcd938x_set_swr_port),
3650 SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
3651 SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
3652 WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
3653 2, 0x10, 0, ear_pa_gain),
3654 SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
3655 wcd938x_get_swr_port, wcd938x_set_swr_port),
3656 SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
3657 wcd938x_get_swr_port, wcd938x_set_swr_port),
3658 SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
3659 wcd938x_get_swr_port, wcd938x_set_swr_port),
3660 SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
3661 wcd938x_get_swr_port, wcd938x_set_swr_port),
3662 SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
3663 wcd938x_get_swr_port, wcd938x_set_swr_port),
3664 SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
3665 wcd938x_get_swr_port, wcd938x_set_swr_port),
3666 SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
3667 wcd938x_get_swr_port, wcd938x_set_swr_port),
3668 SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
3669 wcd938x_get_swr_port, wcd938x_set_swr_port),
3670 SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
3671 wcd938x_get_swr_port, wcd938x_set_swr_port),
3672 SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
3673 wcd938x_get_swr_port, wcd938x_set_swr_port),
3674 SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
3675 wcd938x_get_swr_port, wcd938x_set_swr_port),
3676 SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
3677 wcd938x_get_swr_port, wcd938x_set_swr_port),
3678 SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
3679 wcd938x_get_swr_port, wcd938x_set_swr_port),
3680 SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
3681 wcd938x_ldoh_get, wcd938x_ldoh_put),
3682 SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
3683 wcd938x_bcs_get, wcd938x_bcs_put),
3684
3685 SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
3686 SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
3687 SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
3688 SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
3689 };
3690
3691 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
3692
3693 /*input widgets*/
3694 SND_SOC_DAPM_INPUT("AMIC1"),
3695 SND_SOC_DAPM_INPUT("AMIC2"),
3696 SND_SOC_DAPM_INPUT("AMIC3"),
3697 SND_SOC_DAPM_INPUT("AMIC4"),
3698 SND_SOC_DAPM_INPUT("AMIC5"),
3699 SND_SOC_DAPM_INPUT("AMIC6"),
3700 SND_SOC_DAPM_INPUT("AMIC7"),
3701 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
3702 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
3703 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
3704 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
3705 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
3706
3707 /*tx widgets*/
3708 SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
3709 wcd938x_codec_enable_adc,
3710 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3711 SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
3712 wcd938x_codec_enable_adc,
3713 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3714 SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
3715 wcd938x_codec_enable_adc,
3716 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3717 SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
3718 wcd938x_codec_enable_adc,
3719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3720 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
3721 wcd938x_codec_enable_dmic,
3722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3723 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
3724 wcd938x_codec_enable_dmic,
3725 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3726 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
3727 wcd938x_codec_enable_dmic,
3728 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3729 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
3730 wcd938x_codec_enable_dmic,
3731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3732 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
3733 wcd938x_codec_enable_dmic,
3734 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3735 SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
3736 wcd938x_codec_enable_dmic,
3737 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3738 SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
3739 wcd938x_codec_enable_dmic,
3740 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3741 SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
3742 wcd938x_codec_enable_dmic,
3743 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3744
3745 SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
3746 NULL, 0, wcd938x_adc_enable_req,
3747 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3748 SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
3749 NULL, 0, wcd938x_adc_enable_req,
3750 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3751 SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
3752 NULL, 0, wcd938x_adc_enable_req,
3753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3754 SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
3755 wcd938x_adc_enable_req,
3756 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3757
3758 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
3759 SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
3760 SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
3761 SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
3762 SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
3763
3764 /*tx mixers*/
3765 SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
3766 ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
3767 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3768 SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
3769 ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
3770 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3771 SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
3772 ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
3773 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3774 SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
3775 ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
3776 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3777 SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
3778 ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
3779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3780 SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
3781 ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
3782 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3783 SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
3784 ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
3785 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3786 SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
3787 ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
3788 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3789 SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
3790 ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
3791 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3792 SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
3793 ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
3794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3795 SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
3796 ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
3797 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3798 SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
3799 ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
3800 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3801 /* micbias widgets*/
3802 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3803 wcd938x_codec_enable_micbias,
3804 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3805 SND_SOC_DAPM_POST_PMD),
3806 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3807 wcd938x_codec_enable_micbias,
3808 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3809 SND_SOC_DAPM_POST_PMD),
3810 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3811 wcd938x_codec_enable_micbias,
3812 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3813 SND_SOC_DAPM_POST_PMD),
3814 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3815 wcd938x_codec_enable_micbias,
3816 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3817 SND_SOC_DAPM_POST_PMD),
3818
3819 /* micbias pull up widgets*/
3820 SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3821 wcd938x_codec_enable_micbias_pullup,
3822 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3823 SND_SOC_DAPM_POST_PMD),
3824 SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3825 wcd938x_codec_enable_micbias_pullup,
3826 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3827 SND_SOC_DAPM_POST_PMD),
3828 SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3829 wcd938x_codec_enable_micbias_pullup,
3830 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3831 SND_SOC_DAPM_POST_PMD),
3832 SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3833 wcd938x_codec_enable_micbias_pullup,
3834 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3835 SND_SOC_DAPM_POST_PMD),
3836
3837 /*output widgets tx*/
3838 SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
3839 SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
3840 SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
3841 SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
3842 SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
3843 SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
3844 SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
3845 SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
3846 SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
3847 SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
3848 SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
3849 SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
3850
3851 SND_SOC_DAPM_INPUT("IN1_HPHL"),
3852 SND_SOC_DAPM_INPUT("IN2_HPHR"),
3853 SND_SOC_DAPM_INPUT("IN3_AUX"),
3854
3855 /*rx widgets*/
3856 SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
3857 wcd938x_codec_enable_ear_pa,
3858 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3859 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3860 SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
3861 wcd938x_codec_enable_aux_pa,
3862 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3863 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3864 SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
3865 wcd938x_codec_enable_hphl_pa,
3866 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3867 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3868 SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
3869 wcd938x_codec_enable_hphr_pa,
3870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3871 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3872
3873 SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
3874 wcd938x_codec_hphl_dac_event,
3875 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3876 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3877 SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
3878 wcd938x_codec_hphr_dac_event,
3879 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3880 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3881 SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
3882 wcd938x_codec_ear_dac_event,
3883 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3884 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3885 SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
3886 wcd938x_codec_aux_dac_event,
3887 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3888 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3889
3890 SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
3891
3892 SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
3893 SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
3894 wcd938x_codec_enable_rxclk,
3895 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3896 SND_SOC_DAPM_POST_PMD),
3897
3898 SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
3899
3900 SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3901 SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3902 SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3903
3904 /* rx mixer widgets*/
3905 SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
3906 ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
3907 SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
3908 aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
3909 SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
3910 hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
3911 SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
3912 hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
3913
3914 /*output widgets rx*/
3915 SND_SOC_DAPM_OUTPUT("EAR"),
3916 SND_SOC_DAPM_OUTPUT("AUX"),
3917 SND_SOC_DAPM_OUTPUT("HPHL"),
3918 SND_SOC_DAPM_OUTPUT("HPHR"),
3919
3920 };
3921
3922 static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
3923 {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
3924 {"ADC1_MIXER", "Switch", "ADC1 REQ"},
3925 {"ADC1 REQ", NULL, "ADC1"},
3926 {"ADC1", NULL, "AMIC1"},
3927
3928 {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
3929 {"ADC2_MIXER", "Switch", "ADC2 REQ"},
3930 {"ADC2 REQ", NULL, "ADC2"},
3931 {"ADC2", NULL, "HDR12 MUX"},
3932 {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
3933 {"HDR12 MUX", "HDR12", "AMIC1"},
3934 {"ADC2 MUX", "INP3", "AMIC3"},
3935 {"ADC2 MUX", "INP2", "AMIC2"},
3936
3937 {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
3938 {"ADC3_MIXER", "Switch", "ADC3 REQ"},
3939 {"ADC3 REQ", NULL, "ADC3"},
3940 {"ADC3", NULL, "HDR34 MUX"},
3941 {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
3942 {"HDR34 MUX", "HDR34", "AMIC5"},
3943 {"ADC3 MUX", "INP4", "AMIC4"},
3944 {"ADC3 MUX", "INP6", "AMIC6"},
3945
3946 {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
3947 {"ADC4_MIXER", "Switch", "ADC4 REQ"},
3948 {"ADC4 REQ", NULL, "ADC4"},
3949 {"ADC4", NULL, "ADC4 MUX"},
3950 {"ADC4 MUX", "INP5", "AMIC5"},
3951 {"ADC4 MUX", "INP7", "AMIC7"},
3952
3953 {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
3954 {"DMIC1_MIXER", "Switch", "DMIC1"},
3955
3956 {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
3957 {"DMIC2_MIXER", "Switch", "DMIC2"},
3958
3959 {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
3960 {"DMIC3_MIXER", "Switch", "DMIC3"},
3961
3962 {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
3963 {"DMIC4_MIXER", "Switch", "DMIC4"},
3964
3965 {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
3966 {"DMIC5_MIXER", "Switch", "DMIC5"},
3967
3968 {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
3969 {"DMIC6_MIXER", "Switch", "DMIC6"},
3970
3971 {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
3972 {"DMIC7_MIXER", "Switch", "DMIC7"},
3973
3974 {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
3975 {"DMIC8_MIXER", "Switch", "DMIC8"},
3976
3977 {"IN1_HPHL", NULL, "VDD_BUCK"},
3978 {"IN1_HPHL", NULL, "CLS_H_PORT"},
3979
3980 {"RX1", NULL, "IN1_HPHL"},
3981 {"RX1", NULL, "RXCLK"},
3982 {"RDAC1", NULL, "RX1"},
3983 {"HPHL_RDAC", "Switch", "RDAC1"},
3984 {"HPHL PGA", NULL, "HPHL_RDAC"},
3985 {"HPHL", NULL, "HPHL PGA"},
3986
3987 {"IN2_HPHR", NULL, "VDD_BUCK"},
3988 {"IN2_HPHR", NULL, "CLS_H_PORT"},
3989 {"RX2", NULL, "IN2_HPHR"},
3990 {"RDAC2", NULL, "RX2"},
3991 {"RX2", NULL, "RXCLK"},
3992 {"HPHR_RDAC", "Switch", "RDAC2"},
3993 {"HPHR PGA", NULL, "HPHR_RDAC"},
3994 {"HPHR", NULL, "HPHR PGA"},
3995
3996 {"IN3_AUX", NULL, "VDD_BUCK"},
3997 {"IN3_AUX", NULL, "CLS_H_PORT"},
3998 {"RX3", NULL, "IN3_AUX"},
3999 {"RDAC4", NULL, "RX3"},
4000 {"RX3", NULL, "RXCLK"},
4001 {"AUX_RDAC", "Switch", "RDAC4"},
4002 {"AUX PGA", NULL, "AUX_RDAC"},
4003 {"AUX", NULL, "AUX PGA"},
4004
4005 {"RDAC3_MUX", "RX3", "RX3"},
4006 {"RDAC3_MUX", "RX1", "RX1"},
4007 {"RDAC3", NULL, "RDAC3_MUX"},
4008 {"EAR_RDAC", "Switch", "RDAC3"},
4009 {"EAR PGA", NULL, "EAR_RDAC"},
4010 {"EAR", NULL, "EAR PGA"},
4011 };
4012
wcd938x_set_micbias_data(struct wcd938x_priv * wcd938x)4013 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
4014 {
4015 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
4016
4017 /* set micbias voltage */
4018 vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
4019 vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
4020 vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
4021 vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
4022 if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
4023 return -EINVAL;
4024
4025 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
4026 WCD938X_MICB_VOUT_MASK, vout_ctl_1);
4027 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
4028 WCD938X_MICB_VOUT_MASK, vout_ctl_2);
4029 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
4030 WCD938X_MICB_VOUT_MASK, vout_ctl_3);
4031 regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
4032 WCD938X_MICB_VOUT_MASK, vout_ctl_4);
4033
4034 return 0;
4035 }
4036
wcd938x_wd_handle_irq(int irq,void * data)4037 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
4038 {
4039 return IRQ_HANDLED;
4040 }
4041
4042 static struct irq_chip wcd_irq_chip = {
4043 .name = "WCD938x",
4044 };
4045
wcd_irq_chip_map(struct irq_domain * irqd,unsigned int virq,irq_hw_number_t hw)4046 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
4047 irq_hw_number_t hw)
4048 {
4049 irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
4050 irq_set_nested_thread(virq, 1);
4051 irq_set_noprobe(virq);
4052
4053 return 0;
4054 }
4055
4056 static const struct irq_domain_ops wcd_domain_ops = {
4057 .map = wcd_irq_chip_map,
4058 };
4059
wcd938x_irq_init(struct wcd938x_priv * wcd,struct device * dev)4060 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
4061 {
4062
4063 wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
4064 if (!(wcd->virq)) {
4065 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
4066 return -EINVAL;
4067 }
4068
4069 return devm_regmap_add_irq_chip(dev, wcd->regmap,
4070 irq_create_mapping(wcd->virq, 0),
4071 IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
4072 &wcd->irq_chip);
4073 }
4074
wcd938x_soc_codec_probe(struct snd_soc_component * component)4075 static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
4076 {
4077 struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
4078 struct device *dev = component->dev;
4079 int ret, i;
4080
4081 snd_soc_component_init_regmap(component, wcd938x->regmap);
4082
4083 wcd938x->variant = snd_soc_component_read_field(component,
4084 WCD938X_DIGITAL_EFUSE_REG_0,
4085 WCD938X_ID_MASK);
4086
4087 wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
4088
4089 wcd938x_io_init(wcd938x);
4090 /* Set all interrupts as edge triggered */
4091 for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
4092 regmap_write(wcd938x->regmap,
4093 (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
4094 }
4095
4096 wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4097 WCD938X_IRQ_HPHR_PDM_WD_INT);
4098 wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4099 WCD938X_IRQ_HPHL_PDM_WD_INT);
4100 wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4101 WCD938X_IRQ_AUX_PDM_WD_INT);
4102
4103 /* Request for watchdog interrupt */
4104 ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4105 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4106 "HPHR PDM WD INT", wcd938x);
4107 if (ret)
4108 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
4109
4110 ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4111 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4112 "HPHL PDM WD INT", wcd938x);
4113 if (ret)
4114 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
4115
4116 ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4117 IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4118 "AUX PDM WD INT", wcd938x);
4119 if (ret)
4120 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
4121
4122 /* Disable watchdog interrupt for HPH and AUX */
4123 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
4124 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
4125 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
4126
4127 switch (wcd938x->variant) {
4128 case WCD9380:
4129 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
4130 ARRAY_SIZE(wcd9380_snd_controls));
4131 if (ret < 0) {
4132 dev_err(component->dev,
4133 "%s: Failed to add snd ctrls for variant: %d\n",
4134 __func__, wcd938x->variant);
4135 goto err;
4136 }
4137 break;
4138 case WCD9385:
4139 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
4140 ARRAY_SIZE(wcd9385_snd_controls));
4141 if (ret < 0) {
4142 dev_err(component->dev,
4143 "%s: Failed to add snd ctrls for variant: %d\n",
4144 __func__, wcd938x->variant);
4145 goto err;
4146 }
4147 break;
4148 default:
4149 break;
4150 }
4151
4152 ret = wcd938x_mbhc_init(component);
4153 if (ret)
4154 dev_err(component->dev, "mbhc initialization failed\n");
4155 err:
4156 return ret;
4157 }
4158
wcd938x_codec_set_jack(struct snd_soc_component * comp,struct snd_soc_jack * jack,void * data)4159 static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
4160 struct snd_soc_jack *jack, void *data)
4161 {
4162 struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
4163
4164 if (jack)
4165 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
4166 else
4167 wcd_mbhc_stop(wcd->wcd_mbhc);
4168
4169 return 0;
4170 }
4171
4172 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
4173 .name = "wcd938x_codec",
4174 .probe = wcd938x_soc_codec_probe,
4175 .controls = wcd938x_snd_controls,
4176 .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
4177 .dapm_widgets = wcd938x_dapm_widgets,
4178 .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
4179 .dapm_routes = wcd938x_audio_map,
4180 .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
4181 .set_jack = wcd938x_codec_set_jack,
4182 .endianness = 1,
4183 };
4184
wcd938x_dt_parse_micbias_info(struct device * dev,struct wcd938x_priv * wcd)4185 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
4186 {
4187 struct device_node *np = dev->of_node;
4188 u32 prop_val = 0;
4189 int rc = 0;
4190
4191 rc = of_property_read_u32(np, "qcom,micbias1-microvolt", &prop_val);
4192 if (!rc)
4193 wcd->micb1_mv = prop_val/1000;
4194 else
4195 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
4196
4197 rc = of_property_read_u32(np, "qcom,micbias2-microvolt", &prop_val);
4198 if (!rc)
4199 wcd->micb2_mv = prop_val/1000;
4200 else
4201 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
4202
4203 rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
4204 if (!rc)
4205 wcd->micb3_mv = prop_val/1000;
4206 else
4207 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
4208
4209 rc = of_property_read_u32(np, "qcom,micbias4-microvolt", &prop_val);
4210 if (!rc)
4211 wcd->micb4_mv = prop_val/1000;
4212 else
4213 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
4214 }
4215
wcd938x_swap_gnd_mic(struct snd_soc_component * component,bool active)4216 static bool wcd938x_swap_gnd_mic(struct snd_soc_component *component, bool active)
4217 {
4218 int value;
4219
4220 struct wcd938x_priv *wcd938x;
4221
4222 wcd938x = snd_soc_component_get_drvdata(component);
4223
4224 value = gpiod_get_value(wcd938x->us_euro_gpio);
4225
4226 gpiod_set_value(wcd938x->us_euro_gpio, !value);
4227
4228 return true;
4229 }
4230
4231
wcd938x_populate_dt_data(struct wcd938x_priv * wcd938x,struct device * dev)4232 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
4233 {
4234 struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
4235 int ret;
4236
4237 wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
4238 if (wcd938x->reset_gpio < 0) {
4239 dev_err(dev, "Failed to get reset gpio: err = %d\n",
4240 wcd938x->reset_gpio);
4241 return wcd938x->reset_gpio;
4242 }
4243
4244 wcd938x->us_euro_gpio = devm_gpiod_get_optional(dev, "us-euro",
4245 GPIOD_OUT_LOW);
4246 if (IS_ERR(wcd938x->us_euro_gpio)) {
4247 dev_err(dev, "us-euro swap Control GPIO not found\n");
4248 return PTR_ERR(wcd938x->us_euro_gpio);
4249 }
4250
4251 cfg->swap_gnd_mic = wcd938x_swap_gnd_mic;
4252
4253 wcd938x->supplies[0].supply = "vdd-rxtx";
4254 wcd938x->supplies[1].supply = "vdd-io";
4255 wcd938x->supplies[2].supply = "vdd-buck";
4256 wcd938x->supplies[3].supply = "vdd-mic-bias";
4257
4258 ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
4259 if (ret) {
4260 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
4261 return ret;
4262 }
4263
4264 ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
4265 if (ret) {
4266 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
4267 return ret;
4268 }
4269
4270 wcd938x_dt_parse_micbias_info(dev, wcd938x);
4271
4272 cfg->mbhc_micbias = MIC_BIAS_2;
4273 cfg->anc_micbias = MIC_BIAS_2;
4274 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
4275 cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
4276 cfg->micb_mv = wcd938x->micb2_mv;
4277 cfg->linein_th = 5000;
4278 cfg->hs_thr = 1700;
4279 cfg->hph_thr = 50;
4280
4281 wcd_dt_parse_mbhc_data(dev, cfg);
4282
4283 return 0;
4284 }
4285
wcd938x_reset(struct wcd938x_priv * wcd938x)4286 static int wcd938x_reset(struct wcd938x_priv *wcd938x)
4287 {
4288 gpio_direction_output(wcd938x->reset_gpio, 0);
4289 /* 20us sleep required after pulling the reset gpio to LOW */
4290 usleep_range(20, 30);
4291 gpio_set_value(wcd938x->reset_gpio, 1);
4292 /* 20us sleep required after pulling the reset gpio to HIGH */
4293 usleep_range(20, 30);
4294
4295 return 0;
4296 }
4297
wcd938x_codec_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)4298 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
4299 struct snd_pcm_hw_params *params,
4300 struct snd_soc_dai *dai)
4301 {
4302 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4303 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4304
4305 return wcd938x_sdw_hw_params(wcd, substream, params, dai);
4306 }
4307
wcd938x_codec_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)4308 static int wcd938x_codec_free(struct snd_pcm_substream *substream,
4309 struct snd_soc_dai *dai)
4310 {
4311 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4312 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4313
4314 return wcd938x_sdw_free(wcd, substream, dai);
4315 }
4316
wcd938x_codec_set_sdw_stream(struct snd_soc_dai * dai,void * stream,int direction)4317 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
4318 void *stream, int direction)
4319 {
4320 struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4321 struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4322
4323 return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
4324
4325 }
4326
4327 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
4328 .hw_params = wcd938x_codec_hw_params,
4329 .hw_free = wcd938x_codec_free,
4330 .set_stream = wcd938x_codec_set_sdw_stream,
4331 };
4332
4333 static struct snd_soc_dai_driver wcd938x_dais[] = {
4334 [0] = {
4335 .name = "wcd938x-sdw-rx",
4336 .playback = {
4337 .stream_name = "WCD AIF1 Playback",
4338 .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
4339 .formats = WCD938X_FORMATS_S16_S24_LE,
4340 .rate_max = 192000,
4341 .rate_min = 8000,
4342 .channels_min = 1,
4343 .channels_max = 2,
4344 },
4345 .ops = &wcd938x_sdw_dai_ops,
4346 },
4347 [1] = {
4348 .name = "wcd938x-sdw-tx",
4349 .capture = {
4350 .stream_name = "WCD AIF1 Capture",
4351 .rates = WCD938X_RATES_MASK,
4352 .formats = SNDRV_PCM_FMTBIT_S16_LE,
4353 .rate_min = 8000,
4354 .rate_max = 192000,
4355 .channels_min = 1,
4356 .channels_max = 4,
4357 },
4358 .ops = &wcd938x_sdw_dai_ops,
4359 },
4360 };
4361
wcd938x_bind(struct device * dev)4362 static int wcd938x_bind(struct device *dev)
4363 {
4364 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4365 int ret;
4366
4367 ret = component_bind_all(dev, wcd938x);
4368 if (ret) {
4369 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
4370 __func__, ret);
4371 return ret;
4372 }
4373
4374 wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
4375 if (!wcd938x->rxdev) {
4376 dev_err(dev, "could not find slave with matching of node\n");
4377 return -EINVAL;
4378 }
4379 wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
4380 wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
4381
4382 wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
4383 if (!wcd938x->txdev) {
4384 dev_err(dev, "could not find txslave with matching of node\n");
4385 return -EINVAL;
4386 }
4387 wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
4388 wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
4389 wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
4390 if (!wcd938x->tx_sdw_dev) {
4391 dev_err(dev, "could not get txslave with matching of dev\n");
4392 return -EINVAL;
4393 }
4394
4395 /* As TX is main CSR reg interface, which should not be suspended first.
4396 * expicilty add the dependency link */
4397 if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
4398 DL_FLAG_PM_RUNTIME)) {
4399 dev_err(dev, "could not devlink tx and rx\n");
4400 return -EINVAL;
4401 }
4402
4403 if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
4404 DL_FLAG_PM_RUNTIME)) {
4405 dev_err(dev, "could not devlink wcd and tx\n");
4406 return -EINVAL;
4407 }
4408
4409 if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
4410 DL_FLAG_PM_RUNTIME)) {
4411 dev_err(dev, "could not devlink wcd and rx\n");
4412 return -EINVAL;
4413 }
4414
4415 wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
4416 if (IS_ERR(wcd938x->regmap)) {
4417 dev_err(dev, "%s: tx csr regmap not found\n", __func__);
4418 return PTR_ERR(wcd938x->regmap);
4419 }
4420
4421 ret = wcd938x_irq_init(wcd938x, dev);
4422 if (ret) {
4423 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
4424 return ret;
4425 }
4426
4427 wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
4428 wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
4429
4430 ret = wcd938x_set_micbias_data(wcd938x);
4431 if (ret < 0) {
4432 dev_err(dev, "%s: bad micbias pdata\n", __func__);
4433 return ret;
4434 }
4435
4436 ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
4437 wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
4438 if (ret)
4439 dev_err(dev, "%s: Codec registration failed\n",
4440 __func__);
4441
4442 return ret;
4443
4444 }
4445
wcd938x_unbind(struct device * dev)4446 static void wcd938x_unbind(struct device *dev)
4447 {
4448 struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4449
4450 device_link_remove(dev, wcd938x->txdev);
4451 device_link_remove(dev, wcd938x->rxdev);
4452 device_link_remove(wcd938x->rxdev, wcd938x->txdev);
4453 snd_soc_unregister_component(dev);
4454 component_unbind_all(dev, wcd938x);
4455 }
4456
4457 static const struct component_master_ops wcd938x_comp_ops = {
4458 .bind = wcd938x_bind,
4459 .unbind = wcd938x_unbind,
4460 };
4461
wcd938x_add_slave_components(struct wcd938x_priv * wcd938x,struct device * dev,struct component_match ** matchptr)4462 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
4463 struct device *dev,
4464 struct component_match **matchptr)
4465 {
4466 struct device_node *np;
4467
4468 np = dev->of_node;
4469
4470 wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
4471 if (!wcd938x->rxnode) {
4472 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
4473 return -ENODEV;
4474 }
4475
4476 of_node_get(wcd938x->rxnode);
4477 component_match_add_release(dev, matchptr, component_release_of,
4478 component_compare_of, wcd938x->rxnode);
4479
4480 wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
4481 if (!wcd938x->txnode) {
4482 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
4483 return -ENODEV;
4484 }
4485 of_node_get(wcd938x->txnode);
4486 component_match_add_release(dev, matchptr, component_release_of,
4487 component_compare_of, wcd938x->txnode);
4488 return 0;
4489 }
4490
wcd938x_probe(struct platform_device * pdev)4491 static int wcd938x_probe(struct platform_device *pdev)
4492 {
4493 struct component_match *match = NULL;
4494 struct wcd938x_priv *wcd938x = NULL;
4495 struct device *dev = &pdev->dev;
4496 int ret;
4497
4498 wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
4499 GFP_KERNEL);
4500 if (!wcd938x)
4501 return -ENOMEM;
4502
4503 dev_set_drvdata(dev, wcd938x);
4504 mutex_init(&wcd938x->micb_lock);
4505
4506 ret = wcd938x_populate_dt_data(wcd938x, dev);
4507 if (ret) {
4508 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
4509 return -EINVAL;
4510 }
4511
4512 ret = wcd938x_add_slave_components(wcd938x, dev, &match);
4513 if (ret)
4514 return ret;
4515
4516 wcd938x_reset(wcd938x);
4517
4518 ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
4519 if (ret)
4520 return ret;
4521
4522 pm_runtime_set_autosuspend_delay(dev, 1000);
4523 pm_runtime_use_autosuspend(dev);
4524 pm_runtime_mark_last_busy(dev);
4525 pm_runtime_set_active(dev);
4526 pm_runtime_enable(dev);
4527 pm_runtime_idle(dev);
4528
4529 return 0;
4530 }
4531
wcd938x_remove(struct platform_device * pdev)4532 static int wcd938x_remove(struct platform_device *pdev)
4533 {
4534 component_master_del(&pdev->dev, &wcd938x_comp_ops);
4535
4536 return 0;
4537 }
4538
4539 #if defined(CONFIG_OF)
4540 static const struct of_device_id wcd938x_dt_match[] = {
4541 { .compatible = "qcom,wcd9380-codec" },
4542 { .compatible = "qcom,wcd9385-codec" },
4543 {}
4544 };
4545 MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
4546 #endif
4547
4548 static struct platform_driver wcd938x_codec_driver = {
4549 .probe = wcd938x_probe,
4550 .remove = wcd938x_remove,
4551 .driver = {
4552 .name = "wcd938x_codec",
4553 .of_match_table = of_match_ptr(wcd938x_dt_match),
4554 .suppress_bind_attrs = true,
4555 },
4556 };
4557
4558 module_platform_driver(wcd938x_codec_driver);
4559 MODULE_DESCRIPTION("WCD938X Codec driver");
4560 MODULE_LICENSE("GPL");
4561
