Searched refs:VIA_PCI_DMA_CSR1 (Results 1 – 1 of 1) sorted by relevance
360 #define VIA_PCI_DMA_CSR1 0xE94 /* Command/Status Register of Channel 1 */ macro398 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,407 {VIA_IRQ_DMA1_TD_ENABLE, VIA_IRQ_DMA1_TD_PENDING, VIA_PCI_DMA_CSR1,
