Searched refs:VIA_PCI_DMA_CSR0 (Results 1 – 1 of 1) sorted by relevance
| /Linux-v6.1/drivers/gpu/drm/via/ |
| D | via_dri1.c | 359 #define VIA_PCI_DMA_CSR0 0xE90 /* Command/Status Register of Channel 0 */ macro
396 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
405 {VIA_IRQ_DMA0_TD_ENABLE, VIA_IRQ_DMA0_TD_PENDING, VIA_PCI_DMA_CSR0,
1652 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
1658 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
1659 via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04); in via_fire_dmablit()
1725 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); in via_abort_dmablit()
1733 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); in via_dmablit_engine_off()
1761 ((status = via_read(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); in via_dmablit_handler()
1780 via_write(dev_priv, VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); in via_dmablit_handler()
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