Home
last modified time | relevance | path

Searched refs:UVD_MPC_SET_MUXA1__VARA_7__SHIFT (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h611 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Duvd_3_1_sh_mask.h492 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
Duvd_4_0_sh_mask.h511 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c macro
Duvd_4_2_sh_mask.h496 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
Duvd_5_0_sh_mask.h528 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
Duvd_6_0_sh_mask.h530 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1118 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Dvcn_2_5_sh_mask.h2859 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2624 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2851 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3932 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4182 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT … macro