Searched refs:UVD_MPC_SET_MUXA0__VARA_2__SHIFT (Results 1 – 17 of 17) sorted by relevance
600 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
482 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
501 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c macro
486 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
518 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
520 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
1107 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2848 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2613 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
2840 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
3921 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
4171 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT … macro
914 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v4_0_start_dpg_mode()1053 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v4_0_start()
829 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v1_0_start_spg_mode()1012 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v1_0_start_dpg_mode()
842 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_0_start_dpg_mode()977 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_0_start()
824 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start_dpg_mode()978 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v2_5_start()
990 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v3_0_start_dpg_mode()1156 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | in vcn_v3_0_start()
