Home
last modified time | relevance | path

Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT (Results 1 – 17 of 17) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c471 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_disable_clock_gating()
595 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
597 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
656 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
658 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
Dvcn_v2_0.c497 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_disable_clock_gating()
599 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
601 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
657 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
659 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
Dvcn_v2_5.c564 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_disable_clock_gating()
670 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
672 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
729 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
731 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
Dvcn_v3_0.c702 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_disable_clock_gating()
830 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
832 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
886 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
888 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
Dvcn_v4_0.c756 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
811 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_enable_clock_gating()
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h418 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Duvd_3_1_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h37 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h242 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h244 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
/Linux-v6.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h911 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Dvcn_2_5_sh_mask.h1979 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Dvcn_2_0_0_sh_mask.h1929 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3650 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2709 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
Dvcn_4_0_0_sh_mask.h87 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro