1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/of_device.h>
29 #include <linux/io.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* shadow registers */
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 unsigned int ucr4;
218 unsigned int ufcr;
219
220 /* DMA fields */
221 unsigned int dma_is_enabled:1;
222 unsigned int dma_is_rxing:1;
223 unsigned int dma_is_txing:1;
224 struct dma_chan *dma_chan_rx, *dma_chan_tx;
225 struct scatterlist rx_sgl, tx_sgl[2];
226 void *rx_buf;
227 struct circ_buf rx_ring;
228 unsigned int rx_buf_size;
229 unsigned int rx_period_length;
230 unsigned int rx_periods;
231 dma_cookie_t rx_cookie;
232 unsigned int tx_bytes;
233 unsigned int dma_tx_nents;
234 unsigned int saved_reg[10];
235 bool context_saved;
236
237 enum imx_tx_state tx_state;
238 struct hrtimer trigger_start_tx;
239 struct hrtimer trigger_stop_tx;
240 };
241
242 struct imx_port_ucrs {
243 unsigned int ucr1;
244 unsigned int ucr2;
245 unsigned int ucr3;
246 };
247
248 static struct imx_uart_data imx_uart_devdata[] = {
249 [IMX1_UART] = {
250 .uts_reg = IMX1_UTS,
251 .devtype = IMX1_UART,
252 },
253 [IMX21_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX21_UART,
256 },
257 [IMX53_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX53_UART,
260 },
261 [IMX6Q_UART] = {
262 .uts_reg = IMX21_UTS,
263 .devtype = IMX6Q_UART,
264 },
265 };
266
267 static const struct of_device_id imx_uart_dt_ids[] = {
268 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
269 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273 };
274 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)276 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
277 {
278 switch (offset) {
279 case UCR1:
280 sport->ucr1 = val;
281 break;
282 case UCR2:
283 sport->ucr2 = val;
284 break;
285 case UCR3:
286 sport->ucr3 = val;
287 break;
288 case UCR4:
289 sport->ucr4 = val;
290 break;
291 case UFCR:
292 sport->ufcr = val;
293 break;
294 default:
295 break;
296 }
297 writel(val, sport->port.membase + offset);
298 }
299
imx_uart_readl(struct imx_port * sport,u32 offset)300 static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
301 {
302 switch (offset) {
303 case UCR1:
304 return sport->ucr1;
305 break;
306 case UCR2:
307 /*
308 * UCR2_SRST is the only bit in the cached registers that might
309 * differ from the value that was last written. As it only
310 * automatically becomes one after being cleared, reread
311 * conditionally.
312 */
313 if (!(sport->ucr2 & UCR2_SRST))
314 sport->ucr2 = readl(sport->port.membase + offset);
315 return sport->ucr2;
316 break;
317 case UCR3:
318 return sport->ucr3;
319 break;
320 case UCR4:
321 return sport->ucr4;
322 break;
323 case UFCR:
324 return sport->ufcr;
325 break;
326 default:
327 return readl(sport->port.membase + offset);
328 }
329 }
330
imx_uart_uts_reg(struct imx_port * sport)331 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
332 {
333 return sport->devdata->uts_reg;
334 }
335
imx_uart_is_imx1(struct imx_port * sport)336 static inline int imx_uart_is_imx1(struct imx_port *sport)
337 {
338 return sport->devdata->devtype == IMX1_UART;
339 }
340
imx_uart_is_imx21(struct imx_port * sport)341 static inline int imx_uart_is_imx21(struct imx_port *sport)
342 {
343 return sport->devdata->devtype == IMX21_UART;
344 }
345
imx_uart_is_imx53(struct imx_port * sport)346 static inline int imx_uart_is_imx53(struct imx_port *sport)
347 {
348 return sport->devdata->devtype == IMX53_UART;
349 }
350
imx_uart_is_imx6q(struct imx_port * sport)351 static inline int imx_uart_is_imx6q(struct imx_port *sport)
352 {
353 return sport->devdata->devtype == IMX6Q_UART;
354 }
355 /*
356 * Save and restore functions for UCR1, UCR2 and UCR3 registers
357 */
358 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)359 static void imx_uart_ucrs_save(struct imx_port *sport,
360 struct imx_port_ucrs *ucr)
361 {
362 /* save control registers */
363 ucr->ucr1 = imx_uart_readl(sport, UCR1);
364 ucr->ucr2 = imx_uart_readl(sport, UCR2);
365 ucr->ucr3 = imx_uart_readl(sport, UCR3);
366 }
367
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)368 static void imx_uart_ucrs_restore(struct imx_port *sport,
369 struct imx_port_ucrs *ucr)
370 {
371 /* restore control registers */
372 imx_uart_writel(sport, ucr->ucr1, UCR1);
373 imx_uart_writel(sport, ucr->ucr2, UCR2);
374 imx_uart_writel(sport, ucr->ucr3, UCR3);
375 }
376 #endif
377
378 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)379 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
380 {
381 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
382
383 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
384 }
385
386 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)387 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
388 {
389 *ucr2 &= ~UCR2_CTSC;
390 *ucr2 |= UCR2_CTS;
391
392 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
393 }
394
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)395 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
396 {
397 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
398 }
399
400 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)401 static void imx_uart_start_rx(struct uart_port *port)
402 {
403 struct imx_port *sport = (struct imx_port *)port;
404 unsigned int ucr1, ucr2;
405
406 ucr1 = imx_uart_readl(sport, UCR1);
407 ucr2 = imx_uart_readl(sport, UCR2);
408
409 ucr2 |= UCR2_RXEN;
410
411 if (sport->dma_is_enabled) {
412 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
413 } else {
414 ucr1 |= UCR1_RRDYEN;
415 ucr2 |= UCR2_ATEN;
416 }
417
418 /* Write UCR2 first as it includes RXEN */
419 imx_uart_writel(sport, ucr2, UCR2);
420 imx_uart_writel(sport, ucr1, UCR1);
421 }
422
423 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)424 static void imx_uart_stop_tx(struct uart_port *port)
425 {
426 struct imx_port *sport = (struct imx_port *)port;
427 u32 ucr1, ucr4, usr2;
428
429 if (sport->tx_state == OFF)
430 return;
431
432 /*
433 * We are maybe in the SMP context, so if the DMA TX thread is running
434 * on other cpu, we have to wait for it to finish.
435 */
436 if (sport->dma_is_txing)
437 return;
438
439 ucr1 = imx_uart_readl(sport, UCR1);
440 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
441
442 usr2 = imx_uart_readl(sport, USR2);
443 if (!(usr2 & USR2_TXDC)) {
444 /* The shifter is still busy, so retry once TC triggers */
445 return;
446 }
447
448 ucr4 = imx_uart_readl(sport, UCR4);
449 ucr4 &= ~UCR4_TCEN;
450 imx_uart_writel(sport, ucr4, UCR4);
451
452 /* in rs485 mode disable transmitter */
453 if (port->rs485.flags & SER_RS485_ENABLED) {
454 if (sport->tx_state == SEND) {
455 sport->tx_state = WAIT_AFTER_SEND;
456
457 if (port->rs485.delay_rts_after_send > 0) {
458 start_hrtimer_ms(&sport->trigger_stop_tx,
459 port->rs485.delay_rts_after_send);
460 return;
461 }
462
463 /* continue without any delay */
464 }
465
466 if (sport->tx_state == WAIT_AFTER_RTS ||
467 sport->tx_state == WAIT_AFTER_SEND) {
468 u32 ucr2;
469
470 hrtimer_try_to_cancel(&sport->trigger_start_tx);
471
472 ucr2 = imx_uart_readl(sport, UCR2);
473 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
474 imx_uart_rts_active(sport, &ucr2);
475 else
476 imx_uart_rts_inactive(sport, &ucr2);
477 imx_uart_writel(sport, ucr2, UCR2);
478
479 imx_uart_start_rx(port);
480
481 sport->tx_state = OFF;
482 }
483 } else {
484 sport->tx_state = OFF;
485 }
486 }
487
488 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)489 static void imx_uart_stop_rx(struct uart_port *port)
490 {
491 struct imx_port *sport = (struct imx_port *)port;
492 u32 ucr1, ucr2, ucr4;
493
494 ucr1 = imx_uart_readl(sport, UCR1);
495 ucr2 = imx_uart_readl(sport, UCR2);
496 ucr4 = imx_uart_readl(sport, UCR4);
497
498 if (sport->dma_is_enabled) {
499 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
500 } else {
501 ucr1 &= ~UCR1_RRDYEN;
502 ucr2 &= ~UCR2_ATEN;
503 ucr4 &= ~UCR4_OREN;
504 }
505 imx_uart_writel(sport, ucr1, UCR1);
506 imx_uart_writel(sport, ucr4, UCR4);
507
508 ucr2 &= ~UCR2_RXEN;
509 imx_uart_writel(sport, ucr2, UCR2);
510 }
511
512 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)513 static void imx_uart_enable_ms(struct uart_port *port)
514 {
515 struct imx_port *sport = (struct imx_port *)port;
516
517 mod_timer(&sport->timer, jiffies);
518
519 mctrl_gpio_enable_ms(sport->gpios);
520 }
521
522 static void imx_uart_dma_tx(struct imx_port *sport);
523
524 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)525 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
526 {
527 struct circ_buf *xmit = &sport->port.state->xmit;
528
529 if (sport->port.x_char) {
530 /* Send next char */
531 imx_uart_writel(sport, sport->port.x_char, URTX0);
532 sport->port.icount.tx++;
533 sport->port.x_char = 0;
534 return;
535 }
536
537 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
538 imx_uart_stop_tx(&sport->port);
539 return;
540 }
541
542 if (sport->dma_is_enabled) {
543 u32 ucr1;
544 /*
545 * We've just sent a X-char Ensure the TX DMA is enabled
546 * and the TX IRQ is disabled.
547 **/
548 ucr1 = imx_uart_readl(sport, UCR1);
549 ucr1 &= ~UCR1_TRDYEN;
550 if (sport->dma_is_txing) {
551 ucr1 |= UCR1_TXDMAEN;
552 imx_uart_writel(sport, ucr1, UCR1);
553 } else {
554 imx_uart_writel(sport, ucr1, UCR1);
555 imx_uart_dma_tx(sport);
556 }
557
558 return;
559 }
560
561 while (!uart_circ_empty(xmit) &&
562 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
563 /* send xmit->buf[xmit->tail]
564 * out the port here */
565 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
566 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
567 sport->port.icount.tx++;
568 }
569
570 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
571 uart_write_wakeup(&sport->port);
572
573 if (uart_circ_empty(xmit))
574 imx_uart_stop_tx(&sport->port);
575 }
576
imx_uart_dma_tx_callback(void * data)577 static void imx_uart_dma_tx_callback(void *data)
578 {
579 struct imx_port *sport = data;
580 struct scatterlist *sgl = &sport->tx_sgl[0];
581 struct circ_buf *xmit = &sport->port.state->xmit;
582 unsigned long flags;
583 u32 ucr1;
584
585 spin_lock_irqsave(&sport->port.lock, flags);
586
587 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
588
589 ucr1 = imx_uart_readl(sport, UCR1);
590 ucr1 &= ~UCR1_TXDMAEN;
591 imx_uart_writel(sport, ucr1, UCR1);
592
593 /* update the stat */
594 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
595 sport->port.icount.tx += sport->tx_bytes;
596
597 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
598
599 sport->dma_is_txing = 0;
600
601 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
602 uart_write_wakeup(&sport->port);
603
604 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
605 imx_uart_dma_tx(sport);
606 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
607 u32 ucr4 = imx_uart_readl(sport, UCR4);
608 ucr4 |= UCR4_TCEN;
609 imx_uart_writel(sport, ucr4, UCR4);
610 }
611
612 spin_unlock_irqrestore(&sport->port.lock, flags);
613 }
614
615 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)616 static void imx_uart_dma_tx(struct imx_port *sport)
617 {
618 struct circ_buf *xmit = &sport->port.state->xmit;
619 struct scatterlist *sgl = sport->tx_sgl;
620 struct dma_async_tx_descriptor *desc;
621 struct dma_chan *chan = sport->dma_chan_tx;
622 struct device *dev = sport->port.dev;
623 u32 ucr1, ucr4;
624 int ret;
625
626 if (sport->dma_is_txing)
627 return;
628
629 ucr4 = imx_uart_readl(sport, UCR4);
630 ucr4 &= ~UCR4_TCEN;
631 imx_uart_writel(sport, ucr4, UCR4);
632
633 sport->tx_bytes = uart_circ_chars_pending(xmit);
634
635 if (xmit->tail < xmit->head || xmit->head == 0) {
636 sport->dma_tx_nents = 1;
637 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
638 } else {
639 sport->dma_tx_nents = 2;
640 sg_init_table(sgl, 2);
641 sg_set_buf(sgl, xmit->buf + xmit->tail,
642 UART_XMIT_SIZE - xmit->tail);
643 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
644 }
645
646 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
647 if (ret == 0) {
648 dev_err(dev, "DMA mapping error for TX.\n");
649 return;
650 }
651 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
652 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
653 if (!desc) {
654 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
655 DMA_TO_DEVICE);
656 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
657 return;
658 }
659 desc->callback = imx_uart_dma_tx_callback;
660 desc->callback_param = sport;
661
662 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
663 uart_circ_chars_pending(xmit));
664
665 ucr1 = imx_uart_readl(sport, UCR1);
666 ucr1 |= UCR1_TXDMAEN;
667 imx_uart_writel(sport, ucr1, UCR1);
668
669 /* fire it */
670 sport->dma_is_txing = 1;
671 dmaengine_submit(desc);
672 dma_async_issue_pending(chan);
673 return;
674 }
675
676 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)677 static void imx_uart_start_tx(struct uart_port *port)
678 {
679 struct imx_port *sport = (struct imx_port *)port;
680 u32 ucr1;
681
682 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
683 return;
684
685 /*
686 * We cannot simply do nothing here if sport->tx_state == SEND already
687 * because UCR1_TXMPTYEN might already have been cleared in
688 * imx_uart_stop_tx(), but tx_state is still SEND.
689 */
690
691 if (port->rs485.flags & SER_RS485_ENABLED) {
692 if (sport->tx_state == OFF) {
693 u32 ucr2 = imx_uart_readl(sport, UCR2);
694 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
695 imx_uart_rts_active(sport, &ucr2);
696 else
697 imx_uart_rts_inactive(sport, &ucr2);
698 imx_uart_writel(sport, ucr2, UCR2);
699
700 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
701 imx_uart_stop_rx(port);
702
703 sport->tx_state = WAIT_AFTER_RTS;
704
705 if (port->rs485.delay_rts_before_send > 0) {
706 start_hrtimer_ms(&sport->trigger_start_tx,
707 port->rs485.delay_rts_before_send);
708 return;
709 }
710
711 /* continue without any delay */
712 }
713
714 if (sport->tx_state == WAIT_AFTER_SEND
715 || sport->tx_state == WAIT_AFTER_RTS) {
716
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
718
719 /*
720 * Enable transmitter and shifter empty irq only if DMA
721 * is off. In the DMA case this is done in the
722 * tx-callback.
723 */
724 if (!sport->dma_is_enabled) {
725 u32 ucr4 = imx_uart_readl(sport, UCR4);
726 ucr4 |= UCR4_TCEN;
727 imx_uart_writel(sport, ucr4, UCR4);
728 }
729
730 sport->tx_state = SEND;
731 }
732 } else {
733 sport->tx_state = SEND;
734 }
735
736 if (!sport->dma_is_enabled) {
737 ucr1 = imx_uart_readl(sport, UCR1);
738 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
739 }
740
741 if (sport->dma_is_enabled) {
742 if (sport->port.x_char) {
743 /* We have X-char to send, so enable TX IRQ and
744 * disable TX DMA to let TX interrupt to send X-char */
745 ucr1 = imx_uart_readl(sport, UCR1);
746 ucr1 &= ~UCR1_TXDMAEN;
747 ucr1 |= UCR1_TRDYEN;
748 imx_uart_writel(sport, ucr1, UCR1);
749 return;
750 }
751
752 if (!uart_circ_empty(&port->state->xmit) &&
753 !uart_tx_stopped(port))
754 imx_uart_dma_tx(sport);
755 return;
756 }
757 }
758
__imx_uart_rtsint(int irq,void * dev_id)759 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
760 {
761 struct imx_port *sport = dev_id;
762 u32 usr1;
763
764 imx_uart_writel(sport, USR1_RTSD, USR1);
765 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
766 uart_handle_cts_change(&sport->port, !!usr1);
767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
768
769 return IRQ_HANDLED;
770 }
771
imx_uart_rtsint(int irq,void * dev_id)772 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
773 {
774 struct imx_port *sport = dev_id;
775 irqreturn_t ret;
776
777 spin_lock(&sport->port.lock);
778
779 ret = __imx_uart_rtsint(irq, dev_id);
780
781 spin_unlock(&sport->port.lock);
782
783 return ret;
784 }
785
imx_uart_txint(int irq,void * dev_id)786 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
787 {
788 struct imx_port *sport = dev_id;
789
790 spin_lock(&sport->port.lock);
791 imx_uart_transmit_buffer(sport);
792 spin_unlock(&sport->port.lock);
793 return IRQ_HANDLED;
794 }
795
__imx_uart_rxint(int irq,void * dev_id)796 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
797 {
798 struct imx_port *sport = dev_id;
799 unsigned int rx, flg, ignored = 0;
800 struct tty_port *port = &sport->port.state->port;
801
802 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
803 u32 usr2;
804
805 flg = TTY_NORMAL;
806 sport->port.icount.rx++;
807
808 rx = imx_uart_readl(sport, URXD0);
809
810 usr2 = imx_uart_readl(sport, USR2);
811 if (usr2 & USR2_BRCD) {
812 imx_uart_writel(sport, USR2_BRCD, USR2);
813 if (uart_handle_break(&sport->port))
814 continue;
815 }
816
817 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
818 continue;
819
820 if (unlikely(rx & URXD_ERR)) {
821 if (rx & URXD_BRK)
822 sport->port.icount.brk++;
823 else if (rx & URXD_PRERR)
824 sport->port.icount.parity++;
825 else if (rx & URXD_FRMERR)
826 sport->port.icount.frame++;
827 if (rx & URXD_OVRRUN)
828 sport->port.icount.overrun++;
829
830 if (rx & sport->port.ignore_status_mask) {
831 if (++ignored > 100)
832 goto out;
833 continue;
834 }
835
836 rx &= (sport->port.read_status_mask | 0xFF);
837
838 if (rx & URXD_BRK)
839 flg = TTY_BREAK;
840 else if (rx & URXD_PRERR)
841 flg = TTY_PARITY;
842 else if (rx & URXD_FRMERR)
843 flg = TTY_FRAME;
844 if (rx & URXD_OVRRUN)
845 flg = TTY_OVERRUN;
846
847 sport->port.sysrq = 0;
848 }
849
850 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
851 goto out;
852
853 if (tty_insert_flip_char(port, rx, flg) == 0)
854 sport->port.icount.buf_overrun++;
855 }
856
857 out:
858 tty_flip_buffer_push(port);
859
860 return IRQ_HANDLED;
861 }
862
imx_uart_rxint(int irq,void * dev_id)863 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
864 {
865 struct imx_port *sport = dev_id;
866 irqreturn_t ret;
867
868 spin_lock(&sport->port.lock);
869
870 ret = __imx_uart_rxint(irq, dev_id);
871
872 spin_unlock(&sport->port.lock);
873
874 return ret;
875 }
876
877 static void imx_uart_clear_rx_errors(struct imx_port *sport);
878
879 /*
880 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
881 */
imx_uart_get_hwmctrl(struct imx_port * sport)882 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
883 {
884 unsigned int tmp = TIOCM_DSR;
885 unsigned usr1 = imx_uart_readl(sport, USR1);
886 unsigned usr2 = imx_uart_readl(sport, USR2);
887
888 if (usr1 & USR1_RTSS)
889 tmp |= TIOCM_CTS;
890
891 /* in DCE mode DCDIN is always 0 */
892 if (!(usr2 & USR2_DCDIN))
893 tmp |= TIOCM_CAR;
894
895 if (sport->dte_mode)
896 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
897 tmp |= TIOCM_RI;
898
899 return tmp;
900 }
901
902 /*
903 * Handle any change of modem status signal since we were last called.
904 */
imx_uart_mctrl_check(struct imx_port * sport)905 static void imx_uart_mctrl_check(struct imx_port *sport)
906 {
907 unsigned int status, changed;
908
909 status = imx_uart_get_hwmctrl(sport);
910 changed = status ^ sport->old_status;
911
912 if (changed == 0)
913 return;
914
915 sport->old_status = status;
916
917 if (changed & TIOCM_RI && status & TIOCM_RI)
918 sport->port.icount.rng++;
919 if (changed & TIOCM_DSR)
920 sport->port.icount.dsr++;
921 if (changed & TIOCM_CAR)
922 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
923 if (changed & TIOCM_CTS)
924 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
925
926 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
927 }
928
imx_uart_int(int irq,void * dev_id)929 static irqreturn_t imx_uart_int(int irq, void *dev_id)
930 {
931 struct imx_port *sport = dev_id;
932 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
933 irqreturn_t ret = IRQ_NONE;
934
935 spin_lock(&sport->port.lock);
936
937 usr1 = imx_uart_readl(sport, USR1);
938 usr2 = imx_uart_readl(sport, USR2);
939 ucr1 = imx_uart_readl(sport, UCR1);
940 ucr2 = imx_uart_readl(sport, UCR2);
941 ucr3 = imx_uart_readl(sport, UCR3);
942 ucr4 = imx_uart_readl(sport, UCR4);
943
944 /*
945 * Even if a condition is true that can trigger an irq only handle it if
946 * the respective irq source is enabled. This prevents some undesired
947 * actions, for example if a character that sits in the RX FIFO and that
948 * should be fetched via DMA is tried to be fetched using PIO. Or the
949 * receiver is currently off and so reading from URXD0 results in an
950 * exception. So just mask the (raw) status bits for disabled irqs.
951 */
952 if ((ucr1 & UCR1_RRDYEN) == 0)
953 usr1 &= ~USR1_RRDY;
954 if ((ucr2 & UCR2_ATEN) == 0)
955 usr1 &= ~USR1_AGTIM;
956 if ((ucr1 & UCR1_TRDYEN) == 0)
957 usr1 &= ~USR1_TRDY;
958 if ((ucr4 & UCR4_TCEN) == 0)
959 usr2 &= ~USR2_TXDC;
960 if ((ucr3 & UCR3_DTRDEN) == 0)
961 usr1 &= ~USR1_DTRD;
962 if ((ucr1 & UCR1_RTSDEN) == 0)
963 usr1 &= ~USR1_RTSD;
964 if ((ucr3 & UCR3_AWAKEN) == 0)
965 usr1 &= ~USR1_AWAKE;
966 if ((ucr4 & UCR4_OREN) == 0)
967 usr2 &= ~USR2_ORE;
968
969 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
970 imx_uart_writel(sport, USR1_AGTIM, USR1);
971
972 __imx_uart_rxint(irq, dev_id);
973 ret = IRQ_HANDLED;
974 }
975
976 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
977 imx_uart_transmit_buffer(sport);
978 ret = IRQ_HANDLED;
979 }
980
981 if (usr1 & USR1_DTRD) {
982 imx_uart_writel(sport, USR1_DTRD, USR1);
983
984 imx_uart_mctrl_check(sport);
985
986 ret = IRQ_HANDLED;
987 }
988
989 if (usr1 & USR1_RTSD) {
990 __imx_uart_rtsint(irq, dev_id);
991 ret = IRQ_HANDLED;
992 }
993
994 if (usr1 & USR1_AWAKE) {
995 imx_uart_writel(sport, USR1_AWAKE, USR1);
996 ret = IRQ_HANDLED;
997 }
998
999 if (usr2 & USR2_ORE) {
1000 sport->port.icount.overrun++;
1001 imx_uart_writel(sport, USR2_ORE, USR2);
1002 ret = IRQ_HANDLED;
1003 }
1004
1005 spin_unlock(&sport->port.lock);
1006
1007 return ret;
1008 }
1009
1010 /*
1011 * Return TIOCSER_TEMT when transmitter is not busy.
1012 */
imx_uart_tx_empty(struct uart_port * port)1013 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1014 {
1015 struct imx_port *sport = (struct imx_port *)port;
1016 unsigned int ret;
1017
1018 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1019
1020 /* If the TX DMA is working, return 0. */
1021 if (sport->dma_is_txing)
1022 ret = 0;
1023
1024 return ret;
1025 }
1026
1027 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1028 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1029 {
1030 struct imx_port *sport = (struct imx_port *)port;
1031 unsigned int ret = imx_uart_get_hwmctrl(sport);
1032
1033 mctrl_gpio_get(sport->gpios, &ret);
1034
1035 return ret;
1036 }
1037
1038 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1039 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1040 {
1041 struct imx_port *sport = (struct imx_port *)port;
1042 u32 ucr3, uts;
1043
1044 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1045 u32 ucr2;
1046
1047 /*
1048 * Turn off autoRTS if RTS is lowered and restore autoRTS
1049 * setting if RTS is raised.
1050 */
1051 ucr2 = imx_uart_readl(sport, UCR2);
1052 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1053 if (mctrl & TIOCM_RTS) {
1054 ucr2 |= UCR2_CTS;
1055 /*
1056 * UCR2_IRTS is unset if and only if the port is
1057 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1058 * to get the state to restore to.
1059 */
1060 if (!(ucr2 & UCR2_IRTS))
1061 ucr2 |= UCR2_CTSC;
1062 }
1063 imx_uart_writel(sport, ucr2, UCR2);
1064 }
1065
1066 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1067 if (!(mctrl & TIOCM_DTR))
1068 ucr3 |= UCR3_DSR;
1069 imx_uart_writel(sport, ucr3, UCR3);
1070
1071 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1072 if (mctrl & TIOCM_LOOP)
1073 uts |= UTS_LOOP;
1074 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1075
1076 mctrl_gpio_set(sport->gpios, mctrl);
1077 }
1078
1079 /*
1080 * Interrupts always disabled.
1081 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1082 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1083 {
1084 struct imx_port *sport = (struct imx_port *)port;
1085 unsigned long flags;
1086 u32 ucr1;
1087
1088 spin_lock_irqsave(&sport->port.lock, flags);
1089
1090 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1091
1092 if (break_state != 0)
1093 ucr1 |= UCR1_SNDBRK;
1094
1095 imx_uart_writel(sport, ucr1, UCR1);
1096
1097 spin_unlock_irqrestore(&sport->port.lock, flags);
1098 }
1099
1100 /*
1101 * This is our per-port timeout handler, for checking the
1102 * modem status signals.
1103 */
imx_uart_timeout(struct timer_list * t)1104 static void imx_uart_timeout(struct timer_list *t)
1105 {
1106 struct imx_port *sport = from_timer(sport, t, timer);
1107 unsigned long flags;
1108
1109 if (sport->port.state) {
1110 spin_lock_irqsave(&sport->port.lock, flags);
1111 imx_uart_mctrl_check(sport);
1112 spin_unlock_irqrestore(&sport->port.lock, flags);
1113
1114 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1115 }
1116 }
1117
1118 /*
1119 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1120 * [1] the RX DMA buffer is full.
1121 * [2] the aging timer expires
1122 *
1123 * Condition [2] is triggered when a character has been sitting in the FIFO
1124 * for at least 8 byte durations.
1125 */
imx_uart_dma_rx_callback(void * data)1126 static void imx_uart_dma_rx_callback(void *data)
1127 {
1128 struct imx_port *sport = data;
1129 struct dma_chan *chan = sport->dma_chan_rx;
1130 struct scatterlist *sgl = &sport->rx_sgl;
1131 struct tty_port *port = &sport->port.state->port;
1132 struct dma_tx_state state;
1133 struct circ_buf *rx_ring = &sport->rx_ring;
1134 enum dma_status status;
1135 unsigned int w_bytes = 0;
1136 unsigned int r_bytes;
1137 unsigned int bd_size;
1138
1139 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1140
1141 if (status == DMA_ERROR) {
1142 imx_uart_clear_rx_errors(sport);
1143 return;
1144 }
1145
1146 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1147
1148 /*
1149 * The state-residue variable represents the empty space
1150 * relative to the entire buffer. Taking this in consideration
1151 * the head is always calculated base on the buffer total
1152 * length - DMA transaction residue. The UART script from the
1153 * SDMA firmware will jump to the next buffer descriptor,
1154 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1155 * Taking this in consideration the tail is always at the
1156 * beginning of the buffer descriptor that contains the head.
1157 */
1158
1159 /* Calculate the head */
1160 rx_ring->head = sg_dma_len(sgl) - state.residue;
1161
1162 /* Calculate the tail. */
1163 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1164 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1165
1166 if (rx_ring->head <= sg_dma_len(sgl) &&
1167 rx_ring->head > rx_ring->tail) {
1168
1169 /* Move data from tail to head */
1170 r_bytes = rx_ring->head - rx_ring->tail;
1171
1172 /* CPU claims ownership of RX DMA buffer */
1173 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1174 DMA_FROM_DEVICE);
1175
1176 w_bytes = tty_insert_flip_string(port,
1177 sport->rx_buf + rx_ring->tail, r_bytes);
1178
1179 /* UART retrieves ownership of RX DMA buffer */
1180 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1181 DMA_FROM_DEVICE);
1182
1183 if (w_bytes != r_bytes)
1184 sport->port.icount.buf_overrun++;
1185
1186 sport->port.icount.rx += w_bytes;
1187 } else {
1188 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1189 WARN_ON(rx_ring->head <= rx_ring->tail);
1190 }
1191 }
1192
1193 if (w_bytes) {
1194 tty_flip_buffer_push(port);
1195 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1196 }
1197 }
1198
imx_uart_start_rx_dma(struct imx_port * sport)1199 static int imx_uart_start_rx_dma(struct imx_port *sport)
1200 {
1201 struct scatterlist *sgl = &sport->rx_sgl;
1202 struct dma_chan *chan = sport->dma_chan_rx;
1203 struct device *dev = sport->port.dev;
1204 struct dma_async_tx_descriptor *desc;
1205 int ret;
1206
1207 sport->rx_ring.head = 0;
1208 sport->rx_ring.tail = 0;
1209
1210 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1211 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1212 if (ret == 0) {
1213 dev_err(dev, "DMA mapping error for RX.\n");
1214 return -EINVAL;
1215 }
1216
1217 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1218 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1219 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1220
1221 if (!desc) {
1222 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1223 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1224 return -EINVAL;
1225 }
1226 desc->callback = imx_uart_dma_rx_callback;
1227 desc->callback_param = sport;
1228
1229 dev_dbg(dev, "RX: prepare for the DMA.\n");
1230 sport->dma_is_rxing = 1;
1231 sport->rx_cookie = dmaengine_submit(desc);
1232 dma_async_issue_pending(chan);
1233 return 0;
1234 }
1235
imx_uart_clear_rx_errors(struct imx_port * sport)1236 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1237 {
1238 struct tty_port *port = &sport->port.state->port;
1239 u32 usr1, usr2;
1240
1241 usr1 = imx_uart_readl(sport, USR1);
1242 usr2 = imx_uart_readl(sport, USR2);
1243
1244 if (usr2 & USR2_BRCD) {
1245 sport->port.icount.brk++;
1246 imx_uart_writel(sport, USR2_BRCD, USR2);
1247 uart_handle_break(&sport->port);
1248 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1249 sport->port.icount.buf_overrun++;
1250 tty_flip_buffer_push(port);
1251 } else {
1252 if (usr1 & USR1_FRAMERR) {
1253 sport->port.icount.frame++;
1254 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1255 } else if (usr1 & USR1_PARITYERR) {
1256 sport->port.icount.parity++;
1257 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1258 }
1259 }
1260
1261 if (usr2 & USR2_ORE) {
1262 sport->port.icount.overrun++;
1263 imx_uart_writel(sport, USR2_ORE, USR2);
1264 }
1265
1266 }
1267
1268 #define TXTL_DEFAULT 2 /* reset default */
1269 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1270 #define TXTL_DMA 8 /* DMA burst setting */
1271 #define RXTL_DMA 9 /* DMA burst setting */
1272
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1273 static void imx_uart_setup_ufcr(struct imx_port *sport,
1274 unsigned char txwl, unsigned char rxwl)
1275 {
1276 unsigned int val;
1277
1278 /* set receiver / transmitter trigger level */
1279 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1280 val |= txwl << UFCR_TXTL_SHF | rxwl;
1281 imx_uart_writel(sport, val, UFCR);
1282 }
1283
imx_uart_dma_exit(struct imx_port * sport)1284 static void imx_uart_dma_exit(struct imx_port *sport)
1285 {
1286 if (sport->dma_chan_rx) {
1287 dmaengine_terminate_sync(sport->dma_chan_rx);
1288 dma_release_channel(sport->dma_chan_rx);
1289 sport->dma_chan_rx = NULL;
1290 sport->rx_cookie = -EINVAL;
1291 kfree(sport->rx_buf);
1292 sport->rx_buf = NULL;
1293 }
1294
1295 if (sport->dma_chan_tx) {
1296 dmaengine_terminate_sync(sport->dma_chan_tx);
1297 dma_release_channel(sport->dma_chan_tx);
1298 sport->dma_chan_tx = NULL;
1299 }
1300 }
1301
imx_uart_dma_init(struct imx_port * sport)1302 static int imx_uart_dma_init(struct imx_port *sport)
1303 {
1304 struct dma_slave_config slave_config = {};
1305 struct device *dev = sport->port.dev;
1306 int ret;
1307
1308 /* Prepare for RX : */
1309 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1310 if (!sport->dma_chan_rx) {
1311 dev_dbg(dev, "cannot get the DMA channel.\n");
1312 ret = -EINVAL;
1313 goto err;
1314 }
1315
1316 slave_config.direction = DMA_DEV_TO_MEM;
1317 slave_config.src_addr = sport->port.mapbase + URXD0;
1318 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1319 /* one byte less than the watermark level to enable the aging timer */
1320 slave_config.src_maxburst = RXTL_DMA - 1;
1321 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1322 if (ret) {
1323 dev_err(dev, "error in RX dma configuration.\n");
1324 goto err;
1325 }
1326
1327 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1328 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1329 if (!sport->rx_buf) {
1330 ret = -ENOMEM;
1331 goto err;
1332 }
1333 sport->rx_ring.buf = sport->rx_buf;
1334
1335 /* Prepare for TX : */
1336 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1337 if (!sport->dma_chan_tx) {
1338 dev_err(dev, "cannot get the TX DMA channel!\n");
1339 ret = -EINVAL;
1340 goto err;
1341 }
1342
1343 slave_config.direction = DMA_MEM_TO_DEV;
1344 slave_config.dst_addr = sport->port.mapbase + URTX0;
1345 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1346 slave_config.dst_maxburst = TXTL_DMA;
1347 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1348 if (ret) {
1349 dev_err(dev, "error in TX dma configuration.");
1350 goto err;
1351 }
1352
1353 return 0;
1354 err:
1355 imx_uart_dma_exit(sport);
1356 return ret;
1357 }
1358
imx_uart_enable_dma(struct imx_port * sport)1359 static void imx_uart_enable_dma(struct imx_port *sport)
1360 {
1361 u32 ucr1;
1362
1363 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1364
1365 /* set UCR1 */
1366 ucr1 = imx_uart_readl(sport, UCR1);
1367 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1368 imx_uart_writel(sport, ucr1, UCR1);
1369
1370 sport->dma_is_enabled = 1;
1371 }
1372
imx_uart_disable_dma(struct imx_port * sport)1373 static void imx_uart_disable_dma(struct imx_port *sport)
1374 {
1375 u32 ucr1;
1376
1377 /* clear UCR1 */
1378 ucr1 = imx_uart_readl(sport, UCR1);
1379 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1380 imx_uart_writel(sport, ucr1, UCR1);
1381
1382 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1383
1384 sport->dma_is_enabled = 0;
1385 }
1386
1387 /* half the RX buffer size */
1388 #define CTSTL 16
1389
imx_uart_startup(struct uart_port * port)1390 static int imx_uart_startup(struct uart_port *port)
1391 {
1392 struct imx_port *sport = (struct imx_port *)port;
1393 int retval, i;
1394 unsigned long flags;
1395 int dma_is_inited = 0;
1396 u32 ucr1, ucr2, ucr3, ucr4;
1397
1398 retval = clk_prepare_enable(sport->clk_per);
1399 if (retval)
1400 return retval;
1401 retval = clk_prepare_enable(sport->clk_ipg);
1402 if (retval) {
1403 clk_disable_unprepare(sport->clk_per);
1404 return retval;
1405 }
1406
1407 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1408
1409 /* disable the DREN bit (Data Ready interrupt enable) before
1410 * requesting IRQs
1411 */
1412 ucr4 = imx_uart_readl(sport, UCR4);
1413
1414 /* set the trigger level for CTS */
1415 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1416 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1417
1418 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1419
1420 /* Can we enable the DMA support? */
1421 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1422 dma_is_inited = 1;
1423
1424 spin_lock_irqsave(&sport->port.lock, flags);
1425 /* Reset fifo's and state machines */
1426 i = 100;
1427
1428 ucr2 = imx_uart_readl(sport, UCR2);
1429 ucr2 &= ~UCR2_SRST;
1430 imx_uart_writel(sport, ucr2, UCR2);
1431
1432 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1433 udelay(1);
1434
1435 /*
1436 * Finally, clear and enable interrupts
1437 */
1438 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1439 imx_uart_writel(sport, USR2_ORE, USR2);
1440
1441 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1442 ucr1 |= UCR1_UARTEN;
1443 if (sport->have_rtscts)
1444 ucr1 |= UCR1_RTSDEN;
1445
1446 imx_uart_writel(sport, ucr1, UCR1);
1447
1448 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1449 if (!dma_is_inited)
1450 ucr4 |= UCR4_OREN;
1451 if (sport->inverted_rx)
1452 ucr4 |= UCR4_INVR;
1453 imx_uart_writel(sport, ucr4, UCR4);
1454
1455 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1456 /*
1457 * configure tx polarity before enabling tx
1458 */
1459 if (sport->inverted_tx)
1460 ucr3 |= UCR3_INVT;
1461
1462 if (!imx_uart_is_imx1(sport)) {
1463 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1464
1465 if (sport->dte_mode)
1466 /* disable broken interrupts */
1467 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1468 }
1469 imx_uart_writel(sport, ucr3, UCR3);
1470
1471 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1472 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1473 if (!sport->have_rtscts)
1474 ucr2 |= UCR2_IRTS;
1475 /*
1476 * make sure the edge sensitive RTS-irq is disabled,
1477 * we're using RTSD instead.
1478 */
1479 if (!imx_uart_is_imx1(sport))
1480 ucr2 &= ~UCR2_RTSEN;
1481 imx_uart_writel(sport, ucr2, UCR2);
1482
1483 /*
1484 * Enable modem status interrupts
1485 */
1486 imx_uart_enable_ms(&sport->port);
1487
1488 if (dma_is_inited) {
1489 imx_uart_enable_dma(sport);
1490 imx_uart_start_rx_dma(sport);
1491 } else {
1492 ucr1 = imx_uart_readl(sport, UCR1);
1493 ucr1 |= UCR1_RRDYEN;
1494 imx_uart_writel(sport, ucr1, UCR1);
1495
1496 ucr2 = imx_uart_readl(sport, UCR2);
1497 ucr2 |= UCR2_ATEN;
1498 imx_uart_writel(sport, ucr2, UCR2);
1499 }
1500
1501 spin_unlock_irqrestore(&sport->port.lock, flags);
1502
1503 return 0;
1504 }
1505
imx_uart_shutdown(struct uart_port * port)1506 static void imx_uart_shutdown(struct uart_port *port)
1507 {
1508 struct imx_port *sport = (struct imx_port *)port;
1509 unsigned long flags;
1510 u32 ucr1, ucr2, ucr4;
1511
1512 if (sport->dma_is_enabled) {
1513 dmaengine_terminate_sync(sport->dma_chan_tx);
1514 if (sport->dma_is_txing) {
1515 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1516 sport->dma_tx_nents, DMA_TO_DEVICE);
1517 sport->dma_is_txing = 0;
1518 }
1519 dmaengine_terminate_sync(sport->dma_chan_rx);
1520 if (sport->dma_is_rxing) {
1521 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1522 1, DMA_FROM_DEVICE);
1523 sport->dma_is_rxing = 0;
1524 }
1525
1526 spin_lock_irqsave(&sport->port.lock, flags);
1527 imx_uart_stop_tx(port);
1528 imx_uart_stop_rx(port);
1529 imx_uart_disable_dma(sport);
1530 spin_unlock_irqrestore(&sport->port.lock, flags);
1531 imx_uart_dma_exit(sport);
1532 }
1533
1534 mctrl_gpio_disable_ms(sport->gpios);
1535
1536 spin_lock_irqsave(&sport->port.lock, flags);
1537 ucr2 = imx_uart_readl(sport, UCR2);
1538 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1539 imx_uart_writel(sport, ucr2, UCR2);
1540 spin_unlock_irqrestore(&sport->port.lock, flags);
1541
1542 /*
1543 * Stop our timer.
1544 */
1545 del_timer_sync(&sport->timer);
1546
1547 /*
1548 * Disable all interrupts, port and break condition.
1549 */
1550
1551 spin_lock_irqsave(&sport->port.lock, flags);
1552
1553 ucr1 = imx_uart_readl(sport, UCR1);
1554 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1555 imx_uart_writel(sport, ucr1, UCR1);
1556
1557 ucr4 = imx_uart_readl(sport, UCR4);
1558 ucr4 &= ~UCR4_TCEN;
1559 imx_uart_writel(sport, ucr4, UCR4);
1560
1561 spin_unlock_irqrestore(&sport->port.lock, flags);
1562
1563 clk_disable_unprepare(sport->clk_per);
1564 clk_disable_unprepare(sport->clk_ipg);
1565 }
1566
1567 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1568 static void imx_uart_flush_buffer(struct uart_port *port)
1569 {
1570 struct imx_port *sport = (struct imx_port *)port;
1571 struct scatterlist *sgl = &sport->tx_sgl[0];
1572 u32 ucr2;
1573 int i = 100, ubir, ubmr, uts;
1574
1575 if (!sport->dma_chan_tx)
1576 return;
1577
1578 sport->tx_bytes = 0;
1579 dmaengine_terminate_all(sport->dma_chan_tx);
1580 if (sport->dma_is_txing) {
1581 u32 ucr1;
1582
1583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1584 DMA_TO_DEVICE);
1585 ucr1 = imx_uart_readl(sport, UCR1);
1586 ucr1 &= ~UCR1_TXDMAEN;
1587 imx_uart_writel(sport, ucr1, UCR1);
1588 sport->dma_is_txing = 0;
1589 }
1590
1591 /*
1592 * According to the Reference Manual description of the UART SRST bit:
1593 *
1594 * "Reset the transmit and receive state machines,
1595 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1596 * and UTS[6-3]".
1597 *
1598 * We don't need to restore the old values from USR1, USR2, URXD and
1599 * UTXD. UBRC is read only, so only save/restore the other three
1600 * registers.
1601 */
1602 ubir = imx_uart_readl(sport, UBIR);
1603 ubmr = imx_uart_readl(sport, UBMR);
1604 uts = imx_uart_readl(sport, IMX21_UTS);
1605
1606 ucr2 = imx_uart_readl(sport, UCR2);
1607 ucr2 &= ~UCR2_SRST;
1608 imx_uart_writel(sport, ucr2, UCR2);
1609
1610 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1611 udelay(1);
1612
1613 /* Restore the registers */
1614 imx_uart_writel(sport, ubir, UBIR);
1615 imx_uart_writel(sport, ubmr, UBMR);
1616 imx_uart_writel(sport, uts, IMX21_UTS);
1617 }
1618
1619 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1620 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1621 const struct ktermios *old)
1622 {
1623 struct imx_port *sport = (struct imx_port *)port;
1624 unsigned long flags;
1625 u32 ucr2, old_ucr2, ufcr;
1626 unsigned int baud, quot;
1627 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1628 unsigned long div;
1629 unsigned long num, denom, old_ubir, old_ubmr;
1630 uint64_t tdiv64;
1631
1632 /*
1633 * We only support CS7 and CS8.
1634 */
1635 while ((termios->c_cflag & CSIZE) != CS7 &&
1636 (termios->c_cflag & CSIZE) != CS8) {
1637 termios->c_cflag &= ~CSIZE;
1638 termios->c_cflag |= old_csize;
1639 old_csize = CS8;
1640 }
1641
1642 del_timer_sync(&sport->timer);
1643
1644 /*
1645 * Ask the core to calculate the divisor for us.
1646 */
1647 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1648 quot = uart_get_divisor(port, baud);
1649
1650 spin_lock_irqsave(&sport->port.lock, flags);
1651
1652 /*
1653 * Read current UCR2 and save it for future use, then clear all the bits
1654 * except those we will or may need to preserve.
1655 */
1656 old_ucr2 = imx_uart_readl(sport, UCR2);
1657 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1658
1659 ucr2 |= UCR2_SRST | UCR2_IRTS;
1660 if ((termios->c_cflag & CSIZE) == CS8)
1661 ucr2 |= UCR2_WS;
1662
1663 if (!sport->have_rtscts)
1664 termios->c_cflag &= ~CRTSCTS;
1665
1666 if (port->rs485.flags & SER_RS485_ENABLED) {
1667 /*
1668 * RTS is mandatory for rs485 operation, so keep
1669 * it under manual control and keep transmitter
1670 * disabled.
1671 */
1672 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1673 imx_uart_rts_active(sport, &ucr2);
1674 else
1675 imx_uart_rts_inactive(sport, &ucr2);
1676
1677 } else if (termios->c_cflag & CRTSCTS) {
1678 /*
1679 * Only let receiver control RTS output if we were not requested
1680 * to have RTS inactive (which then should take precedence).
1681 */
1682 if (ucr2 & UCR2_CTS)
1683 ucr2 |= UCR2_CTSC;
1684 }
1685
1686 if (termios->c_cflag & CRTSCTS)
1687 ucr2 &= ~UCR2_IRTS;
1688 if (termios->c_cflag & CSTOPB)
1689 ucr2 |= UCR2_STPB;
1690 if (termios->c_cflag & PARENB) {
1691 ucr2 |= UCR2_PREN;
1692 if (termios->c_cflag & PARODD)
1693 ucr2 |= UCR2_PROE;
1694 }
1695
1696 sport->port.read_status_mask = 0;
1697 if (termios->c_iflag & INPCK)
1698 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1699 if (termios->c_iflag & (BRKINT | PARMRK))
1700 sport->port.read_status_mask |= URXD_BRK;
1701
1702 /*
1703 * Characters to ignore
1704 */
1705 sport->port.ignore_status_mask = 0;
1706 if (termios->c_iflag & IGNPAR)
1707 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1708 if (termios->c_iflag & IGNBRK) {
1709 sport->port.ignore_status_mask |= URXD_BRK;
1710 /*
1711 * If we're ignoring parity and break indicators,
1712 * ignore overruns too (for real raw support).
1713 */
1714 if (termios->c_iflag & IGNPAR)
1715 sport->port.ignore_status_mask |= URXD_OVRRUN;
1716 }
1717
1718 if ((termios->c_cflag & CREAD) == 0)
1719 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1720
1721 /*
1722 * Update the per-port timeout.
1723 */
1724 uart_update_timeout(port, termios->c_cflag, baud);
1725
1726 /* custom-baudrate handling */
1727 div = sport->port.uartclk / (baud * 16);
1728 if (baud == 38400 && quot != div)
1729 baud = sport->port.uartclk / (quot * 16);
1730
1731 div = sport->port.uartclk / (baud * 16);
1732 if (div > 7)
1733 div = 7;
1734 if (!div)
1735 div = 1;
1736
1737 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1738 1 << 16, 1 << 16, &num, &denom);
1739
1740 tdiv64 = sport->port.uartclk;
1741 tdiv64 *= num;
1742 do_div(tdiv64, denom * 16 * div);
1743 tty_termios_encode_baud_rate(termios,
1744 (speed_t)tdiv64, (speed_t)tdiv64);
1745
1746 num -= 1;
1747 denom -= 1;
1748
1749 ufcr = imx_uart_readl(sport, UFCR);
1750 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1751 imx_uart_writel(sport, ufcr, UFCR);
1752
1753 /*
1754 * Two registers below should always be written both and in this
1755 * particular order. One consequence is that we need to check if any of
1756 * them changes and then update both. We do need the check for change
1757 * as even writing the same values seem to "restart"
1758 * transmission/receiving logic in the hardware, that leads to data
1759 * breakage even when rate doesn't in fact change. E.g., user switches
1760 * RTS/CTS handshake and suddenly gets broken bytes.
1761 */
1762 old_ubir = imx_uart_readl(sport, UBIR);
1763 old_ubmr = imx_uart_readl(sport, UBMR);
1764 if (old_ubir != num || old_ubmr != denom) {
1765 imx_uart_writel(sport, num, UBIR);
1766 imx_uart_writel(sport, denom, UBMR);
1767 }
1768
1769 if (!imx_uart_is_imx1(sport))
1770 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1771 IMX21_ONEMS);
1772
1773 imx_uart_writel(sport, ucr2, UCR2);
1774
1775 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1776 imx_uart_enable_ms(&sport->port);
1777
1778 spin_unlock_irqrestore(&sport->port.lock, flags);
1779 }
1780
imx_uart_type(struct uart_port * port)1781 static const char *imx_uart_type(struct uart_port *port)
1782 {
1783 struct imx_port *sport = (struct imx_port *)port;
1784
1785 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1786 }
1787
1788 /*
1789 * Configure/autoconfigure the port.
1790 */
imx_uart_config_port(struct uart_port * port,int flags)1791 static void imx_uart_config_port(struct uart_port *port, int flags)
1792 {
1793 struct imx_port *sport = (struct imx_port *)port;
1794
1795 if (flags & UART_CONFIG_TYPE)
1796 sport->port.type = PORT_IMX;
1797 }
1798
1799 /*
1800 * Verify the new serial_struct (for TIOCSSERIAL).
1801 * The only change we allow are to the flags and type, and
1802 * even then only between PORT_IMX and PORT_UNKNOWN
1803 */
1804 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1805 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1806 {
1807 struct imx_port *sport = (struct imx_port *)port;
1808 int ret = 0;
1809
1810 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1811 ret = -EINVAL;
1812 if (sport->port.irq != ser->irq)
1813 ret = -EINVAL;
1814 if (ser->io_type != UPIO_MEM)
1815 ret = -EINVAL;
1816 if (sport->port.uartclk / 16 != ser->baud_base)
1817 ret = -EINVAL;
1818 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1819 ret = -EINVAL;
1820 if (sport->port.iobase != ser->port)
1821 ret = -EINVAL;
1822 if (ser->hub6 != 0)
1823 ret = -EINVAL;
1824 return ret;
1825 }
1826
1827 #if defined(CONFIG_CONSOLE_POLL)
1828
imx_uart_poll_init(struct uart_port * port)1829 static int imx_uart_poll_init(struct uart_port *port)
1830 {
1831 struct imx_port *sport = (struct imx_port *)port;
1832 unsigned long flags;
1833 u32 ucr1, ucr2;
1834 int retval;
1835
1836 retval = clk_prepare_enable(sport->clk_ipg);
1837 if (retval)
1838 return retval;
1839 retval = clk_prepare_enable(sport->clk_per);
1840 if (retval)
1841 clk_disable_unprepare(sport->clk_ipg);
1842
1843 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1844
1845 spin_lock_irqsave(&sport->port.lock, flags);
1846
1847 /*
1848 * Be careful about the order of enabling bits here. First enable the
1849 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1850 * This prevents that a character that already sits in the RX fifo is
1851 * triggering an irq but the try to fetch it from there results in an
1852 * exception because UARTEN or RXEN is still off.
1853 */
1854 ucr1 = imx_uart_readl(sport, UCR1);
1855 ucr2 = imx_uart_readl(sport, UCR2);
1856
1857 if (imx_uart_is_imx1(sport))
1858 ucr1 |= IMX1_UCR1_UARTCLKEN;
1859
1860 ucr1 |= UCR1_UARTEN;
1861 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1862
1863 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1864 ucr2 &= ~UCR2_ATEN;
1865
1866 imx_uart_writel(sport, ucr1, UCR1);
1867 imx_uart_writel(sport, ucr2, UCR2);
1868
1869 /* now enable irqs */
1870 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1871 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1872
1873 spin_unlock_irqrestore(&sport->port.lock, flags);
1874
1875 return 0;
1876 }
1877
imx_uart_poll_get_char(struct uart_port * port)1878 static int imx_uart_poll_get_char(struct uart_port *port)
1879 {
1880 struct imx_port *sport = (struct imx_port *)port;
1881 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1882 return NO_POLL_CHAR;
1883
1884 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1885 }
1886
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1887 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1888 {
1889 struct imx_port *sport = (struct imx_port *)port;
1890 unsigned int status;
1891
1892 /* drain */
1893 do {
1894 status = imx_uart_readl(sport, USR1);
1895 } while (~status & USR1_TRDY);
1896
1897 /* write */
1898 imx_uart_writel(sport, c, URTX0);
1899
1900 /* flush */
1901 do {
1902 status = imx_uart_readl(sport, USR2);
1903 } while (~status & USR2_TXDC);
1904 }
1905 #endif
1906
1907 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1908 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1909 struct serial_rs485 *rs485conf)
1910 {
1911 struct imx_port *sport = (struct imx_port *)port;
1912 u32 ucr2;
1913
1914 if (rs485conf->flags & SER_RS485_ENABLED) {
1915 /* Enable receiver if low-active RTS signal is requested */
1916 if (sport->have_rtscts && !sport->have_rtsgpio &&
1917 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1918 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1919
1920 /* disable transmitter */
1921 ucr2 = imx_uart_readl(sport, UCR2);
1922 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1923 imx_uart_rts_active(sport, &ucr2);
1924 else
1925 imx_uart_rts_inactive(sport, &ucr2);
1926 imx_uart_writel(sport, ucr2, UCR2);
1927 }
1928
1929 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1930 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1931 rs485conf->flags & SER_RS485_RX_DURING_TX)
1932 imx_uart_start_rx(port);
1933
1934 return 0;
1935 }
1936
1937 static const struct uart_ops imx_uart_pops = {
1938 .tx_empty = imx_uart_tx_empty,
1939 .set_mctrl = imx_uart_set_mctrl,
1940 .get_mctrl = imx_uart_get_mctrl,
1941 .stop_tx = imx_uart_stop_tx,
1942 .start_tx = imx_uart_start_tx,
1943 .stop_rx = imx_uart_stop_rx,
1944 .enable_ms = imx_uart_enable_ms,
1945 .break_ctl = imx_uart_break_ctl,
1946 .startup = imx_uart_startup,
1947 .shutdown = imx_uart_shutdown,
1948 .flush_buffer = imx_uart_flush_buffer,
1949 .set_termios = imx_uart_set_termios,
1950 .type = imx_uart_type,
1951 .config_port = imx_uart_config_port,
1952 .verify_port = imx_uart_verify_port,
1953 #if defined(CONFIG_CONSOLE_POLL)
1954 .poll_init = imx_uart_poll_init,
1955 .poll_get_char = imx_uart_poll_get_char,
1956 .poll_put_char = imx_uart_poll_put_char,
1957 #endif
1958 };
1959
1960 static struct imx_port *imx_uart_ports[UART_NR];
1961
1962 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)1963 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1964 {
1965 struct imx_port *sport = (struct imx_port *)port;
1966
1967 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1968 barrier();
1969
1970 imx_uart_writel(sport, ch, URTX0);
1971 }
1972
1973 /*
1974 * Interrupts are disabled on entering
1975 */
1976 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)1977 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1978 {
1979 struct imx_port *sport = imx_uart_ports[co->index];
1980 struct imx_port_ucrs old_ucr;
1981 unsigned long flags;
1982 unsigned int ucr1;
1983 int locked = 1;
1984
1985 if (sport->port.sysrq)
1986 locked = 0;
1987 else if (oops_in_progress)
1988 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1989 else
1990 spin_lock_irqsave(&sport->port.lock, flags);
1991
1992 /*
1993 * First, save UCR1/2/3 and then disable interrupts
1994 */
1995 imx_uart_ucrs_save(sport, &old_ucr);
1996 ucr1 = old_ucr.ucr1;
1997
1998 if (imx_uart_is_imx1(sport))
1999 ucr1 |= IMX1_UCR1_UARTCLKEN;
2000 ucr1 |= UCR1_UARTEN;
2001 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2002
2003 imx_uart_writel(sport, ucr1, UCR1);
2004
2005 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2006
2007 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2008
2009 /*
2010 * Finally, wait for transmitter to become empty
2011 * and restore UCR1/2/3
2012 */
2013 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2014
2015 imx_uart_ucrs_restore(sport, &old_ucr);
2016
2017 if (locked)
2018 spin_unlock_irqrestore(&sport->port.lock, flags);
2019 }
2020
2021 /*
2022 * If the port was already initialised (eg, by a boot loader),
2023 * try to determine the current setup.
2024 */
2025 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2026 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2027 int *parity, int *bits)
2028 {
2029
2030 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2031 /* ok, the port was enabled */
2032 unsigned int ucr2, ubir, ubmr, uartclk;
2033 unsigned int baud_raw;
2034 unsigned int ucfr_rfdiv;
2035
2036 ucr2 = imx_uart_readl(sport, UCR2);
2037
2038 *parity = 'n';
2039 if (ucr2 & UCR2_PREN) {
2040 if (ucr2 & UCR2_PROE)
2041 *parity = 'o';
2042 else
2043 *parity = 'e';
2044 }
2045
2046 if (ucr2 & UCR2_WS)
2047 *bits = 8;
2048 else
2049 *bits = 7;
2050
2051 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2052 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2053
2054 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2055 if (ucfr_rfdiv == 6)
2056 ucfr_rfdiv = 7;
2057 else
2058 ucfr_rfdiv = 6 - ucfr_rfdiv;
2059
2060 uartclk = clk_get_rate(sport->clk_per);
2061 uartclk /= ucfr_rfdiv;
2062
2063 { /*
2064 * The next code provides exact computation of
2065 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2066 * without need of float support or long long division,
2067 * which would be required to prevent 32bit arithmetic overflow
2068 */
2069 unsigned int mul = ubir + 1;
2070 unsigned int div = 16 * (ubmr + 1);
2071 unsigned int rem = uartclk % div;
2072
2073 baud_raw = (uartclk / div) * mul;
2074 baud_raw += (rem * mul + div / 2) / div;
2075 *baud = (baud_raw + 50) / 100 * 100;
2076 }
2077
2078 if (*baud != baud_raw)
2079 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2080 baud_raw, *baud);
2081 }
2082 }
2083
2084 static int
imx_uart_console_setup(struct console * co,char * options)2085 imx_uart_console_setup(struct console *co, char *options)
2086 {
2087 struct imx_port *sport;
2088 int baud = 9600;
2089 int bits = 8;
2090 int parity = 'n';
2091 int flow = 'n';
2092 int retval;
2093
2094 /*
2095 * Check whether an invalid uart number has been specified, and
2096 * if so, search for the first available port that does have
2097 * console support.
2098 */
2099 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2100 co->index = 0;
2101 sport = imx_uart_ports[co->index];
2102 if (sport == NULL)
2103 return -ENODEV;
2104
2105 /* For setting the registers, we only need to enable the ipg clock. */
2106 retval = clk_prepare_enable(sport->clk_ipg);
2107 if (retval)
2108 goto error_console;
2109
2110 if (options)
2111 uart_parse_options(options, &baud, &parity, &bits, &flow);
2112 else
2113 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2114
2115 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2116
2117 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2118
2119 if (retval) {
2120 clk_disable_unprepare(sport->clk_ipg);
2121 goto error_console;
2122 }
2123
2124 retval = clk_prepare_enable(sport->clk_per);
2125 if (retval)
2126 clk_disable_unprepare(sport->clk_ipg);
2127
2128 error_console:
2129 return retval;
2130 }
2131
2132 static int
imx_uart_console_exit(struct console * co)2133 imx_uart_console_exit(struct console *co)
2134 {
2135 struct imx_port *sport = imx_uart_ports[co->index];
2136
2137 clk_disable_unprepare(sport->clk_per);
2138 clk_disable_unprepare(sport->clk_ipg);
2139
2140 return 0;
2141 }
2142
2143 static struct uart_driver imx_uart_uart_driver;
2144 static struct console imx_uart_console = {
2145 .name = DEV_NAME,
2146 .write = imx_uart_console_write,
2147 .device = uart_console_device,
2148 .setup = imx_uart_console_setup,
2149 .exit = imx_uart_console_exit,
2150 .flags = CON_PRINTBUFFER,
2151 .index = -1,
2152 .data = &imx_uart_uart_driver,
2153 };
2154
2155 #define IMX_CONSOLE &imx_uart_console
2156
2157 #else
2158 #define IMX_CONSOLE NULL
2159 #endif
2160
2161 static struct uart_driver imx_uart_uart_driver = {
2162 .owner = THIS_MODULE,
2163 .driver_name = DRIVER_NAME,
2164 .dev_name = DEV_NAME,
2165 .major = SERIAL_IMX_MAJOR,
2166 .minor = MINOR_START,
2167 .nr = ARRAY_SIZE(imx_uart_ports),
2168 .cons = IMX_CONSOLE,
2169 };
2170
imx_trigger_start_tx(struct hrtimer * t)2171 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2172 {
2173 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2174 unsigned long flags;
2175
2176 spin_lock_irqsave(&sport->port.lock, flags);
2177 if (sport->tx_state == WAIT_AFTER_RTS)
2178 imx_uart_start_tx(&sport->port);
2179 spin_unlock_irqrestore(&sport->port.lock, flags);
2180
2181 return HRTIMER_NORESTART;
2182 }
2183
imx_trigger_stop_tx(struct hrtimer * t)2184 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2185 {
2186 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2187 unsigned long flags;
2188
2189 spin_lock_irqsave(&sport->port.lock, flags);
2190 if (sport->tx_state == WAIT_AFTER_SEND)
2191 imx_uart_stop_tx(&sport->port);
2192 spin_unlock_irqrestore(&sport->port.lock, flags);
2193
2194 return HRTIMER_NORESTART;
2195 }
2196
2197 static const struct serial_rs485 imx_no_rs485 = {}; /* No RS485 if no RTS */
2198 static const struct serial_rs485 imx_rs485_supported = {
2199 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2200 SER_RS485_RX_DURING_TX,
2201 .delay_rts_before_send = 1,
2202 .delay_rts_after_send = 1,
2203 };
2204
2205 /* Default RX DMA buffer configuration */
2206 #define RX_DMA_PERIODS 16
2207 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2208
imx_uart_probe(struct platform_device * pdev)2209 static int imx_uart_probe(struct platform_device *pdev)
2210 {
2211 struct device_node *np = pdev->dev.of_node;
2212 struct imx_port *sport;
2213 void __iomem *base;
2214 u32 dma_buf_conf[2];
2215 int ret = 0;
2216 u32 ucr1;
2217 struct resource *res;
2218 int txirq, rxirq, rtsirq;
2219
2220 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2221 if (!sport)
2222 return -ENOMEM;
2223
2224 sport->devdata = of_device_get_match_data(&pdev->dev);
2225
2226 ret = of_alias_get_id(np, "serial");
2227 if (ret < 0) {
2228 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2229 return ret;
2230 }
2231 sport->port.line = ret;
2232
2233 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2234 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2235 sport->have_rtscts = 1;
2236
2237 if (of_get_property(np, "fsl,dte-mode", NULL))
2238 sport->dte_mode = 1;
2239
2240 if (of_get_property(np, "rts-gpios", NULL))
2241 sport->have_rtsgpio = 1;
2242
2243 if (of_get_property(np, "fsl,inverted-tx", NULL))
2244 sport->inverted_tx = 1;
2245
2246 if (of_get_property(np, "fsl,inverted-rx", NULL))
2247 sport->inverted_rx = 1;
2248
2249 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2250 sport->rx_period_length = dma_buf_conf[0];
2251 sport->rx_periods = dma_buf_conf[1];
2252 } else {
2253 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2254 sport->rx_periods = RX_DMA_PERIODS;
2255 }
2256
2257 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2258 dev_err(&pdev->dev, "serial%d out of range\n",
2259 sport->port.line);
2260 return -EINVAL;
2261 }
2262
2263 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2264 base = devm_ioremap_resource(&pdev->dev, res);
2265 if (IS_ERR(base))
2266 return PTR_ERR(base);
2267
2268 rxirq = platform_get_irq(pdev, 0);
2269 if (rxirq < 0)
2270 return rxirq;
2271 txirq = platform_get_irq_optional(pdev, 1);
2272 rtsirq = platform_get_irq_optional(pdev, 2);
2273
2274 sport->port.dev = &pdev->dev;
2275 sport->port.mapbase = res->start;
2276 sport->port.membase = base;
2277 sport->port.type = PORT_IMX;
2278 sport->port.iotype = UPIO_MEM;
2279 sport->port.irq = rxirq;
2280 sport->port.fifosize = 32;
2281 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2282 sport->port.ops = &imx_uart_pops;
2283 sport->port.rs485_config = imx_uart_rs485_config;
2284 /* RTS is required to control the RS485 transmitter */
2285 if (sport->have_rtscts || sport->have_rtsgpio)
2286 sport->port.rs485_supported = imx_rs485_supported;
2287 else
2288 sport->port.rs485_supported = imx_no_rs485;
2289 sport->port.flags = UPF_BOOT_AUTOCONF;
2290 timer_setup(&sport->timer, imx_uart_timeout, 0);
2291
2292 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2293 if (IS_ERR(sport->gpios))
2294 return PTR_ERR(sport->gpios);
2295
2296 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2297 if (IS_ERR(sport->clk_ipg)) {
2298 ret = PTR_ERR(sport->clk_ipg);
2299 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2300 return ret;
2301 }
2302
2303 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2304 if (IS_ERR(sport->clk_per)) {
2305 ret = PTR_ERR(sport->clk_per);
2306 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2307 return ret;
2308 }
2309
2310 sport->port.uartclk = clk_get_rate(sport->clk_per);
2311
2312 /* For register access, we only need to enable the ipg clock. */
2313 ret = clk_prepare_enable(sport->clk_ipg);
2314 if (ret) {
2315 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2316 return ret;
2317 }
2318
2319 /* initialize shadow register values */
2320 sport->ucr1 = readl(sport->port.membase + UCR1);
2321 sport->ucr2 = readl(sport->port.membase + UCR2);
2322 sport->ucr3 = readl(sport->port.membase + UCR3);
2323 sport->ucr4 = readl(sport->port.membase + UCR4);
2324 sport->ufcr = readl(sport->port.membase + UFCR);
2325
2326 ret = uart_get_rs485_mode(&sport->port);
2327 if (ret) {
2328 clk_disable_unprepare(sport->clk_ipg);
2329 return ret;
2330 }
2331
2332 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2333 (!sport->have_rtscts && !sport->have_rtsgpio))
2334 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2335
2336 /*
2337 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2338 * signal cannot be set low during transmission in case the
2339 * receiver is off (limitation of the i.MX UART IP).
2340 */
2341 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2342 sport->have_rtscts && !sport->have_rtsgpio &&
2343 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2344 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2345 dev_err(&pdev->dev,
2346 "low-active RTS not possible when receiver is off, enabling receiver\n");
2347
2348 /* Disable interrupts before requesting them */
2349 ucr1 = imx_uart_readl(sport, UCR1);
2350 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2351 imx_uart_writel(sport, ucr1, UCR1);
2352
2353 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2354 /*
2355 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2356 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2357 * and DCD (when they are outputs) or enables the respective
2358 * irqs. So set this bit early, i.e. before requesting irqs.
2359 */
2360 u32 ufcr = imx_uart_readl(sport, UFCR);
2361 if (!(ufcr & UFCR_DCEDTE))
2362 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2363
2364 /*
2365 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2366 * enabled later because they cannot be cleared
2367 * (confirmed on i.MX25) which makes them unusable.
2368 */
2369 imx_uart_writel(sport,
2370 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2371 UCR3);
2372
2373 } else {
2374 u32 ucr3 = UCR3_DSR;
2375 u32 ufcr = imx_uart_readl(sport, UFCR);
2376 if (ufcr & UFCR_DCEDTE)
2377 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2378
2379 if (!imx_uart_is_imx1(sport))
2380 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2381 imx_uart_writel(sport, ucr3, UCR3);
2382 }
2383
2384 clk_disable_unprepare(sport->clk_ipg);
2385
2386 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2387 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2388 sport->trigger_start_tx.function = imx_trigger_start_tx;
2389 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2390
2391 /*
2392 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2393 * chips only have one interrupt.
2394 */
2395 if (txirq > 0) {
2396 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2397 dev_name(&pdev->dev), sport);
2398 if (ret) {
2399 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2400 ret);
2401 return ret;
2402 }
2403
2404 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2405 dev_name(&pdev->dev), sport);
2406 if (ret) {
2407 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2408 ret);
2409 return ret;
2410 }
2411
2412 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2413 dev_name(&pdev->dev), sport);
2414 if (ret) {
2415 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2416 ret);
2417 return ret;
2418 }
2419 } else {
2420 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2421 dev_name(&pdev->dev), sport);
2422 if (ret) {
2423 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2424 return ret;
2425 }
2426 }
2427
2428 imx_uart_ports[sport->port.line] = sport;
2429
2430 platform_set_drvdata(pdev, sport);
2431
2432 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2433 }
2434
imx_uart_remove(struct platform_device * pdev)2435 static int imx_uart_remove(struct platform_device *pdev)
2436 {
2437 struct imx_port *sport = platform_get_drvdata(pdev);
2438
2439 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2440 }
2441
imx_uart_restore_context(struct imx_port * sport)2442 static void imx_uart_restore_context(struct imx_port *sport)
2443 {
2444 unsigned long flags;
2445
2446 spin_lock_irqsave(&sport->port.lock, flags);
2447 if (!sport->context_saved) {
2448 spin_unlock_irqrestore(&sport->port.lock, flags);
2449 return;
2450 }
2451
2452 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2453 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2454 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2455 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2456 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2457 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2458 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2459 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2460 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2461 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2462 sport->context_saved = false;
2463 spin_unlock_irqrestore(&sport->port.lock, flags);
2464 }
2465
imx_uart_save_context(struct imx_port * sport)2466 static void imx_uart_save_context(struct imx_port *sport)
2467 {
2468 unsigned long flags;
2469
2470 /* Save necessary regs */
2471 spin_lock_irqsave(&sport->port.lock, flags);
2472 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2473 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2474 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2475 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2476 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2477 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2478 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2479 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2480 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2481 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2482 sport->context_saved = true;
2483 spin_unlock_irqrestore(&sport->port.lock, flags);
2484 }
2485
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2486 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2487 {
2488 u32 ucr3;
2489
2490 ucr3 = imx_uart_readl(sport, UCR3);
2491 if (on) {
2492 imx_uart_writel(sport, USR1_AWAKE, USR1);
2493 ucr3 |= UCR3_AWAKEN;
2494 } else {
2495 ucr3 &= ~UCR3_AWAKEN;
2496 }
2497 imx_uart_writel(sport, ucr3, UCR3);
2498
2499 if (sport->have_rtscts) {
2500 u32 ucr1 = imx_uart_readl(sport, UCR1);
2501 if (on) {
2502 imx_uart_writel(sport, USR1_RTSD, USR1);
2503 ucr1 |= UCR1_RTSDEN;
2504 } else {
2505 ucr1 &= ~UCR1_RTSDEN;
2506 }
2507 imx_uart_writel(sport, ucr1, UCR1);
2508 }
2509 }
2510
imx_uart_suspend_noirq(struct device * dev)2511 static int imx_uart_suspend_noirq(struct device *dev)
2512 {
2513 struct imx_port *sport = dev_get_drvdata(dev);
2514
2515 imx_uart_save_context(sport);
2516
2517 clk_disable(sport->clk_ipg);
2518
2519 pinctrl_pm_select_sleep_state(dev);
2520
2521 return 0;
2522 }
2523
imx_uart_resume_noirq(struct device * dev)2524 static int imx_uart_resume_noirq(struct device *dev)
2525 {
2526 struct imx_port *sport = dev_get_drvdata(dev);
2527 int ret;
2528
2529 pinctrl_pm_select_default_state(dev);
2530
2531 ret = clk_enable(sport->clk_ipg);
2532 if (ret)
2533 return ret;
2534
2535 imx_uart_restore_context(sport);
2536
2537 return 0;
2538 }
2539
imx_uart_suspend(struct device * dev)2540 static int imx_uart_suspend(struct device *dev)
2541 {
2542 struct imx_port *sport = dev_get_drvdata(dev);
2543 int ret;
2544
2545 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2546 disable_irq(sport->port.irq);
2547
2548 ret = clk_prepare_enable(sport->clk_ipg);
2549 if (ret)
2550 return ret;
2551
2552 /* enable wakeup from i.MX UART */
2553 imx_uart_enable_wakeup(sport, true);
2554
2555 return 0;
2556 }
2557
imx_uart_resume(struct device * dev)2558 static int imx_uart_resume(struct device *dev)
2559 {
2560 struct imx_port *sport = dev_get_drvdata(dev);
2561
2562 /* disable wakeup from i.MX UART */
2563 imx_uart_enable_wakeup(sport, false);
2564
2565 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2566 enable_irq(sport->port.irq);
2567
2568 clk_disable_unprepare(sport->clk_ipg);
2569
2570 return 0;
2571 }
2572
imx_uart_freeze(struct device * dev)2573 static int imx_uart_freeze(struct device *dev)
2574 {
2575 struct imx_port *sport = dev_get_drvdata(dev);
2576
2577 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2578
2579 return clk_prepare_enable(sport->clk_ipg);
2580 }
2581
imx_uart_thaw(struct device * dev)2582 static int imx_uart_thaw(struct device *dev)
2583 {
2584 struct imx_port *sport = dev_get_drvdata(dev);
2585
2586 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2587
2588 clk_disable_unprepare(sport->clk_ipg);
2589
2590 return 0;
2591 }
2592
2593 static const struct dev_pm_ops imx_uart_pm_ops = {
2594 .suspend_noirq = imx_uart_suspend_noirq,
2595 .resume_noirq = imx_uart_resume_noirq,
2596 .freeze_noirq = imx_uart_suspend_noirq,
2597 .thaw_noirq = imx_uart_resume_noirq,
2598 .restore_noirq = imx_uart_resume_noirq,
2599 .suspend = imx_uart_suspend,
2600 .resume = imx_uart_resume,
2601 .freeze = imx_uart_freeze,
2602 .thaw = imx_uart_thaw,
2603 .restore = imx_uart_thaw,
2604 };
2605
2606 static struct platform_driver imx_uart_platform_driver = {
2607 .probe = imx_uart_probe,
2608 .remove = imx_uart_remove,
2609
2610 .driver = {
2611 .name = "imx-uart",
2612 .of_match_table = imx_uart_dt_ids,
2613 .pm = &imx_uart_pm_ops,
2614 },
2615 };
2616
imx_uart_init(void)2617 static int __init imx_uart_init(void)
2618 {
2619 int ret = uart_register_driver(&imx_uart_uart_driver);
2620
2621 if (ret)
2622 return ret;
2623
2624 ret = platform_driver_register(&imx_uart_platform_driver);
2625 if (ret != 0)
2626 uart_unregister_driver(&imx_uart_uart_driver);
2627
2628 return ret;
2629 }
2630
imx_uart_exit(void)2631 static void __exit imx_uart_exit(void)
2632 {
2633 platform_driver_unregister(&imx_uart_platform_driver);
2634 uart_unregister_driver(&imx_uart_uart_driver);
2635 }
2636
2637 module_init(imx_uart_init);
2638 module_exit(imx_uart_exit);
2639
2640 MODULE_AUTHOR("Sascha Hauer");
2641 MODULE_DESCRIPTION("IMX generic serial port driver");
2642 MODULE_LICENSE("GPL");
2643 MODULE_ALIAS("platform:imx-uart");
2644
