1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 *
5 * Based on drivers/tty/serial/8250/8250_pci.c,
6 *
7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23
24 #include <asm/byteorder.h>
25
26 #include "8250.h"
27
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea
35
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
43 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
44 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
45
46 #define UART_EXAR_INT0 0x80
47 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
48 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */
49 #define UART_EXAR_DVID 0x8d /* Device identification */
50
51 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
52 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
53 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
54 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
55 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
56 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
57 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
58
59 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
61
62 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
63 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
64 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
65 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
66 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
67 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
68 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
69 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
70 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
71 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
72 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
73 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
74
75 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
76
77 /*
78 * IOT2040 MPIO wiring semantics:
79 *
80 * MPIO Port Function
81 * ---- ---- --------
82 * 0 2 Mode bit 0
83 * 1 2 Mode bit 1
84 * 2 2 Terminate bus
85 * 3 - <reserved>
86 * 4 3 Mode bit 0
87 * 5 3 Mode bit 1
88 * 6 3 Terminate bus
89 * 7 - <reserved>
90 * 8 2 Enable
91 * 9 3 Enable
92 * 10 - Red LED
93 * 11..15 - <unused>
94 */
95
96 /* IOT2040 MPIOs 0..7 */
97 #define IOT2040_UART_MODE_RS232 0x01
98 #define IOT2040_UART_MODE_RS485 0x02
99 #define IOT2040_UART_MODE_RS422 0x03
100 #define IOT2040_UART_TERMINATE_BUS 0x04
101
102 #define IOT2040_UART1_MASK 0x0f
103 #define IOT2040_UART2_SHIFT 4
104
105 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
106 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
107
108 /* IOT2040 MPIOs 8..15 */
109 #define IOT2040_UARTS_ENABLE 0x03
110 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
111
112 struct exar8250;
113
114 struct exar8250_platform {
115 int (*rs485_config)(struct uart_port *port, struct ktermios *termios,
116 struct serial_rs485 *rs485);
117 const struct serial_rs485 *rs485_supported;
118 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
119 void (*unregister_gpio)(struct uart_8250_port *);
120 };
121
122 /**
123 * struct exar8250_board - board information
124 * @num_ports: number of serial ports
125 * @reg_shift: describes UART register mapping in PCI memory
126 * @setup: quirk run at ->probe() stage
127 * @exit: quirk run at ->remove() stage
128 */
129 struct exar8250_board {
130 unsigned int num_ports;
131 unsigned int reg_shift;
132 int (*setup)(struct exar8250 *, struct pci_dev *,
133 struct uart_8250_port *, int);
134 void (*exit)(struct pci_dev *pcidev);
135 };
136
137 struct exar8250 {
138 unsigned int nr;
139 struct exar8250_board *board;
140 void __iomem *virt;
141 int line[];
142 };
143
exar_pm(struct uart_port * port,unsigned int state,unsigned int old)144 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
145 {
146 /*
147 * Exar UARTs have a SLEEP register that enables or disables each UART
148 * to enter sleep mode separately. On the XR17V35x the register
149 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
150 * the UART channel may only write to the corresponding bit.
151 */
152 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
153 }
154
155 /*
156 * XR17V35x UARTs have an extra fractional divisor register (DLD)
157 * Calculate divisor with extra 4-bit fractional portion
158 */
xr17v35x_get_divisor(struct uart_port * p,unsigned int baud,unsigned int * frac)159 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
160 unsigned int *frac)
161 {
162 unsigned int quot_16;
163
164 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
165 *frac = quot_16 & 0x0f;
166
167 return quot_16 >> 4;
168 }
169
xr17v35x_set_divisor(struct uart_port * p,unsigned int baud,unsigned int quot,unsigned int quot_frac)170 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
171 unsigned int quot, unsigned int quot_frac)
172 {
173 serial8250_do_set_divisor(p, baud, quot, quot_frac);
174
175 /* Preserve bits not related to baudrate; DLD[7:4]. */
176 quot_frac |= serial_port_in(p, 0x2) & 0xf0;
177 serial_port_out(p, 0x2, quot_frac);
178 }
179
xr17v35x_startup(struct uart_port * port)180 static int xr17v35x_startup(struct uart_port *port)
181 {
182 /*
183 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
184 * MCR [7:5] and MSR [7:0]
185 */
186 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
187
188 /*
189 * Make sure all interrups are masked until initialization is
190 * complete and the FIFOs are cleared
191 */
192 serial_port_out(port, UART_IER, 0);
193
194 return serial8250_do_startup(port);
195 }
196
exar_shutdown(struct uart_port * port)197 static void exar_shutdown(struct uart_port *port)
198 {
199 bool tx_complete = false;
200 struct uart_8250_port *up = up_to_u8250p(port);
201 struct circ_buf *xmit = &port->state->xmit;
202 int i = 0;
203 u16 lsr;
204
205 do {
206 lsr = serial_in(up, UART_LSR);
207 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
208 tx_complete = true;
209 else
210 tx_complete = false;
211 usleep_range(1000, 1100);
212 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
213
214 serial8250_do_shutdown(port);
215 }
216
default_setup(struct exar8250 * priv,struct pci_dev * pcidev,int idx,unsigned int offset,struct uart_8250_port * port)217 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
218 int idx, unsigned int offset,
219 struct uart_8250_port *port)
220 {
221 const struct exar8250_board *board = priv->board;
222 unsigned int bar = 0;
223 unsigned char status;
224
225 port->port.iotype = UPIO_MEM;
226 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
227 port->port.membase = priv->virt + offset;
228 port->port.regshift = board->reg_shift;
229
230 /*
231 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
232 * with when DLAB is set which will cause the device to incorrectly match
233 * and assign port type to PORT_16650. The EFR for this UART is found
234 * at offset 0x09. Instead check the Deice ID (DVID) register
235 * for a 2, 4 or 8 port UART.
236 */
237 status = readb(port->port.membase + UART_EXAR_DVID);
238 if (status == 0x82 || status == 0x84 || status == 0x88) {
239 port->port.type = PORT_XR17V35X;
240
241 port->port.get_divisor = xr17v35x_get_divisor;
242 port->port.set_divisor = xr17v35x_set_divisor;
243
244 port->port.startup = xr17v35x_startup;
245 } else {
246 port->port.type = PORT_XR17D15X;
247 }
248
249 port->port.pm = exar_pm;
250 port->port.shutdown = exar_shutdown;
251
252 return 0;
253 }
254
255 static int
pci_fastcom335_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)256 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
257 struct uart_8250_port *port, int idx)
258 {
259 unsigned int offset = idx * 0x200;
260 unsigned int baud = 1843200;
261 u8 __iomem *p;
262 int err;
263
264 port->port.uartclk = baud * 16;
265
266 err = default_setup(priv, pcidev, idx, offset, port);
267 if (err)
268 return err;
269
270 p = port->port.membase;
271
272 writeb(0x00, p + UART_EXAR_8XMODE);
273 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
274 writeb(32, p + UART_EXAR_TXTRG);
275 writeb(32, p + UART_EXAR_RXTRG);
276
277 /*
278 * Setup Multipurpose Input/Output pins.
279 */
280 if (idx == 0) {
281 switch (pcidev->device) {
282 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
283 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
284 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
285 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
286 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
287 break;
288 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
289 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
290 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
291 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
292 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
293 break;
294 }
295 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
296 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
297 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
298 }
299
300 return 0;
301 }
302
303 static int
pci_connect_tech_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)304 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
305 struct uart_8250_port *port, int idx)
306 {
307 unsigned int offset = idx * 0x200;
308 unsigned int baud = 1843200;
309
310 port->port.uartclk = baud * 16;
311 return default_setup(priv, pcidev, idx, offset, port);
312 }
313
314 static int
pci_xr17c154_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)315 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
316 struct uart_8250_port *port, int idx)
317 {
318 unsigned int offset = idx * 0x200;
319 unsigned int baud = 921600;
320
321 port->port.uartclk = baud * 16;
322 return default_setup(priv, pcidev, idx, offset, port);
323 }
324
setup_gpio(struct pci_dev * pcidev,u8 __iomem * p)325 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
326 {
327 /*
328 * The Commtech adapters required the MPIOs to be driven low. The Exar
329 * devices will export them as GPIOs, so we pre-configure them safely
330 * as inputs.
331 */
332
333 u8 dir = 0x00;
334
335 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
336 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
337 // Configure GPIO as inputs for Commtech adapters
338 dir = 0xff;
339 } else {
340 // Configure GPIO as outputs for SeaLevel adapters
341 dir = 0x00;
342 }
343
344 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
345 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
346 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
347 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
348 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
349 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
350 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
351 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
352 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
353 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
354 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
355 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
356 }
357
__xr17v35x_register_gpio(struct pci_dev * pcidev,const struct software_node * node)358 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
359 const struct software_node *node)
360 {
361 struct platform_device *pdev;
362
363 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
364 if (!pdev)
365 return NULL;
366
367 pdev->dev.parent = &pcidev->dev;
368 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
369
370 if (device_add_software_node(&pdev->dev, node) < 0 ||
371 platform_device_add(pdev) < 0) {
372 platform_device_put(pdev);
373 return NULL;
374 }
375
376 return pdev;
377 }
378
__xr17v35x_unregister_gpio(struct platform_device * pdev)379 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
380 {
381 device_remove_software_node(&pdev->dev);
382 platform_device_unregister(pdev);
383 }
384
385 static const struct property_entry exar_gpio_properties[] = {
386 PROPERTY_ENTRY_U32("exar,first-pin", 0),
387 PROPERTY_ENTRY_U32("ngpios", 16),
388 { }
389 };
390
391 static const struct software_node exar_gpio_node = {
392 .properties = exar_gpio_properties,
393 };
394
xr17v35x_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)395 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
396 {
397 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
398 port->port.private_data =
399 __xr17v35x_register_gpio(pcidev, &exar_gpio_node);
400
401 return 0;
402 }
403
xr17v35x_unregister_gpio(struct uart_8250_port * port)404 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
405 {
406 if (!port->port.private_data)
407 return;
408
409 __xr17v35x_unregister_gpio(port->port.private_data);
410 port->port.private_data = NULL;
411 }
412
generic_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)413 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios,
414 struct serial_rs485 *rs485)
415 {
416 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
417 u8 __iomem *p = port->membase;
418 u8 value;
419
420 value = readb(p + UART_EXAR_FCTR);
421 if (is_rs485)
422 value |= UART_FCTR_EXAR_485;
423 else
424 value &= ~UART_FCTR_EXAR_485;
425
426 writeb(value, p + UART_EXAR_FCTR);
427
428 if (is_rs485)
429 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
430
431 return 0;
432 }
433
434 static const struct serial_rs485 generic_rs485_supported = {
435 .flags = SER_RS485_ENABLED,
436 };
437
438 static const struct exar8250_platform exar8250_default_platform = {
439 .register_gpio = xr17v35x_register_gpio,
440 .unregister_gpio = xr17v35x_unregister_gpio,
441 .rs485_config = generic_rs485_config,
442 .rs485_supported = &generic_rs485_supported,
443 };
444
iot2040_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)445 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios,
446 struct serial_rs485 *rs485)
447 {
448 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
449 u8 __iomem *p = port->membase;
450 u8 mask = IOT2040_UART1_MASK;
451 u8 mode, value;
452
453 if (is_rs485) {
454 if (rs485->flags & SER_RS485_RX_DURING_TX)
455 mode = IOT2040_UART_MODE_RS422;
456 else
457 mode = IOT2040_UART_MODE_RS485;
458
459 if (rs485->flags & SER_RS485_TERMINATE_BUS)
460 mode |= IOT2040_UART_TERMINATE_BUS;
461 } else {
462 mode = IOT2040_UART_MODE_RS232;
463 }
464
465 if (port->line == 3) {
466 mask <<= IOT2040_UART2_SHIFT;
467 mode <<= IOT2040_UART2_SHIFT;
468 }
469
470 value = readb(p + UART_EXAR_MPIOLVL_7_0);
471 value &= ~mask;
472 value |= mode;
473 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
474
475 return generic_rs485_config(port, termios, rs485);
476 }
477
478 static const struct serial_rs485 iot2040_rs485_supported = {
479 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS,
480 };
481
482 static const struct property_entry iot2040_gpio_properties[] = {
483 PROPERTY_ENTRY_U32("exar,first-pin", 10),
484 PROPERTY_ENTRY_U32("ngpios", 1),
485 { }
486 };
487
488 static const struct software_node iot2040_gpio_node = {
489 .properties = iot2040_gpio_properties,
490 };
491
iot2040_register_gpio(struct pci_dev * pcidev,struct uart_8250_port * port)492 static int iot2040_register_gpio(struct pci_dev *pcidev,
493 struct uart_8250_port *port)
494 {
495 u8 __iomem *p = port->port.membase;
496
497 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
498 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
499 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
500 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
501
502 port->port.private_data =
503 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
504
505 return 0;
506 }
507
508 static const struct exar8250_platform iot2040_platform = {
509 .rs485_config = iot2040_rs485_config,
510 .rs485_supported = &iot2040_rs485_supported,
511 .register_gpio = iot2040_register_gpio,
512 .unregister_gpio = xr17v35x_unregister_gpio,
513 };
514
515 /*
516 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
517 * IOT2020 doesn't have. Therefore it is sufficient to match on the common
518 * board name after the device was found.
519 */
520 static const struct dmi_system_id exar_platforms[] = {
521 {
522 .matches = {
523 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
524 },
525 .driver_data = (void *)&iot2040_platform,
526 },
527 {}
528 };
529
exar_get_platform(void)530 static const struct exar8250_platform *exar_get_platform(void)
531 {
532 const struct dmi_system_id *dmi_match;
533
534 dmi_match = dmi_first_match(exar_platforms);
535 if (dmi_match)
536 return dmi_match->driver_data;
537
538 return &exar8250_default_platform;
539 }
540
541 static int
pci_xr17v35x_setup(struct exar8250 * priv,struct pci_dev * pcidev,struct uart_8250_port * port,int idx)542 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
543 struct uart_8250_port *port, int idx)
544 {
545 const struct exar8250_platform *platform = exar_get_platform();
546 unsigned int offset = idx * 0x400;
547 unsigned int baud = 7812500;
548 u8 __iomem *p;
549 int ret;
550
551 port->port.uartclk = baud * 16;
552 port->port.rs485_config = platform->rs485_config;
553 port->port.rs485_supported = *(platform->rs485_supported);
554
555 /*
556 * Setup the UART clock for the devices on expansion slot to
557 * half the clock speed of the main chip (which is 125MHz)
558 */
559 if (idx >= 8)
560 port->port.uartclk /= 2;
561
562 ret = default_setup(priv, pcidev, idx, offset, port);
563 if (ret)
564 return ret;
565
566 p = port->port.membase;
567
568 writeb(0x00, p + UART_EXAR_8XMODE);
569 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
570 writeb(128, p + UART_EXAR_TXTRG);
571 writeb(128, p + UART_EXAR_RXTRG);
572
573 if (idx == 0) {
574 /* Setup Multipurpose Input/Output pins. */
575 setup_gpio(pcidev, p);
576
577 ret = platform->register_gpio(pcidev, port);
578 }
579
580 return ret;
581 }
582
pci_xr17v35x_exit(struct pci_dev * pcidev)583 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
584 {
585 const struct exar8250_platform *platform = exar_get_platform();
586 struct exar8250 *priv = pci_get_drvdata(pcidev);
587 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
588
589 platform->unregister_gpio(port);
590 }
591
exar_misc_clear(struct exar8250 * priv)592 static inline void exar_misc_clear(struct exar8250 *priv)
593 {
594 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
595 readb(priv->virt + UART_EXAR_INT0);
596
597 /* Clear INT0 for Expansion Interface slave ports, too */
598 if (priv->board->num_ports > 8)
599 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
600 }
601
602 /*
603 * These Exar UARTs have an extra interrupt indicator that could fire for a
604 * few interrupts that are not presented/cleared through IIR. One of which is
605 * a wakeup interrupt when coming out of sleep. These interrupts are only
606 * cleared by reading global INT0 or INT1 registers as interrupts are
607 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
608 * channel's address space, but for the sake of bus efficiency we register a
609 * dedicated handler at the PCI device level to handle them.
610 */
exar_misc_handler(int irq,void * data)611 static irqreturn_t exar_misc_handler(int irq, void *data)
612 {
613 exar_misc_clear(data);
614
615 return IRQ_HANDLED;
616 }
617
618 static int
exar_pci_probe(struct pci_dev * pcidev,const struct pci_device_id * ent)619 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
620 {
621 unsigned int nr_ports, i, bar = 0, maxnr;
622 struct exar8250_board *board;
623 struct uart_8250_port uart;
624 struct exar8250 *priv;
625 int rc;
626
627 board = (struct exar8250_board *)ent->driver_data;
628 if (!board)
629 return -EINVAL;
630
631 rc = pcim_enable_device(pcidev);
632 if (rc)
633 return rc;
634
635 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
636
637 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
638 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
639 else if (board->num_ports)
640 nr_ports = board->num_ports;
641 else
642 nr_ports = pcidev->device & 0x0f;
643
644 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
645 if (!priv)
646 return -ENOMEM;
647
648 priv->board = board;
649 priv->virt = pcim_iomap(pcidev, bar, 0);
650 if (!priv->virt)
651 return -ENOMEM;
652
653 pci_set_master(pcidev);
654
655 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
656 if (rc < 0)
657 return rc;
658
659 memset(&uart, 0, sizeof(uart));
660 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
661 uart.port.irq = pci_irq_vector(pcidev, 0);
662 uart.port.dev = &pcidev->dev;
663
664 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
665 IRQF_SHARED, "exar_uart", priv);
666 if (rc)
667 return rc;
668
669 /* Clear interrupts */
670 exar_misc_clear(priv);
671
672 for (i = 0; i < nr_ports && i < maxnr; i++) {
673 rc = board->setup(priv, pcidev, &uart, i);
674 if (rc) {
675 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
676 break;
677 }
678
679 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
680 uart.port.iobase, uart.port.irq, uart.port.iotype);
681
682 priv->line[i] = serial8250_register_8250_port(&uart);
683 if (priv->line[i] < 0) {
684 dev_err(&pcidev->dev,
685 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
686 uart.port.iobase, uart.port.irq,
687 uart.port.iotype, priv->line[i]);
688 break;
689 }
690 }
691 priv->nr = i;
692 pci_set_drvdata(pcidev, priv);
693 return 0;
694 }
695
exar_pci_remove(struct pci_dev * pcidev)696 static void exar_pci_remove(struct pci_dev *pcidev)
697 {
698 struct exar8250 *priv = pci_get_drvdata(pcidev);
699 unsigned int i;
700
701 for (i = 0; i < priv->nr; i++)
702 serial8250_unregister_port(priv->line[i]);
703
704 if (priv->board->exit)
705 priv->board->exit(pcidev);
706 }
707
exar_suspend(struct device * dev)708 static int __maybe_unused exar_suspend(struct device *dev)
709 {
710 struct pci_dev *pcidev = to_pci_dev(dev);
711 struct exar8250 *priv = pci_get_drvdata(pcidev);
712 unsigned int i;
713
714 for (i = 0; i < priv->nr; i++)
715 if (priv->line[i] >= 0)
716 serial8250_suspend_port(priv->line[i]);
717
718 /* Ensure that every init quirk is properly torn down */
719 if (priv->board->exit)
720 priv->board->exit(pcidev);
721
722 return 0;
723 }
724
exar_resume(struct device * dev)725 static int __maybe_unused exar_resume(struct device *dev)
726 {
727 struct exar8250 *priv = dev_get_drvdata(dev);
728 unsigned int i;
729
730 exar_misc_clear(priv);
731
732 for (i = 0; i < priv->nr; i++)
733 if (priv->line[i] >= 0)
734 serial8250_resume_port(priv->line[i]);
735
736 return 0;
737 }
738
739 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
740
741 static const struct exar8250_board pbn_fastcom335_2 = {
742 .num_ports = 2,
743 .setup = pci_fastcom335_setup,
744 };
745
746 static const struct exar8250_board pbn_fastcom335_4 = {
747 .num_ports = 4,
748 .setup = pci_fastcom335_setup,
749 };
750
751 static const struct exar8250_board pbn_fastcom335_8 = {
752 .num_ports = 8,
753 .setup = pci_fastcom335_setup,
754 };
755
756 static const struct exar8250_board pbn_connect = {
757 .setup = pci_connect_tech_setup,
758 };
759
760 static const struct exar8250_board pbn_exar_ibm_saturn = {
761 .num_ports = 1,
762 .setup = pci_xr17c154_setup,
763 };
764
765 static const struct exar8250_board pbn_exar_XR17C15x = {
766 .setup = pci_xr17c154_setup,
767 };
768
769 static const struct exar8250_board pbn_exar_XR17V35x = {
770 .setup = pci_xr17v35x_setup,
771 .exit = pci_xr17v35x_exit,
772 };
773
774 static const struct exar8250_board pbn_fastcom35x_2 = {
775 .num_ports = 2,
776 .setup = pci_xr17v35x_setup,
777 .exit = pci_xr17v35x_exit,
778 };
779
780 static const struct exar8250_board pbn_fastcom35x_4 = {
781 .num_ports = 4,
782 .setup = pci_xr17v35x_setup,
783 .exit = pci_xr17v35x_exit,
784 };
785
786 static const struct exar8250_board pbn_fastcom35x_8 = {
787 .num_ports = 8,
788 .setup = pci_xr17v35x_setup,
789 .exit = pci_xr17v35x_exit,
790 };
791
792 static const struct exar8250_board pbn_exar_XR17V4358 = {
793 .num_ports = 12,
794 .setup = pci_xr17v35x_setup,
795 .exit = pci_xr17v35x_exit,
796 };
797
798 static const struct exar8250_board pbn_exar_XR17V8358 = {
799 .num_ports = 16,
800 .setup = pci_xr17v35x_setup,
801 .exit = pci_xr17v35x_exit,
802 };
803
804 #define CONNECT_DEVICE(devid, sdevid, bd) { \
805 PCI_DEVICE_SUB( \
806 PCI_VENDOR_ID_EXAR, \
807 PCI_DEVICE_ID_EXAR_##devid, \
808 PCI_SUBVENDOR_ID_CONNECT_TECH, \
809 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
810 (kernel_ulong_t)&bd \
811 }
812
813 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
814
815 #define IBM_DEVICE(devid, sdevid, bd) { \
816 PCI_DEVICE_SUB( \
817 PCI_VENDOR_ID_EXAR, \
818 PCI_DEVICE_ID_EXAR_##devid, \
819 PCI_VENDOR_ID_IBM, \
820 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
821 (kernel_ulong_t)&bd \
822 }
823
824 static const struct pci_device_id exar_pci_tbl[] = {
825 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
826 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
827 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
828 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
829 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
830 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
831 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
832
833 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
834 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
835 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
836 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
837 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
838 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
839 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
840 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
841 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
842 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
843 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
844 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
845
846 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
847
848 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
849 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
850 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
851 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
852
853 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
854 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
855 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
856 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
857 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
858 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
859 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
860 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
861 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
862
863 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
864 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
865 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
866 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
867 { 0, }
868 };
869 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
870
871 static struct pci_driver exar_pci_driver = {
872 .name = "exar_serial",
873 .probe = exar_pci_probe,
874 .remove = exar_pci_remove,
875 .driver = {
876 .pm = &exar_pci_pm,
877 },
878 .id_table = exar_pci_tbl,
879 };
880 module_pci_driver(exar_pci_driver);
881
882 MODULE_LICENSE("GPL");
883 MODULE_DESCRIPTION("Exar Serial Driver");
884 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
885
