Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 14 of 14) sorted by relevance
| /Linux-v6.1/drivers/gpu/drm/radeon/ |
| D | cik.c | 7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
[all …]
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| D | cikd.h | 1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | nid.h | 497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | evergreen.c | 4527 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4531 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4535 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4541 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
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| D | sid.h | 1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | evergreend.h | 1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | si.c | 6078 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6082 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6086 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
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| D | r600d.h | 718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | r600.c | 3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
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| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | sid.h | 1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
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| D | gfx_v11_0.c | 5721 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
5729 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_gfx_eop_interrupt_state()
5778 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
5786 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_compute_eop_interrupt_state()
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| D | gfx_v9_0.c | 5521 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5568 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5574 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
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| D | gfx_v10_0.c | 8975 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
8981 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
9028 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
9034 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
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| D | gfx_v8_0.c | 6438 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
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