Searched refs:TEGRA234_CLK_PLLP_OUT0 (Results 1 – 2 of 2) sorted by relevance
88 #define TEGRA234_CLK_PLLP_OUT0 102U macro
751 &bpmp TEGRA234_CLK_PLLP_OUT0>;753 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;770 &bpmp TEGRA234_CLK_PLLP_OUT0>;772 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;789 &bpmp TEGRA234_CLK_PLLP_OUT0>;791 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;808 &bpmp TEGRA234_CLK_PLLP_OUT0>;810 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;827 &bpmp TEGRA234_CLK_PLLP_OUT0>;829 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;[all …]