Searched refs:TEGRA186_CLK_PLL_A_OUT0 (Results 1 – 2 of 2) sorted by relevance
192 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;252 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;266 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;280 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;294 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;308 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;322 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;334 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;346 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;358 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;[all …]
712 #define TEGRA186_CLK_PLL_A_OUT0 246 macro
