Searched refs:STMP_OFFSET_REG_SET (Results 1 – 10 of 10) sorted by relevance
103 ts->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_map_ts_channel()285 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_setup_touch_detection()307 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_x_pos()333 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_y_pos()359 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_prepare_pressure()376 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_enable_touch_detection()384 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_start_touch_event()452 ts->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_finish_touch_event()572 ts->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_ts_hw_init()
85 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()87 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET); in stmp3xxx_wdt_set_timeout()193 STMP_OFFSET_REG_SET); in stmp3xxx_alarm_irq_enable()195 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET); in stmp3xxx_alarm_irq_enable()345 STMP_OFFSET_REG_SET); in stmp3xxx_rtc_probe()
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()310 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()316 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()329 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()373 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()412 STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()178 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()441 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; in mxs_lradc_adc_configure_trigger()513 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()514 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()516 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET); in mxs_lradc_adc_buffer_preenable()
202 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()227 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_reset_chan()272 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()275 mxs_dma->base + HW_APBHX_CHANNEL_CTRL + STMP_OFFSET_REG_SET); in mxs_dma_pause_chan()688 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()690 mxs_dma->base + HW_APBHX_CTRL0 + STMP_OFFSET_REG_SET); in mxs_dma_init()695 mxs_dma->base + HW_APBHX_CTRL1 + STMP_OFFSET_REG_SET); in mxs_dma_init()
11 #define STMP_OFFSET_REG_SET 0x4 macro
52 writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET); in stmp_reset_block()
76 writel(BM_OCOTP_CTRL_RD_BANK_OPEN, otp->base + STMP_OFFSET_REG_SET); in mxs_ocotp_read()
77 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET); in timrot_irq_enable()
522 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()524 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); in mxs_mmc_enable_sdio_irq()
