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Searched refs:SSPP_VIG3 (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c141 status->sspp[SSPP_VIG3] = (value >> 10) & 0x3; in dpu_hw_get_danger_status()
238 status->sspp[SSPP_VIG3] = (value >> 10) & 0x1; in dpu_hw_get_safe_status()
Ddpu_hw_mdss.h114 SSPP_VIG3, enumerator
Ddpu_hw_ctl.c166 case SSPP_VIG3: in dpu_hw_ctl_update_pending_flush_sspp()
439 case SSPP_VIG3: in dpu_hw_ctl_setup_blendstage()
Ddpu_hw_catalog.c804 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
823 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
868 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
/Linux-v6.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_ctl.c300 case SSPP_VIG3: return MDP5_CTL_LAYER_REG_VIG3(stage); in mdp_ctl_blend_mask()
323 case SSPP_VIG3: return MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3; in mdp_ctl_blend_ext_mask()
451 case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3; in mdp_ctl_flush_mask_pipe()
Dmdp5_cfg.c206 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
458 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
Dmdp5_kms.c687 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in hwpipe_init() enumerator
Dmdp5.xml.h84 SSPP_VIG3 = 9, enumerator
558 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]); in __offset_PIPE()